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[linux/fpc-iii.git] / include / asm-mips / mach-au1x00 / au1xxx_ide.h
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1 /*
2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
33 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34 #define DMA_WAIT_TIMEOUT 100
35 #define NUM_DESCRIPTORS PRD_ENTRIES
36 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37 #define NUM_DESCRIPTORS 2
38 #endif
40 #ifndef AU1XXX_ATA_RQSIZE
41 #define AU1XXX_ATA_RQSIZE 128
42 #endif
44 /* Disable Burstable-Support for DBDMA */
45 #ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46 #define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47 #endif
49 #ifdef CONFIG_PM
51 * This will enable the device to be powered up when write() or read()
52 * is called. If this is not defined, the driver will return -EBUSY.
54 #define WAKE_ON_ACCESS 1
56 typedef struct
58 spinlock_t lock; /* Used to block on state transitions */
59 au1xxx_power_dev_t *dev; /* Power Managers device structure */
60 unsigned stopped; /* USed to signaling device is stopped */
61 } pm_state;
62 #endif
65 typedef struct
67 u32 tx_dev_id, rx_dev_id, target_dev_id;
68 u32 tx_chan, rx_chan;
69 void *tx_desc_head, *rx_desc_head;
70 ide_hwif_t *hwif;
71 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
72 ide_drive_t *drive;
73 u8 white_list, black_list;
74 struct dbdma_cmd *dma_table_cpu;
75 dma_addr_t dma_table_dma;
76 #endif
77 int irq;
78 u32 regbase;
79 #ifdef CONFIG_PM
80 pm_state pm;
81 #endif
82 } _auide_hwif;
84 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
85 /* HD white list */
86 static const struct drive_list_entry dma_white_list [] = {
88 * Hitachi
90 { "HITACHI_DK14FA-20" , NULL },
91 { "HTS726060M9AT00" , NULL },
93 * Maxtor
95 { "Maxtor 6E040L0" , NULL },
96 { "Maxtor 6Y080P0" , NULL },
97 { "Maxtor 6Y160P0" , NULL },
99 * Seagate
101 { "ST3120026A" , NULL },
102 { "ST320014A" , NULL },
103 { "ST94011A" , NULL },
104 { "ST340016A" , NULL },
106 * Western Digital
108 { "WDC WD400UE-00HCT0" , NULL },
109 { "WDC WD400JB-00JJC0" , NULL },
110 { NULL , NULL }
113 /* HD black list */
114 static const struct drive_list_entry dma_black_list [] = {
116 * Western Digital
118 { "WDC WD100EB-00CGH0" , NULL },
119 { "WDC WD200BB-00AUA1" , NULL },
120 { "WDC AC24300L" , NULL },
121 { NULL , NULL }
123 #endif
125 /*******************************************************************************
126 * PIO Mode timing calculation : *
128 * Static Bus Spec ATA Spec *
129 * Tcsoe = t1 *
130 * Toecs = t9 *
131 * Twcs = t9 *
132 * Tcsh = t2i | t2 *
133 * Tcsoff = t2i | t2 *
134 * Twp = t2 *
135 * Tcsw = t1 *
136 * Tpm = 0 *
137 * Ta = t1+t2 *
138 *******************************************************************************/
140 #define TCSOE_MASK (0x07<<29)
141 #define TOECS_MASK (0x07<<26)
142 #define TWCS_MASK (0x07<<28)
143 #define TCSH_MASK (0x0F<<24)
144 #define TCSOFF_MASK (0x07<<20)
145 #define TWP_MASK (0x3F<<14)
146 #define TCSW_MASK (0x0F<<10)
147 #define TPM_MASK (0x0F<<6)
148 #define TA_MASK (0x3F<<0)
149 #define TS_MASK (1<<8)
151 /* Timing parameters PIO mode 0 */
152 #define SBC_IDE_PIO0_TCSOE (0x04<<29)
153 #define SBC_IDE_PIO0_TOECS (0x01<<26)
154 #define SBC_IDE_PIO0_TWCS (0x02<<28)
155 #define SBC_IDE_PIO0_TCSH (0x08<<24)
156 #define SBC_IDE_PIO0_TCSOFF (0x07<<20)
157 #define SBC_IDE_PIO0_TWP (0x10<<14)
158 #define SBC_IDE_PIO0_TCSW (0x04<<10)
159 #define SBC_IDE_PIO0_TPM (0x0<<6)
160 #define SBC_IDE_PIO0_TA (0x15<<0)
161 /* Timing parameters PIO mode 1 */
162 #define SBC_IDE_PIO1_TCSOE (0x03<<29)
163 #define SBC_IDE_PIO1_TOECS (0x01<<26)
164 #define SBC_IDE_PIO1_TWCS (0x01<<28)
165 #define SBC_IDE_PIO1_TCSH (0x06<<24)
166 #define SBC_IDE_PIO1_TCSOFF (0x06<<20)
167 #define SBC_IDE_PIO1_TWP (0x08<<14)
168 #define SBC_IDE_PIO1_TCSW (0x03<<10)
169 #define SBC_IDE_PIO1_TPM (0x00<<6)
170 #define SBC_IDE_PIO1_TA (0x0B<<0)
171 /* Timing parameters PIO mode 2 */
172 #define SBC_IDE_PIO2_TCSOE (0x05<<29)
173 #define SBC_IDE_PIO2_TOECS (0x01<<26)
174 #define SBC_IDE_PIO2_TWCS (0x01<<28)
175 #define SBC_IDE_PIO2_TCSH (0x07<<24)
176 #define SBC_IDE_PIO2_TCSOFF (0x07<<20)
177 #define SBC_IDE_PIO2_TWP (0x1F<<14)
178 #define SBC_IDE_PIO2_TCSW (0x05<<10)
179 #define SBC_IDE_PIO2_TPM (0x00<<6)
180 #define SBC_IDE_PIO2_TA (0x22<<0)
181 /* Timing parameters PIO mode 3 */
182 #define SBC_IDE_PIO3_TCSOE (0x05<<29)
183 #define SBC_IDE_PIO3_TOECS (0x01<<26)
184 #define SBC_IDE_PIO3_TWCS (0x01<<28)
185 #define SBC_IDE_PIO3_TCSH (0x0D<<24)
186 #define SBC_IDE_PIO3_TCSOFF (0x0D<<20)
187 #define SBC_IDE_PIO3_TWP (0x15<<14)
188 #define SBC_IDE_PIO3_TCSW (0x05<<10)
189 #define SBC_IDE_PIO3_TPM (0x00<<6)
190 #define SBC_IDE_PIO3_TA (0x1A<<0)
191 /* Timing parameters PIO mode 4 */
192 #define SBC_IDE_PIO4_TCSOE (0x04<<29)
193 #define SBC_IDE_PIO4_TOECS (0x01<<26)
194 #define SBC_IDE_PIO4_TWCS (0x01<<28)
195 #define SBC_IDE_PIO4_TCSH (0x04<<24)
196 #define SBC_IDE_PIO4_TCSOFF (0x04<<20)
197 #define SBC_IDE_PIO4_TWP (0x0D<<14)
198 #define SBC_IDE_PIO4_TCSW (0x03<<10)
199 #define SBC_IDE_PIO4_TPM (0x00<<6)
200 #define SBC_IDE_PIO4_TA (0x12<<0)
201 /* Timing parameters MDMA mode 0 */
202 #define SBC_IDE_MDMA0_TCSOE (0x03<<29)
203 #define SBC_IDE_MDMA0_TOECS (0x01<<26)
204 #define SBC_IDE_MDMA0_TWCS (0x01<<28)
205 #define SBC_IDE_MDMA0_TCSH (0x07<<24)
206 #define SBC_IDE_MDMA0_TCSOFF (0x07<<20)
207 #define SBC_IDE_MDMA0_TWP (0x0C<<14)
208 #define SBC_IDE_MDMA0_TCSW (0x03<<10)
209 #define SBC_IDE_MDMA0_TPM (0x00<<6)
210 #define SBC_IDE_MDMA0_TA (0x0F<<0)
211 /* Timing parameters MDMA mode 1 */
212 #define SBC_IDE_MDMA1_TCSOE (0x05<<29)
213 #define SBC_IDE_MDMA1_TOECS (0x01<<26)
214 #define SBC_IDE_MDMA1_TWCS (0x01<<28)
215 #define SBC_IDE_MDMA1_TCSH (0x05<<24)
216 #define SBC_IDE_MDMA1_TCSOFF (0x05<<20)
217 #define SBC_IDE_MDMA1_TWP (0x0F<<14)
218 #define SBC_IDE_MDMA1_TCSW (0x05<<10)
219 #define SBC_IDE_MDMA1_TPM (0x00<<6)
220 #define SBC_IDE_MDMA1_TA (0x15<<0)
221 /* Timing parameters MDMA mode 2 */
222 #define SBC_IDE_MDMA2_TCSOE (0x04<<29)
223 #define SBC_IDE_MDMA2_TOECS (0x01<<26)
224 #define SBC_IDE_MDMA2_TWCS (0x01<<28)
225 #define SBC_IDE_MDMA2_TCSH (0x04<<24)
226 #define SBC_IDE_MDMA2_TCSOFF (0x04<<20)
227 #define SBC_IDE_MDMA2_TWP (0x0D<<14)
228 #define SBC_IDE_MDMA2_TCSW (0x04<<10)
229 #define SBC_IDE_MDMA2_TPM (0x00<<6)
230 #define SBC_IDE_MDMA2_TA (0x12<<0)
232 #define SBC_IDE_TIMING(mode) \
233 SBC_IDE_##mode##_TWCS | \
234 SBC_IDE_##mode##_TCSH | \
235 SBC_IDE_##mode##_TCSOFF | \
236 SBC_IDE_##mode##_TWP | \
237 SBC_IDE_##mode##_TCSW | \
238 SBC_IDE_##mode##_TPM | \
239 SBC_IDE_##mode##_TA