Linux 2.6.25.20
[linux/fpc-iii.git] / include / asm-ppc / system.h
blob0593cb889d45306cf6dac6f5b837ccbca081935f
1 /*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4 #ifndef __PPC_SYSTEM_H
5 #define __PPC_SYSTEM_H
7 #include <linux/kernel.h>
9 #include <asm/hw_irq.h>
12 * Memory barrier.
13 * The sync instruction guarantees that all memory accesses initiated
14 * by this processor have been performed (with respect to all other
15 * mechanisms that access memory). The eieio instruction is a barrier
16 * providing an ordering (separately) for (a) cacheable stores and (b)
17 * loads and stores to non-cacheable memory (e.g. I/O devices).
19 * mb() prevents loads and stores being reordered across this point.
20 * rmb() prevents loads being reordered across this point.
21 * wmb() prevents stores being reordered across this point.
22 * read_barrier_depends() prevents data-dependent loads being reordered
23 * across this point (nop on PPC).
25 * We can use the eieio instruction for wmb, but since it doesn't
26 * give any ordering guarantees about loads, we have to use the
27 * stronger but slower sync instruction for mb and rmb.
29 #define mb() __asm__ __volatile__ ("sync" : : : "memory")
30 #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
31 #define wmb() __asm__ __volatile__ ("eieio" : : : "memory")
32 #define read_barrier_depends() do { } while(0)
34 #define set_mb(var, value) do { var = value; mb(); } while (0)
36 #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
37 #ifdef CONFIG_SMP
38 #define smp_mb() mb()
39 #define smp_rmb() rmb()
40 #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
41 #define smp_read_barrier_depends() read_barrier_depends()
42 #else
43 #define smp_mb() barrier()
44 #define smp_rmb() barrier()
45 #define smp_wmb() barrier()
46 #define smp_read_barrier_depends() do { } while(0)
47 #endif /* CONFIG_SMP */
49 #ifdef __KERNEL__
50 struct task_struct;
51 struct pt_regs;
53 extern void print_backtrace(unsigned long *);
54 extern void show_regs(struct pt_regs * regs);
55 extern void flush_instruction_cache(void);
56 extern void hard_reset_now(void);
57 extern void poweroff_now(void);
58 extern int set_dabr(unsigned long dabr);
59 #ifdef CONFIG_6xx
60 extern long _get_L2CR(void);
61 extern long _get_L3CR(void);
62 extern void _set_L2CR(unsigned long);
63 extern void _set_L3CR(unsigned long);
64 #else
65 #define _get_L2CR() 0L
66 #define _get_L3CR() 0L
67 #define _set_L2CR(val) do { } while(0)
68 #define _set_L3CR(val) do { } while(0)
69 #endif
70 extern void via_cuda_init(void);
71 extern void pmac_nvram_init(void);
72 extern void chrp_nvram_init(void);
73 extern void read_rtc_time(void);
74 extern void pmac_find_display(void);
75 extern void giveup_fpu(struct task_struct *);
76 extern void disable_kernel_fp(void);
77 extern void enable_kernel_fp(void);
78 extern void flush_fp_to_thread(struct task_struct *);
79 extern void enable_kernel_altivec(void);
80 extern void giveup_altivec(struct task_struct *);
81 extern void load_up_altivec(struct task_struct *);
82 extern int emulate_altivec(struct pt_regs *);
83 extern void giveup_spe(struct task_struct *);
84 extern void load_up_spe(struct task_struct *);
85 extern int fix_alignment(struct pt_regs *);
86 extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
87 extern void cvt_df(double *from, float *to, struct thread_struct *thread);
89 #ifndef CONFIG_SMP
90 extern void discard_lazy_cpu_state(void);
91 #else
92 static inline void discard_lazy_cpu_state(void)
95 #endif
97 #ifdef CONFIG_ALTIVEC
98 extern void flush_altivec_to_thread(struct task_struct *);
99 #else
100 static inline void flush_altivec_to_thread(struct task_struct *t)
103 #endif
105 #ifdef CONFIG_SPE
106 extern void flush_spe_to_thread(struct task_struct *);
107 #else
108 static inline void flush_spe_to_thread(struct task_struct *t)
111 #endif
113 extern int call_rtas(const char *, int, int, unsigned long *, ...);
114 extern void cacheable_memzero(void *p, unsigned int nb);
115 extern void *cacheable_memcpy(void *, const void *, unsigned int);
116 extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
117 extern void bad_page_fault(struct pt_regs *, unsigned long, int);
118 extern int die(const char *, struct pt_regs *, long);
119 extern void _exception(int, struct pt_regs *, int, unsigned long);
120 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
122 #ifdef CONFIG_BOOKE_WDT
123 extern u32 booke_wdt_enabled;
124 extern u32 booke_wdt_period;
125 #endif /* CONFIG_BOOKE_WDT */
127 struct device_node;
128 extern void note_scsi_host(struct device_node *, void *);
130 extern struct task_struct *__switch_to(struct task_struct *,
131 struct task_struct *);
132 #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
134 struct thread_struct;
135 extern struct task_struct *_switch(struct thread_struct *prev,
136 struct thread_struct *next);
138 extern unsigned int rtas_data;
140 static __inline__ unsigned long
141 xchg_u32(volatile void *p, unsigned long val)
143 unsigned long prev;
145 __asm__ __volatile__ ("\n\
146 1: lwarx %0,0,%2 \n"
147 PPC405_ERR77(0,%2)
148 " stwcx. %3,0,%2 \n\
149 bne- 1b"
150 : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
151 : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
152 : "cc", "memory");
154 return prev;
158 * This function doesn't exist, so you'll get a linker error
159 * if something tries to do an invalid xchg().
161 extern void __xchg_called_with_bad_pointer(void);
163 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
165 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
167 switch (size) {
168 case 4:
169 return (unsigned long) xchg_u32(ptr, x);
170 #if 0 /* xchg_u64 doesn't exist on 32-bit PPC */
171 case 8:
172 return (unsigned long) xchg_u64(ptr, x);
173 #endif /* 0 */
175 __xchg_called_with_bad_pointer();
176 return x;
181 extern inline void * xchg_ptr(void * m, void * val)
183 return (void *) xchg_u32(m, (unsigned long) val);
187 #define __HAVE_ARCH_CMPXCHG 1
189 static __inline__ unsigned long
190 __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
192 unsigned int prev;
194 __asm__ __volatile__ ("\n\
195 1: lwarx %0,0,%2 \n\
196 cmpw 0,%0,%3 \n\
197 bne 2f \n"
198 PPC405_ERR77(0,%2)
199 " stwcx. %4,0,%2 \n\
200 bne- 1b\n"
201 #ifdef CONFIG_SMP
202 " sync\n"
203 #endif /* CONFIG_SMP */
204 "2:"
205 : "=&r" (prev), "=m" (*p)
206 : "r" (p), "r" (old), "r" (new), "m" (*p)
207 : "cc", "memory");
209 return prev;
212 static inline unsigned long
213 __cmpxchg_u32_local(volatile unsigned int *p, unsigned int old,
214 unsigned int new)
216 unsigned int prev;
218 __asm__ __volatile__ ("\n\
219 1: lwarx %0,0,%2 \n\
220 cmpw 0,%0,%3 \n\
221 bne 2f \n"
222 PPC405_ERR77(0,%2)
223 " stwcx. %4,0,%2 \n\
224 bne- 1b\n"
225 "2:"
226 : "=&r" (prev), "=m" (*p)
227 : "r" (p), "r" (old), "r" (new), "m" (*p)
228 : "cc", "memory");
230 return prev;
233 /* This function doesn't exist, so you'll get a linker error
234 if something tries to do an invalid cmpxchg(). */
235 extern void __cmpxchg_called_with_bad_pointer(void);
237 static __inline__ unsigned long
238 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
239 unsigned int size)
241 switch (size) {
242 case 4:
243 return __cmpxchg_u32(ptr, old, new);
244 #if 0 /* we don't have __cmpxchg_u64 on 32-bit PPC */
245 case 8:
246 return __cmpxchg_u64(ptr, old, new);
247 #endif /* 0 */
249 __cmpxchg_called_with_bad_pointer();
250 return old;
253 #define cmpxchg(ptr, o, n) \
254 ({ \
255 __typeof__(*(ptr)) _o_ = (o); \
256 __typeof__(*(ptr)) _n_ = (n); \
257 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
258 (unsigned long)_n_, sizeof(*(ptr))); \
261 #include <asm-generic/cmpxchg-local.h>
263 static inline unsigned long __cmpxchg_local(volatile void *ptr,
264 unsigned long old,
265 unsigned long new, int size)
267 switch (size) {
268 case 4:
269 return __cmpxchg_u32_local(ptr, old, new);
270 default:
271 return __cmpxchg_local_generic(ptr, old, new, size);
274 return old;
278 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
279 * them available.
281 #define cmpxchg_local(ptr, o, n) \
282 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
283 (unsigned long)(n), sizeof(*(ptr))))
284 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
286 #define arch_align_stack(x) (x)
288 #endif /* __KERNEL__ */
289 #endif /* __PPC_SYSTEM_H */