include/asm-v850/v850e_uartb.h

   1 /*
   2  * include/asm-v850/v850e_uartb.h -- V850E on-chip `UARTB' UART
   3  *
   4  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
   5  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General
   8  * Public License.  See the file COPYING in the main directory of this
   9  * archive for more details.
  10  *
  11  * Written by Miles Bader <miles@gnu.org>
  12  */
  13
  14 /* The V850E UARTB is basically a superset of the original V850E UART, but
  15    even where it's the same, the names and details have changed a bit.
  16    It's similar enough to use the same driver (v850e_uart.c), but the
  17    details have been abstracted slightly to do so.  */
  18
  19 #ifndef __V850_V850E_UARTB_H__
  20 #define __V850_V850E_UARTB_H__
  21
  22 \f
  23 /* Raw hardware interface.  */
  24
  25 #define V850E_UARTB_BASE_ADDR(n)        (0xFFFFFA00 + 0x10 * (n))
  26
  27 /* Addresses of specific UART control registers for channel N.  */
  28 #define V850E_UARTB_CTL0_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0x0)
  29 #define V850E_UARTB_CTL2_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0x2)
  30 #define V850E_UARTB_STR_ADDR(n)         (V850E_UARTB_BASE_ADDR(n) + 0x4)
  31 #define V850E_UARTB_RX_ADDR(n)          (V850E_UARTB_BASE_ADDR(n) + 0x6)
  32 #define V850E_UARTB_RXAP_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0x6)
  33 #define V850E_UARTB_TX_ADDR(n)          (V850E_UARTB_BASE_ADDR(n) + 0x8)
  34 #define V850E_UARTB_FIC0_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0xA)
  35 #define V850E_UARTB_FIC1_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0xB)
  36 #define V850E_UARTB_FIC2_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0xC)
  37 #define V850E_UARTB_FIS0_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0xE)
  38 #define V850E_UARTB_FIS1_ADDR(n)        (V850E_UARTB_BASE_ADDR(n) + 0xF)
  39
  40 /* UARTB control register 0 (general config).  */
  41 #define V850E_UARTB_CTL0(n)     (*(volatile u8 *)V850E_UARTB_CTL0_ADDR(n))
  42 /* Control bits for config registers.  */
  43 #define V850E_UARTB_CTL0_PWR            0x80    /* clock enable */
  44 #define V850E_UARTB_CTL0_TXE            0x40    /* transmit enable */
  45 #define V850E_UARTB_CTL0_RXE            0x20    /* receive enable */
  46 #define V850E_UARTB_CTL0_DIR            0x10    /*  */
  47 #define V850E_UARTB_CTL0_PS1            0x08    /* parity */
  48 #define V850E_UARTB_CTL0_PS0            0x04    /* parity */
  49 #define V850E_UARTB_CTL0_CL             0x02    /* char len 1:8bit, 0:7bit */
  50 #define V850E_UARTB_CTL0_SL             0x01    /* stop bit 1:2bit, 0:1bit */
  51 #define V850E_UARTB_CTL0_PS_MASK        0x0C    /* mask covering parity bits */
  52 #define V850E_UARTB_CTL0_PS_NONE        0x00    /* no parity */
  53 #define V850E_UARTB_CTL0_PS_ZERO        0x04    /* zero parity */
  54 #define V850E_UARTB_CTL0_PS_ODD         0x08    /* odd parity */
  55 #define V850E_UARTB_CTL0_PS_EVEN        0x0C    /* even parity */
  56 #define V850E_UARTB_CTL0_CL_8           0x02    /* char len 1:8bit, 0:7bit */
  57 #define V850E_UARTB_CTL0_SL_2           0x01    /* stop bit 1:2bit, 0:1bit */
  58
  59 /* UARTB control register 2 (clock divider).  */
  60 #define V850E_UARTB_CTL2(n)     (*(volatile u16 *)V850E_UARTB_CTL2_ADDR(n))
  61 #define V850E_UARTB_CTL2_MIN    4
  62 #define V850E_UARTB_CTL2_MAX    0xFFFF
  63
  64 /* UARTB serial interface status register.  */
  65 #define V850E_UARTB_STR(n)      (*(volatile u8 *)V850E_UARTB_STR_ADDR(n))
  66 /* Control bits for status registers.  */
  67 #define V850E_UARTB_STR_TSF     0x80    /* UBTX or FIFO exist data  */
  68 #define V850E_UARTB_STR_OVF     0x08    /* overflow error */
  69 #define V850E_UARTB_STR_PE      0x04    /* parity error */
  70 #define V850E_UARTB_STR_FE      0x02    /* framing error */
  71 #define V850E_UARTB_STR_OVE     0x01    /* overrun error */
  72
  73 /* UARTB receive data register.  */
  74 #define V850E_UARTB_RX(n)       (*(volatile u8 *)V850E_UARTB_RX_ADDR(n))
  75 #define V850E_UARTB_RXAP(n)     (*(volatile u16 *)V850E_UARTB_RXAP_ADDR(n))
  76 /* Control bits for status registers.  */
  77 #define V850E_UARTB_RXAP_PEF    0x0200 /* parity error */
  78 #define V850E_UARTB_RXAP_FEF    0x0100 /* framing error */
  79
  80 /* UARTB transmit data register.  */
  81 #define V850E_UARTB_TX(n)       (*(volatile u8 *)V850E_UARTB_TX_ADDR(n))
  82
  83 /* UARTB FIFO control register 0.  */
  84 #define V850E_UARTB_FIC0(n)     (*(volatile u8 *)V850E_UARTB_FIC0_ADDR(n))
  85
  86 /* UARTB FIFO control register 1.  */
  87 #define V850E_UARTB_FIC1(n)     (*(volatile u8 *)V850E_UARTB_FIC1_ADDR(n))
  88
  89 /* UARTB FIFO control register 2.  */
  90 #define V850E_UARTB_FIC2(n)     (*(volatile u16 *)V850E_UARTB_FIC2_ADDR(n))
  91
  92 /* UARTB FIFO status register 0.  */
  93 #define V850E_UARTB_FIS0(n)     (*(volatile u8 *)V850E_UARTB_FIS0_ADDR(n))
  94
  95 /* UARTB FIFO status register 1.  */
  96 #define V850E_UARTB_FIS1(n)     (*(volatile u8 *)V850E_UARTB_FIS1_ADDR(n))
  97
  98 \f
  99 /* Slightly abstract interface used by driver.  */
 100
 101
 102 /* Interrupts used by the UART.  */
 103
 104 /* Received when the most recently transmitted character has been sent.  */
 105 #define V850E_UART_TX_IRQ(chan)         IRQ_INTUBTIT (chan)
 106 /* Received when a new character has been received.  */
 107 #define V850E_UART_RX_IRQ(chan)         IRQ_INTUBTIR (chan)
 108
 109 /* Use by serial driver for information purposes.  */
 110 #define V850E_UART_BASE_ADDR(chan)      V850E_UARTB_BASE_ADDR(chan)
 111
 112
 113 /* UART clock generator interface.  */
 114
 115 /* This type encapsulates a particular uart frequency.  */
 116 typedef u16 v850e_uart_speed_t;
 117
 118 /* Calculate a uart speed from BAUD for this uart.  */
 119 static inline v850e_uart_speed_t v850e_uart_calc_speed (unsigned baud)
 120 {
 121         v850e_uart_speed_t speed;
 122
 123         /*
 124          * V850E/ME2 UARTB baud rate is determined by the value of UBCTL2
 125          * fx = V850E_UARTB_BASE_FREQ = CPU_CLOCK_FREQ/4
 126          * baud = fx / 2*speed   [ speed >= 4 ]
 127          */
 128         speed = V850E_UARTB_CTL2_MIN;
 129         while (((V850E_UARTB_BASE_FREQ / 2) / speed ) > baud)
 130                 speed++;
 131
 132         return speed;
 133 }
 134
 135 /* Return the current speed of uart channel CHAN.  */
 136 #define v850e_uart_speed(chan)              V850E_UARTB_CTL2 (chan)
 137
 138 /* Set the current speed of uart channel CHAN.  */
 139 #define v850e_uart_set_speed(chan, speed)   (V850E_UARTB_CTL2 (chan) = (speed))
 140
 141 /* Return true if SPEED1 and SPEED2 are the same.  */
 142 #define v850e_uart_speed_eq(speed1, speed2) ((speed1) == (speed2))
 143
 144 /* Minimum baud rate possible.  */
 145 #define v850e_uart_min_baud() \
 146    ((V850E_UARTB_BASE_FREQ / 2) / V850E_UARTB_CTL2_MAX)
 147
 148 /* Maximum baud rate possible.  The error is quite high at max, though.  */
 149 #define v850e_uart_max_baud() \
 150    ((V850E_UARTB_BASE_FREQ / 2) / V850E_UARTB_CTL2_MIN)
 151
 152 /* The `maximum' clock rate the uart can used, which is wanted (though not
 153    really used in any useful way) by the serial framework.  */
 154 #define v850e_uart_max_clock() \
 155    (V850E_UARTB_BASE_FREQ / 2)
 156
 157
 158 /* UART configuration interface.  */
 159
 160 /* Type of the uart config register; must be a scalar.  */
 161 typedef u16 v850e_uart_config_t;
 162
 163 /* The uart hardware config register for channel CHAN.  */
 164 #define V850E_UART_CONFIG(chan)         V850E_UARTB_CTL0 (chan)
 165
 166 /* This config bit set if the uart is enabled.  */
 167 #define V850E_UART_CONFIG_ENABLED       V850E_UARTB_CTL0_PWR
 168 /* If the uart _isn't_ enabled, store this value to it to do so.  */
 169 #define V850E_UART_CONFIG_INIT          V850E_UARTB_CTL0_PWR
 170 /* Store this config value to disable the uart channel completely.  */
 171 #define V850E_UART_CONFIG_FINI          0
 172
 173 /* Setting/clearing these bits enable/disable TX/RX, respectively (but
 174    otherwise generally leave things running).  */
 175 #define V850E_UART_CONFIG_RX_ENABLE     V850E_UARTB_CTL0_RXE
 176 #define V850E_UART_CONFIG_TX_ENABLE     V850E_UARTB_CTL0_TXE
 177
 178 /* These masks define which config bits affect TX/RX modes, respectively.  */
 179 #define V850E_UART_CONFIG_RX_BITS \
 180   (V850E_UARTB_CTL0_PS_MASK | V850E_UARTB_CTL0_CL_8)
 181 #define V850E_UART_CONFIG_TX_BITS \
 182   (V850E_UARTB_CTL0_PS_MASK | V850E_UARTB_CTL0_CL_8 | V850E_UARTB_CTL0_SL_2)
 183
 184 static inline v850e_uart_config_t v850e_uart_calc_config (unsigned cflags)
 185 {
 186         v850e_uart_config_t config = 0;
 187
 188         /* Figure out new configuration of control register.  */
 189         if (cflags & CSTOPB)
 190                 /* Number of stop bits, 1 or 2.  */
 191                 config |= V850E_UARTB_CTL0_SL_2;
 192         if ((cflags & CSIZE) == CS8)
 193                 /* Number of data bits, 7 or 8.  */
 194                 config |= V850E_UARTB_CTL0_CL_8;
 195         if (! (cflags & PARENB))
 196                 /* No parity check/generation.  */
 197                 config |= V850E_UARTB_CTL0_PS_NONE;
 198         else if (cflags & PARODD)
 199                 /* Odd parity check/generation.  */
 200                 config |= V850E_UARTB_CTL0_PS_ODD;
 201         else
 202                 /* Even parity check/generation.  */
 203                 config |= V850E_UARTB_CTL0_PS_EVEN;
 204         if (cflags & CREAD)
 205                 /* Reading enabled.  */
 206                 config |= V850E_UARTB_CTL0_RXE;
 207
 208         config |= V850E_UARTB_CTL0_PWR;
 209         config |= V850E_UARTB_CTL0_TXE; /* Writing is always enabled.  */
 210         config |= V850E_UARTB_CTL0_DIR; /* LSB first.  */
 211
 212         return config;
 213 }
 214
 215 /* This should delay as long as necessary for a recently written config
 216    setting to settle, before we turn the uart back on.  */
 217 static inline void
 218 v850e_uart_config_delay (v850e_uart_config_t config, v850e_uart_speed_t speed)
 219 {
 220         /* The UART may not be reset properly unless we wait at least 2
 221            `basic-clocks' until turning on the TXE/RXE bits again.
 222            A `basic clock' is the clock used by the baud-rate generator,
 223            i.e., the cpu clock divided by the 2^new_clk_divlog2.
 224            The loop takes 2 insns, so loop CYCLES / 2 times.  */
 225         register unsigned count = 1 << speed;
 226         while (--count != 0)
 227                 /* nothing */;
 228 }
 229
 230
 231 /* RX/TX interface.  */
 232
 233 /* Return true if all characters awaiting transmission on uart channel N
 234    have been transmitted.  */
 235 #define v850e_uart_xmit_done(n)                                               \
 236    (! (V850E_UARTB_STR(n) & V850E_UARTB_STR_TSF))
 237 /* Wait for this to be true.  */
 238 #define v850e_uart_wait_for_xmit_done(n)                                      \
 239    do { } while (! v850e_uart_xmit_done (n))
 240
 241 /* Return true if uart channel N is ready to transmit a character.  */
 242 #define v850e_uart_xmit_ok(n)                                                 \
 243    (v850e_uart_xmit_done(n) && v850e_uart_cts(n))
 244 /* Wait for this to be true.  */
 245 #define v850e_uart_wait_for_xmit_ok(n)                                        \
 246    do { } while (! v850e_uart_xmit_ok (n))
 247
 248 /* Write character CH to uart channel CHAN.  */
 249 #define v850e_uart_putc(chan, ch)       (V850E_UARTB_TX(chan) = (ch))
 250
 251 /* Return latest character read on channel CHAN.  */
 252 #define v850e_uart_getc(chan)           V850E_UARTB_RX (chan)
 253
 254 /* Return bit-mask of uart error status.  */
 255 #define v850e_uart_err(chan)            V850E_UARTB_STR (chan)
 256 /* Various error bits set in the error result.  */
 257 #define V850E_UART_ERR_OVERRUN          V850E_UARTB_STR_OVE
 258 #define V850E_UART_ERR_FRAME            V850E_UARTB_STR_FE
 259 #define V850E_UART_ERR_PARITY           V850E_UARTB_STR_PE
 260
 261
 262 #endif /* __V850_V850E_UARTB_H__ */