Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

   1 Device Tree Bindings for the Arasan SDHCI Controller
   2
   3   The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
   4   Only deviations are documented here.
   5
   6   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   7   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   8   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
   9   [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
  10
  11 Required Properties:
  12   - compatible: Compatibility string.  One of:
  13     - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
  14     - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
  15     - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
  16     - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
  17       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  18     - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
  19         Note: This binding has been deprecated and moved to [5].
  20     - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
  21       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  22
  23   [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
  24
  25   - reg: From mmc bindings: Register location and length.
  26   - clocks: From clock bindings: Handles to clock inputs.
  27   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  28   - interrupts: Interrupt specifier
  29
  30 Required Properties for "arasan,sdhci-5.1":
  31   - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  32   - phy-names:  MUST be "phy_arasan".
  33
  34 Optional Properties:
  35   - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
  36     used to access core corecfg registers.  Offsets of registers in this
  37     syscon are determined based on the main compatible string for the device.
  38   - clock-output-names: If specified, this will be the name of the card clock
  39     which will be exposed by this device.  Required if #clock-cells is
  40     specified.
  41   - #clock-cells: If specified this should be the value <0>.  With this property
  42     in place we will export a clock representing the Card Clock.  This clock
  43     is expected to be consumed by our PHY.  You must also specify
  44   - xlnx,fails-without-test-cd: when present, the controller doesn't work when
  45     the CD line is not connected properly, and the line is not connected
  46     properly. Test mode can be used to force the controller to function.
  47   - xlnx,int-clock-stable-broken: when present, the controller always reports
  48     that the internal clock is stable even when it is not.
  49
  50 Example:
  51         sdhci@e0100000 {
  52                 compatible = "arasan,sdhci-8.9a";
  53                 reg = <0xe0100000 0x1000>;
  54                 clock-names = "clk_xin", "clk_ahb";
  55                 clocks = <&clkc 21>, <&clkc 32>;
  56                 interrupt-parent = <&gic>;
  57                 interrupts = <0 24 4>;
  58         } ;
  59
  60         sdhci@e2800000 {
  61                 compatible = "arasan,sdhci-5.1";
  62                 reg = <0xe2800000 0x1000>;
  63                 clock-names = "clk_xin", "clk_ahb";
  64                 clocks = <&cru 8>, <&cru 18>;
  65                 interrupt-parent = <&gic>;
  66                 interrupts = <0 24 4>;
  67                 phys = <&emmc_phy>;
  68                 phy-names = "phy_arasan";
  69         } ;
  70
  71         sdhci: sdhci@fe330000 {
  72                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  73                 reg = <0x0 0xfe330000 0x0 0x10000>;
  74                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  75                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  76                 clock-names = "clk_xin", "clk_ahb";
  77                 arasan,soc-ctl-syscon = <&grf>;
  78                 assigned-clocks = <&cru SCLK_EMMC>;
  79                 assigned-clock-rates = <200000000>;
  80                 clock-output-names = "emmc_cardclock";
  81                 phys = <&emmc_phy>;
  82                 phy-names = "phy_arasan";
  83                 #clock-cells = <0>;
  84         };
  85
  86         emmc: sdhci@ec700000 {
  87                 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
  88                 reg = <0xec700000 0x300>;
  89                 interrupt-parent = <&ioapic1>;
  90                 interrupts = <44 1>;
  91                 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
  92                          <&cgu0 LGM_GCLK_EMMC>;
  93                 clock-names = "clk_xin", "clk_ahb", "gate";
  94                 clock-output-names = "emmc_cardclock";
  95                 #clock-cells = <0>;
  96                 phys = <&emmc_phy>;
  97                 phy-names = "phy_arasan";
  98                 arasan,soc-ctl-syscon = <&sysconf>;
  99         };