1 --------------------------------------------------------------------------
2 = Zynq UltraScale+ MPSoC reset driver binding =
3 --------------------------------------------------------------------------
4 The Zynq UltraScale+ MPSoC has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
9 Please also refer to reset.txt in this directory for common reset
10 controller binding usage.
13 - compatible: "xlnx,zynqmp-reset"
14 - #reset-cells: Specifies the number of cells needed to encode reset
22 zynqmp_firmware: zynqmp-firmware {
23 compatible = "xlnx,zynqmp-firmware";
26 zynqmp_reset: reset-controller {
27 compatible = "xlnx,zynqmp-reset";
33 Specifying reset lines connected to IP modules
34 ==============================================
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
38 specified in reset.txt.
40 For list of all valid reset indicies see
41 <dt-bindings/reset/xlnx-zynqmp-resets.h>
45 serdes: zynqmp_phy@fd400000 {
48 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
49 reset-names = "sata_rst";