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iwlwifi: update copyright year to 2009
[linux/fpc-iii.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
blobe6d4503cd213f6e214065f9e33dd9ac96a4d101f
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39 #include <net/mac80211.h>
40
41 #include "iwl-fh.h"
42 #include "iwl-3945-fh.h"
43 #include "iwl-commands.h"
44 #include "iwl-3945.h"
45 #include "iwl-helpers.h"
46 #include "iwl-core.h"
47 #include "iwl-agn-rs.h"
48
49 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_##r##M_IEEE, \
52 IWL_RATE_##ip##M_INDEX, \
53 IWL_RATE_##in##M_INDEX, \
54 IWL_RATE_##rp##M_INDEX, \
55 IWL_RATE_##rn##M_INDEX, \
56 IWL_RATE_##pp##M_INDEX, \
57 IWL_RATE_##np##M_INDEX, \
58 IWL_RATE_##r##M_INDEX_TABLE, \
59 IWL_RATE_##ip##M_INDEX_TABLE }
60
61 /*
62 * Parameter order:
63 * rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
69 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
70 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
74 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
82 };
83
84 /* 1 = enable the iwl3945_disable_events() function */
85 #define IWL_EVT_DISABLE (0)
86 #define IWL_EVT_DISABLE_SIZE (1532/32)
87
88 /**
89 * iwl3945_disable_events - Disable selected events in uCode event log
90 *
91 * Disable an event by writing "1"s into "disable"
92 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
93 * Default values of 0 enable uCode events to be logged.
94 * Use for only special debugging. This function is just a placeholder as-is,
95 * you'll need to provide the special bits! ...
96 * ... and set IWL_EVT_DISABLE to 1. */
97 void iwl3945_disable_events(struct iwl_priv *priv)
98 {
99 int ret;
100 int i;
101 u32 base; /* SRAM address of event log header */
102 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
103 u32 array_size; /* # of u32 entries in array */
104 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
105 0x00000000, /* 31 - 0 Event id numbers */
106 0x00000000, /* 63 - 32 */
107 0x00000000, /* 95 - 64 */
108 0x00000000, /* 127 - 96 */
109 0x00000000, /* 159 - 128 */
110 0x00000000, /* 191 - 160 */
111 0x00000000, /* 223 - 192 */
112 0x00000000, /* 255 - 224 */
113 0x00000000, /* 287 - 256 */
114 0x00000000, /* 319 - 288 */
115 0x00000000, /* 351 - 320 */
116 0x00000000, /* 383 - 352 */
117 0x00000000, /* 415 - 384 */
118 0x00000000, /* 447 - 416 */
119 0x00000000, /* 479 - 448 */
120 0x00000000, /* 511 - 480 */
121 0x00000000, /* 543 - 512 */
122 0x00000000, /* 575 - 544 */
123 0x00000000, /* 607 - 576 */
124 0x00000000, /* 639 - 608 */
125 0x00000000, /* 671 - 640 */
126 0x00000000, /* 703 - 672 */
127 0x00000000, /* 735 - 704 */
128 0x00000000, /* 767 - 736 */
129 0x00000000, /* 799 - 768 */
130 0x00000000, /* 831 - 800 */
131 0x00000000, /* 863 - 832 */
132 0x00000000, /* 895 - 864 */
133 0x00000000, /* 927 - 896 */
134 0x00000000, /* 959 - 928 */
135 0x00000000, /* 991 - 960 */
136 0x00000000, /* 1023 - 992 */
137 0x00000000, /* 1055 - 1024 */
138 0x00000000, /* 1087 - 1056 */
139 0x00000000, /* 1119 - 1088 */
140 0x00000000, /* 1151 - 1120 */
141 0x00000000, /* 1183 - 1152 */
142 0x00000000, /* 1215 - 1184 */
143 0x00000000, /* 1247 - 1216 */
144 0x00000000, /* 1279 - 1248 */
145 0x00000000, /* 1311 - 1280 */
146 0x00000000, /* 1343 - 1312 */
147 0x00000000, /* 1375 - 1344 */
148 0x00000000, /* 1407 - 1376 */
149 0x00000000, /* 1439 - 1408 */
150 0x00000000, /* 1471 - 1440 */
151 0x00000000, /* 1503 - 1472 */
152 };
153
154 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
155 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
156 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
157 return;
158 }
159
160 ret = iwl_grab_nic_access(priv);
161 if (ret) {
162 IWL_WARN(priv, "Can not read from adapter at this time.\n");
163 return;
164 }
165
166 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
168 iwl_release_nic_access(priv);
169
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
172 disable_ptr);
173 ret = iwl_grab_nic_access(priv);
174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
175 iwl_write_targ_mem(priv,
176 disable_ptr + (i * sizeof(u32)),
177 evt_disable[i]);
178
179 iwl_release_nic_access(priv);
180 } else {
181 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
182 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
183 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
184 disable_ptr, array_size);
185 }
186
187 }
188
189 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
190 {
191 int idx;
192
193 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
194 if (iwl3945_rates[idx].plcp == plcp)
195 return idx;
196 return -1;
197 }
198
199 /**
200 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
201 * @priv: eeprom and antenna fields are used to determine antenna flags
202 *
203 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
204 * priv->antenna specifies the antenna diversity mode:
205 *
206 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
207 * IWL_ANTENNA_MAIN - Force MAIN antenna
208 * IWL_ANTENNA_AUX - Force AUX antenna
209 */
210 __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
211 {
212 switch (priv->antenna) {
213 case IWL_ANTENNA_DIVERSITY:
214 return 0;
215
216 case IWL_ANTENNA_MAIN:
217 if (priv->eeprom39.antenna_switch_type)
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
219 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
220
221 case IWL_ANTENNA_AUX:
222 if (priv->eeprom39.antenna_switch_type)
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
224 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
225 }
226
227 /* bad antenna selector value */
228 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
229 return 0; /* "diversity" is default if error */
230 }
231
232 #ifdef CONFIG_IWL3945_DEBUG
233 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
234
235 static const char *iwl3945_get_tx_fail_reason(u32 status)
236 {
237 switch (status & TX_STATUS_MSK) {
238 case TX_STATUS_SUCCESS:
239 return "SUCCESS";
240 TX_STATUS_ENTRY(SHORT_LIMIT);
241 TX_STATUS_ENTRY(LONG_LIMIT);
242 TX_STATUS_ENTRY(FIFO_UNDERRUN);
243 TX_STATUS_ENTRY(MGMNT_ABORT);
244 TX_STATUS_ENTRY(NEXT_FRAG);
245 TX_STATUS_ENTRY(LIFE_EXPIRE);
246 TX_STATUS_ENTRY(DEST_PS);
247 TX_STATUS_ENTRY(ABORTED);
248 TX_STATUS_ENTRY(BT_RETRY);
249 TX_STATUS_ENTRY(STA_INVALID);
250 TX_STATUS_ENTRY(FRAG_DROPPED);
251 TX_STATUS_ENTRY(TID_DISABLE);
252 TX_STATUS_ENTRY(FRAME_FLUSHED);
253 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
254 TX_STATUS_ENTRY(TX_LOCKED);
255 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
256 }
257
258 return "UNKNOWN";
259 }
260 #else
261 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
262 {
263 return "";
264 }
265 #endif
266
267 /*
268 * get ieee prev rate from rate scale table.
269 * for A and B mode we need to overright prev
270 * value
271 */
272 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
273 {
274 int next_rate = iwl3945_get_prev_ieee_rate(rate);
275
276 switch (priv->band) {
277 case IEEE80211_BAND_5GHZ:
278 if (rate == IWL_RATE_12M_INDEX)
279 next_rate = IWL_RATE_9M_INDEX;
280 else if (rate == IWL_RATE_6M_INDEX)
281 next_rate = IWL_RATE_6M_INDEX;
282 break;
283 case IEEE80211_BAND_2GHZ:
284 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
285 iwl3945_is_associated(priv)) {
286 if (rate == IWL_RATE_11M_INDEX)
287 next_rate = IWL_RATE_5M_INDEX;
288 }
289 break;
290
291 default:
292 break;
293 }
294
295 return next_rate;
296 }
297
298
299 /**
300 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
301 *
302 * When FW advances 'R' index, all entries between old and new 'R' index
303 * need to be reclaimed. As result, some free space forms. If there is
304 * enough free space (> low mark), wake the stack that feeds us.
305 */
306 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
307 int txq_id, int index)
308 {
309 struct iwl_tx_queue *txq = &priv->txq[txq_id];
310 struct iwl_queue *q = &txq->q;
311 struct iwl_tx_info *tx_info;
312
313 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
314
315 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
316 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
317
318 tx_info = &txq->txb[txq->q.read_ptr];
319 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
320 tx_info->skb[0] = NULL;
321 iwl3945_hw_txq_free_tfd(priv, txq);
322 }
323
324 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
325 (txq_id != IWL_CMD_QUEUE_NUM) &&
326 priv->mac80211_registered)
327 ieee80211_wake_queue(priv->hw, txq_id);
328 }
329
330 /**
331 * iwl3945_rx_reply_tx - Handle Tx response
332 */
333 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
334 struct iwl_rx_mem_buffer *rxb)
335 {
336 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
337 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
338 int txq_id = SEQ_TO_QUEUE(sequence);
339 int index = SEQ_TO_INDEX(sequence);
340 struct iwl_tx_queue *txq = &priv->txq[txq_id];
341 struct ieee80211_tx_info *info;
342 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
343 u32 status = le32_to_cpu(tx_resp->status);
344 int rate_idx;
345 int fail;
346
347 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
348 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
349 "is out of range [0-%d] %d %d\n", txq_id,
350 index, txq->q.n_bd, txq->q.write_ptr,
351 txq->q.read_ptr);
352 return;
353 }
354
355 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
356 ieee80211_tx_info_clear_status(info);
357
358 /* Fill the MRR chain with some info about on-chip retransmissions */
359 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
360 if (info->band == IEEE80211_BAND_5GHZ)
361 rate_idx -= IWL_FIRST_OFDM_RATE;
362
363 fail = tx_resp->failure_frame;
364
365 info->status.rates[0].idx = rate_idx;
366 info->status.rates[0].count = fail + 1; /* add final attempt */
367
368 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
369 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
370 IEEE80211_TX_STAT_ACK : 0;
371
372 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
373 txq_id, iwl3945_get_tx_fail_reason(status), status,
374 tx_resp->rate, tx_resp->failure_frame);
375
376 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
377 iwl3945_tx_queue_reclaim(priv, txq_id, index);
378
379 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
380 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
381 }
382
383
384
385 /*****************************************************************************
386 *
387 * Intel PRO/Wireless 3945ABG/BG Network Connection
388 *
389 * RX handler implementations
390 *
391 *****************************************************************************/
392
393 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
394 {
395 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
396 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
397 (int)sizeof(struct iwl3945_notif_statistics),
398 le32_to_cpu(pkt->len));
399
400 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
401
402 iwl3945_led_background(priv);
403
404 priv->last_statistics_time = jiffies;
405 }
406
407 /******************************************************************************
408 *
409 * Misc. internal state and helper functions
410 *
411 ******************************************************************************/
412 #ifdef CONFIG_IWL3945_DEBUG
413
414 /**
415 * iwl3945_report_frame - dump frame to syslog during debug sessions
416 *
417 * You may hack this function to show different aspects of received frames,
418 * including selective frame dumps.
419 * group100 parameter selects whether to show 1 out of 100 good frames.
420 */
421 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
422 struct iwl_rx_packet *pkt,
423 struct ieee80211_hdr *header, int group100)
424 {
425 u32 to_us;
426 u32 print_summary = 0;
427 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
428 u32 hundred = 0;
429 u32 dataframe = 0;
430 __le16 fc;
431 u16 seq_ctl;
432 u16 channel;
433 u16 phy_flags;
434 u16 length;
435 u16 status;
436 u16 bcn_tmr;
437 u32 tsf_low;
438 u64 tsf;
439 u8 rssi;
440 u8 agc;
441 u16 sig_avg;
442 u16 noise_diff;
443 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
444 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
445 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
446 u8 *data = IWL_RX_DATA(pkt);
447
448 /* MAC header */
449 fc = header->frame_control;
450 seq_ctl = le16_to_cpu(header->seq_ctrl);
451
452 /* metadata */
453 channel = le16_to_cpu(rx_hdr->channel);
454 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
455 length = le16_to_cpu(rx_hdr->len);
456
457 /* end-of-frame status and timestamp */
458 status = le32_to_cpu(rx_end->status);
459 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
460 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
461 tsf = le64_to_cpu(rx_end->timestamp);
462
463 /* signal statistics */
464 rssi = rx_stats->rssi;
465 agc = rx_stats->agc;
466 sig_avg = le16_to_cpu(rx_stats->sig_avg);
467 noise_diff = le16_to_cpu(rx_stats->noise_diff);
468
469 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
470
471 /* if data frame is to us and all is good,
472 * (optionally) print summary for only 1 out of every 100 */
473 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
474 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
475 dataframe = 1;
476 if (!group100)
477 print_summary = 1; /* print each frame */
478 else if (priv->framecnt_to_us < 100) {
479 priv->framecnt_to_us++;
480 print_summary = 0;
481 } else {
482 priv->framecnt_to_us = 0;
483 print_summary = 1;
484 hundred = 1;
485 }
486 } else {
487 /* print summary for all other frames */
488 print_summary = 1;
489 }
490
491 if (print_summary) {
492 char *title;
493 int rate;
494
495 if (hundred)
496 title = "100Frames";
497 else if (ieee80211_has_retry(fc))
498 title = "Retry";
499 else if (ieee80211_is_assoc_resp(fc))
500 title = "AscRsp";
501 else if (ieee80211_is_reassoc_resp(fc))
502 title = "RasRsp";
503 else if (ieee80211_is_probe_resp(fc)) {
504 title = "PrbRsp";
505 print_dump = 1; /* dump frame contents */
506 } else if (ieee80211_is_beacon(fc)) {
507 title = "Beacon";
508 print_dump = 1; /* dump frame contents */
509 } else if (ieee80211_is_atim(fc))
510 title = "ATIM";
511 else if (ieee80211_is_auth(fc))
512 title = "Auth";
513 else if (ieee80211_is_deauth(fc))
514 title = "DeAuth";
515 else if (ieee80211_is_disassoc(fc))
516 title = "DisAssoc";
517 else
518 title = "Frame";
519
520 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
521 if (rate == -1)
522 rate = 0;
523 else
524 rate = iwl3945_rates[rate].ieee / 2;
525
526 /* print frame summary.
527 * MAC addresses show just the last byte (for brevity),
528 * but you can hack it to show more, if you'd like to. */
529 if (dataframe)
530 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
531 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
532 title, le16_to_cpu(fc), header->addr1[5],
533 length, rssi, channel, rate);
534 else {
535 /* src/dst addresses assume managed mode */
536 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
537 "src=0x%02x, rssi=%u, tim=%lu usec, "
538 "phy=0x%02x, chnl=%d\n",
539 title, le16_to_cpu(fc), header->addr1[5],
540 header->addr3[5], rssi,
541 tsf_low - priv->scan_start_tsf,
542 phy_flags, channel);
543 }
544 }
545 if (print_dump)
546 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
547 }
548 #else
549 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
550 struct iwl_rx_packet *pkt,
551 struct ieee80211_hdr *header, int group100)
552 {
553 }
554 #endif
555
556 /* This is necessary only for a number of statistics, see the caller. */
557 static int iwl3945_is_network_packet(struct iwl_priv *priv,
558 struct ieee80211_hdr *header)
559 {
560 /* Filter incoming packets to determine if they are targeted toward
561 * this network, discarding packets coming from ourselves */
562 switch (priv->iw_mode) {
563 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
564 /* packets to our IBSS update information */
565 return !compare_ether_addr(header->addr3, priv->bssid);
566 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
567 /* packets to our IBSS update information */
568 return !compare_ether_addr(header->addr2, priv->bssid);
569 default:
570 return 1;
571 }
572 }
573
574 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
575 struct iwl_rx_mem_buffer *rxb,
576 struct ieee80211_rx_status *stats)
577 {
578 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
579 #ifdef CONFIG_IWL3945_LEDS
580 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
581 #endif
582 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
583 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
584 short len = le16_to_cpu(rx_hdr->len);
585
586 /* We received data from the HW, so stop the watchdog */
587 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
588 IWL_DEBUG_DROP("Corruption detected!\n");
589 return;
590 }
591
592 /* We only process data packets if the interface is open */
593 if (unlikely(!priv->is_open)) {
594 IWL_DEBUG_DROP_LIMIT
595 ("Dropping packet while interface is not open.\n");
596 return;
597 }
598
599 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
600 /* Set the size of the skb to the size of the frame */
601 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
602
603 if (!iwl3945_mod_params.sw_crypto)
604 iwl3945_set_decrypted_flag(priv, rxb->skb,
605 le32_to_cpu(rx_end->status), stats);
606
607 #ifdef CONFIG_IWL3945_LEDS
608 if (ieee80211_is_data(hdr->frame_control))
609 priv->rxtxpackets += len;
610 #endif
611 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
612 rxb->skb = NULL;
613 }
614
615 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
616
617 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
618 struct iwl_rx_mem_buffer *rxb)
619 {
620 struct ieee80211_hdr *header;
621 struct ieee80211_rx_status rx_status;
622 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
623 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
624 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
625 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
626 int snr;
627 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
628 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
629 u8 network_packet;
630
631 rx_status.flag = 0;
632 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
633 rx_status.freq =
634 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
635 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
636 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
637
638 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
639 if (rx_status.band == IEEE80211_BAND_5GHZ)
640 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
641
642 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
643 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
644
645 /* set the preamble flag if appropriate */
646 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
647 rx_status.flag |= RX_FLAG_SHORTPRE;
648
649 if ((unlikely(rx_stats->phy_count > 20))) {
650 IWL_DEBUG_DROP
651 ("dsp size out of range [0,20]: "
652 "%d/n", rx_stats->phy_count);
653 return;
654 }
655
656 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
657 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
658 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
659 return;
660 }
661
662
663
664 /* Convert 3945's rssi indicator to dBm */
665 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
666
667 /* Set default noise value to -127 */
668 if (priv->last_rx_noise == 0)
669 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
670
671 /* 3945 provides noise info for OFDM frames only.
672 * sig_avg and noise_diff are measured by the 3945's digital signal
673 * processor (DSP), and indicate linear levels of signal level and
674 * distortion/noise within the packet preamble after
675 * automatic gain control (AGC). sig_avg should stay fairly
676 * constant if the radio's AGC is working well.
677 * Since these values are linear (not dB or dBm), linear
678 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
679 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
680 * to obtain noise level in dBm.
681 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
682 if (rx_stats_noise_diff) {
683 snr = rx_stats_sig_avg / rx_stats_noise_diff;
684 rx_status.noise = rx_status.signal -
685 iwl3945_calc_db_from_ratio(snr);
686 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
687 rx_status.noise);
688
689 /* If noise info not available, calculate signal quality indicator (%)
690 * using just the dBm signal level. */
691 } else {
692 rx_status.noise = priv->last_rx_noise;
693 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
694 }
695
696
697 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
698 rx_status.signal, rx_status.noise, rx_status.qual,
699 rx_stats_sig_avg, rx_stats_noise_diff);
700
701 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
702
703 network_packet = iwl3945_is_network_packet(priv, header);
704
705 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
706 network_packet ? '*' : ' ',
707 le16_to_cpu(rx_hdr->channel),
708 rx_status.signal, rx_status.signal,
709 rx_status.noise, rx_status.rate_idx);
710
711 #ifdef CONFIG_IWL3945_DEBUG
712 if (priv->debug_level & (IWL_DL_RX))
713 /* Set "1" to report good data frames in groups of 100 */
714 iwl3945_dbg_report_frame(priv, pkt, header, 1);
715 #endif
716
717 if (network_packet) {
718 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
719 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
720 priv->last_rx_rssi = rx_status.signal;
721 priv->last_rx_noise = rx_status.noise;
722 }
723
724 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
725 }
726
727 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
728 dma_addr_t addr, u16 len)
729 {
730 int count;
731 u32 pad;
732 struct iwl3945_tfd *tfd = (struct iwl3945_tfd *)ptr;
733
734 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
735 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
736
737 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
738 IWL_ERR(priv, "Error can not send more than %d chunks\n",
739 NUM_TFD_CHUNKS);
740 return -EINVAL;
741 }
742
743 tfd->tbs[count].addr = cpu_to_le32(addr);
744 tfd->tbs[count].len = cpu_to_le32(len);
745
746 count++;
747
748 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
749 TFD_CTL_PAD_SET(pad));
750
751 return 0;
752 }
753
754 /**
755 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
756 *
757 * Does NOT advance any indexes
758 */
759 int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
760 {
761 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)&txq->tfds39[0];
762 struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
763 struct pci_dev *dev = priv->pci_dev;
764 int i;
765 int counter;
766
767 /* classify bd */
768 if (txq->q.id == IWL_CMD_QUEUE_NUM)
769 /* nothing to cleanup after for host commands */
770 return 0;
771
772 /* sanity check */
773 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
774 if (counter > NUM_TFD_CHUNKS) {
775 IWL_ERR(priv, "Too many chunks: %i\n", counter);
776 /* @todo issue fatal error, it is quite serious situation */
777 return 0;
778 }
779
780 /* unmap chunks if any */
781
782 for (i = 1; i < counter; i++) {
783 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
784 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
785 if (txq->txb[txq->q.read_ptr].skb[0]) {
786 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
787 if (txq->txb[txq->q.read_ptr].skb[0]) {
788 /* Can be called from interrupt context */
789 dev_kfree_skb_any(skb);
790 txq->txb[txq->q.read_ptr].skb[0] = NULL;
791 }
792 }
793 }
794 return 0;
795 }
796
797 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
798 {
799 int i, start = IWL_AP_ID;
800 int ret = IWL_INVALID_STATION;
801 unsigned long flags;
802
803 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
804 (priv->iw_mode == NL80211_IFTYPE_AP))
805 start = IWL_STA_ID;
806
807 if (is_broadcast_ether_addr(addr))
808 return priv->hw_params.bcast_sta_id;
809
810 spin_lock_irqsave(&priv->sta_lock, flags);
811 for (i = start; i < priv->hw_params.max_stations; i++)
812 if ((priv->stations_39[i].used) &&
813 (!compare_ether_addr
814 (priv->stations_39[i].sta.sta.addr, addr))) {
815 ret = i;
816 goto out;
817 }
818
819 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
820 addr, priv->num_stations);
821 out:
822 spin_unlock_irqrestore(&priv->sta_lock, flags);
823 return ret;
824 }
825
826 /**
827 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
828 *
829 */
830 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
831 struct ieee80211_tx_info *info,
832 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
833 {
834 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
835 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
836 u16 rate_mask;
837 int rate;
838 u8 rts_retry_limit;
839 u8 data_retry_limit;
840 __le32 tx_flags;
841 __le16 fc = hdr->frame_control;
842 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
843
844 rate = iwl3945_rates[rate_index].plcp;
845 tx_flags = tx->tx_flags;
846
847 /* We need to figure out how to get the sta->supp_rates while
848 * in this running context */
849 rate_mask = IWL_RATES_MASK;
850
851 if (tx_id >= IWL_CMD_QUEUE_NUM)
852 rts_retry_limit = 3;
853 else
854 rts_retry_limit = 7;
855
856 if (ieee80211_is_probe_resp(fc)) {
857 data_retry_limit = 3;
858 if (data_retry_limit < rts_retry_limit)
859 rts_retry_limit = data_retry_limit;
860 } else
861 data_retry_limit = IWL_DEFAULT_TX_RETRY;
862
863 if (priv->data_retry_limit != -1)
864 data_retry_limit = priv->data_retry_limit;
865
866 if (ieee80211_is_mgmt(fc)) {
867 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
868 case cpu_to_le16(IEEE80211_STYPE_AUTH):
869 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
870 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
871 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
872 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
873 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
874 tx_flags |= TX_CMD_FLG_CTS_MSK;
875 }
876 break;
877 default:
878 break;
879 }
880 }
881
882 tx->rts_retry_limit = rts_retry_limit;
883 tx->data_retry_limit = data_retry_limit;
884 tx->rate = rate;
885 tx->tx_flags = tx_flags;
886
887 /* OFDM */
888 tx->supp_rates[0] =
889 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
890
891 /* CCK */
892 tx->supp_rates[1] = (rate_mask & 0xF);
893
894 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
895 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
896 tx->rate, le32_to_cpu(tx->tx_flags),
897 tx->supp_rates[1], tx->supp_rates[0]);
898 }
899
900 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
901 {
902 unsigned long flags_spin;
903 struct iwl3945_station_entry *station;
904
905 if (sta_id == IWL_INVALID_STATION)
906 return IWL_INVALID_STATION;
907
908 spin_lock_irqsave(&priv->sta_lock, flags_spin);
909 station = &priv->stations_39[sta_id];
910
911 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
912 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
913 station->sta.mode = STA_CONTROL_MODIFY_MSK;
914
915 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
916
917 iwl3945_send_add_station(priv, &station->sta, flags);
918 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
919 sta_id, tx_rate);
920 return sta_id;
921 }
922
923 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
924 {
925 int rc;
926 unsigned long flags;
927
928 spin_lock_irqsave(&priv->lock, flags);
929 rc = iwl_grab_nic_access(priv);
930 if (rc) {
931 spin_unlock_irqrestore(&priv->lock, flags);
932 return rc;
933 }
934
935 if (src == IWL_PWR_SRC_VAUX) {
936 u32 val;
937
938 rc = pci_read_config_dword(priv->pci_dev,
939 PCI_POWER_SOURCE, &val);
940 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
941 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
942 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
943 ~APMG_PS_CTRL_MSK_PWR_SRC);
944 iwl_release_nic_access(priv);
945
946 iwl_poll_bit(priv, CSR_GPIO_IN,
947 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
948 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
949 } else
950 iwl_release_nic_access(priv);
951 } else {
952 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
953 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
954 ~APMG_PS_CTRL_MSK_PWR_SRC);
955
956 iwl_release_nic_access(priv);
957 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
958 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
959 }
960 spin_unlock_irqrestore(&priv->lock, flags);
961
962 return rc;
963 }
964
965 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
966 {
967 int rc;
968 unsigned long flags;
969
970 spin_lock_irqsave(&priv->lock, flags);
971 rc = iwl_grab_nic_access(priv);
972 if (rc) {
973 spin_unlock_irqrestore(&priv->lock, flags);
974 return rc;
975 }
976
977 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
978 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
979 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
980 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
981 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
982 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
984 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
985 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
986 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
987 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
988 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
989
990 /* fake read to flush all prev I/O */
991 iwl_read_direct32(priv, FH39_RSSR_CTRL);
992
993 iwl_release_nic_access(priv);
994 spin_unlock_irqrestore(&priv->lock, flags);
995
996 return 0;
997 }
998
999 static int iwl3945_tx_reset(struct iwl_priv *priv)
1000 {
1001 int rc;
1002 unsigned long flags;
1003
1004 spin_lock_irqsave(&priv->lock, flags);
1005 rc = iwl_grab_nic_access(priv);
1006 if (rc) {
1007 spin_unlock_irqrestore(&priv->lock, flags);
1008 return rc;
1009 }
1010
1011 /* bypass mode */
1012 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1013
1014 /* RA 0 is active */
1015 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1016
1017 /* all 6 fifo are active */
1018 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1019
1020 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1022 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1023 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1024
1025 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1026 priv->shared_phys);
1027
1028 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1029 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1036
1037 iwl_release_nic_access(priv);
1038 spin_unlock_irqrestore(&priv->lock, flags);
1039
1040 return 0;
1041 }
1042
1043 /**
1044 * iwl3945_txq_ctx_reset - Reset TX queue context
1045 *
1046 * Destroys all DMA structures and initialize them again
1047 */
1048 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1049 {
1050 int rc;
1051 int txq_id, slots_num;
1052
1053 iwl3945_hw_txq_ctx_free(priv);
1054
1055 /* Tx CMD queue */
1056 rc = iwl3945_tx_reset(priv);
1057 if (rc)
1058 goto error;
1059
1060 /* Tx queue(s) */
1061 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1062 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1063 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1064 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1065 txq_id);
1066 if (rc) {
1067 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1068 goto error;
1069 }
1070 }
1071
1072 return rc;
1073
1074 error:
1075 iwl3945_hw_txq_ctx_free(priv);
1076 return rc;
1077 }
1078
1079 static int iwl3945_apm_init(struct iwl_priv *priv)
1080 {
1081 int ret = 0;
1082
1083 iwl3945_power_init_handle(priv);
1084
1085 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1086 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1087
1088 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1089 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1090 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1091
1092 /* set "initialization complete" bit to move adapter
1093 * D0U* --> D0A* state */
1094 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1095
1096 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1097 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1098 if (ret < 0) {
1099 IWL_DEBUG_INFO("Failed to init the card\n");
1100 goto out;
1101 }
1102
1103 ret = iwl_grab_nic_access(priv);
1104 if (ret)
1105 goto out;
1106
1107 /* enable DMA */
1108 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1109 APMG_CLK_VAL_BSM_CLK_RQT);
1110
1111 udelay(20);
1112
1113 /* disable L1-Active */
1114 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1115 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1116
1117 iwl_release_nic_access(priv);
1118 out:
1119 return ret;
1120 }
1121
1122 static void iwl3945_nic_config(struct iwl_priv *priv)
1123 {
1124 unsigned long flags;
1125 u8 rev_id = 0;
1126
1127 spin_lock_irqsave(&priv->lock, flags);
1128
1129 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1130 IWL_DEBUG_INFO("RTP type \n");
1131 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1132 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1133 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1134 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1135 } else {
1136 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1137 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1138 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1139 }
1140
1141 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
1142 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1143 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1144 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1145 } else
1146 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1147
1148 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
1149 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1150 priv->eeprom39.board_revision);
1151 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1152 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1153 } else {
1154 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1155 priv->eeprom39.board_revision);
1156 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1157 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1158 }
1159
1160 if (priv->eeprom39.almgor_m_version <= 1) {
1161 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1162 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1163 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1164 priv->eeprom39.almgor_m_version);
1165 } else {
1166 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1167 priv->eeprom39.almgor_m_version);
1168 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1169 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1170 }
1171 spin_unlock_irqrestore(&priv->lock, flags);
1172
1173 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1174 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1175
1176 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1177 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1178 }
1179
1180 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1181 {
1182 u8 rev_id;
1183 int rc;
1184 unsigned long flags;
1185 struct iwl_rx_queue *rxq = &priv->rxq;
1186
1187 spin_lock_irqsave(&priv->lock, flags);
1188 priv->cfg->ops->lib->apm_ops.init(priv);
1189 spin_unlock_irqrestore(&priv->lock, flags);
1190
1191 /* Determine HW type */
1192 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1193 if (rc)
1194 return rc;
1195 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1196
1197 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1198 if(rc)
1199 return rc;
1200
1201 priv->cfg->ops->lib->apm_ops.config(priv);
1202
1203 /* Allocate the RX queue, or reset if it is already allocated */
1204 if (!rxq->bd) {
1205 rc = iwl_rx_queue_alloc(priv);
1206 if (rc) {
1207 IWL_ERR(priv, "Unable to initialize Rx queue\n");
1208 return -ENOMEM;
1209 }
1210 } else
1211 iwl_rx_queue_reset(priv, rxq);
1212
1213 iwl3945_rx_replenish(priv);
1214
1215 iwl3945_rx_init(priv, rxq);
1216
1217 spin_lock_irqsave(&priv->lock, flags);
1218
1219 /* Look at using this instead:
1220 rxq->need_update = 1;
1221 iwl_rx_queue_update_write_ptr(priv, rxq);
1222 */
1223
1224 rc = iwl_grab_nic_access(priv);
1225 if (rc) {
1226 spin_unlock_irqrestore(&priv->lock, flags);
1227 return rc;
1228 }
1229 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1230 iwl_release_nic_access(priv);
1231
1232 spin_unlock_irqrestore(&priv->lock, flags);
1233
1234 rc = iwl3945_txq_ctx_reset(priv);
1235 if (rc)
1236 return rc;
1237
1238 set_bit(STATUS_INIT, &priv->status);
1239
1240 return 0;
1241 }
1242
1243 /**
1244 * iwl3945_hw_txq_ctx_free - Free TXQ Context
1245 *
1246 * Destroy all TX DMA queues and structures
1247 */
1248 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1249 {
1250 int txq_id;
1251
1252 /* Tx queues */
1253 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1254 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1255 }
1256
1257 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1258 {
1259 int txq_id;
1260 unsigned long flags;
1261
1262 spin_lock_irqsave(&priv->lock, flags);
1263 if (iwl_grab_nic_access(priv)) {
1264 spin_unlock_irqrestore(&priv->lock, flags);
1265 iwl3945_hw_txq_ctx_free(priv);
1266 return;
1267 }
1268
1269 /* stop SCD */
1270 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1271
1272 /* reset TFD queues */
1273 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1274 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1275 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1276 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1277 1000);
1278 }
1279
1280 iwl_release_nic_access(priv);
1281 spin_unlock_irqrestore(&priv->lock, flags);
1282
1283 iwl3945_hw_txq_ctx_free(priv);
1284 }
1285
1286 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1287 {
1288 int ret = 0;
1289 unsigned long flags;
1290
1291 spin_lock_irqsave(&priv->lock, flags);
1292
1293 /* set stop master bit */
1294 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1295
1296 iwl_poll_direct_bit(priv, CSR_RESET,
1297 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1298
1299 if (ret < 0)
1300 goto out;
1301
1302 out:
1303 spin_unlock_irqrestore(&priv->lock, flags);
1304 IWL_DEBUG_INFO("stop master\n");
1305
1306 return ret;
1307 }
1308
1309 static void iwl3945_apm_stop(struct iwl_priv *priv)
1310 {
1311 unsigned long flags;
1312
1313 iwl3945_apm_stop_master(priv);
1314
1315 spin_lock_irqsave(&priv->lock, flags);
1316
1317 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1318
1319 udelay(10);
1320 /* clear "init complete" move adapter D0A* --> D0U state */
1321 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1322 spin_unlock_irqrestore(&priv->lock, flags);
1323 }
1324
1325 static int iwl3945_apm_reset(struct iwl_priv *priv)
1326 {
1327 int rc;
1328 unsigned long flags;
1329
1330 iwl3945_apm_stop_master(priv);
1331
1332 spin_lock_irqsave(&priv->lock, flags);
1333
1334 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1335
1336 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1337 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1338
1339 rc = iwl_grab_nic_access(priv);
1340 if (!rc) {
1341 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1342 APMG_CLK_VAL_BSM_CLK_RQT);
1343
1344 udelay(10);
1345
1346 iwl_set_bit(priv, CSR_GP_CNTRL,
1347 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1348
1349 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1350 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1351 0xFFFFFFFF);
1352
1353 /* enable DMA */
1354 iwl_write_prph(priv, APMG_CLK_EN_REG,
1355 APMG_CLK_VAL_DMA_CLK_RQT |
1356 APMG_CLK_VAL_BSM_CLK_RQT);
1357 udelay(10);
1358
1359 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1360 APMG_PS_CTRL_VAL_RESET_REQ);
1361 udelay(5);
1362 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1363 APMG_PS_CTRL_VAL_RESET_REQ);
1364 iwl_release_nic_access(priv);
1365 }
1366
1367 /* Clear the 'host command active' bit... */
1368 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1369
1370 wake_up_interruptible(&priv->wait_command_queue);
1371 spin_unlock_irqrestore(&priv->lock, flags);
1372
1373 return rc;
1374 }
1375
1376 /**
1377 * iwl3945_hw_reg_adjust_power_by_temp
1378 * return index delta into power gain settings table
1379 */
1380 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1381 {
1382 return (new_reading - old_reading) * (-11) / 100;
1383 }
1384
1385 /**
1386 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1387 */
1388 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1389 {
1390 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1391 }
1392
1393 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1394 {
1395 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1396 }
1397
1398 /**
1399 * iwl3945_hw_reg_txpower_get_temperature
1400 * get the current temperature by reading from NIC
1401 */
1402 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1403 {
1404 int temperature;
1405
1406 temperature = iwl3945_hw_get_temperature(priv);
1407
1408 /* driver's okay range is -260 to +25.
1409 * human readable okay range is 0 to +285 */
1410 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1411
1412 /* handle insane temp reading */
1413 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1414 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
1415
1416 /* if really really hot(?),
1417 * substitute the 3rd band/group's temp measured at factory */
1418 if (priv->last_temperature > 100)
1419 temperature = priv->eeprom39.groups[2].temperature;
1420 else /* else use most recent "sane" value from driver */
1421 temperature = priv->last_temperature;
1422 }
1423
1424 return temperature; /* raw, not "human readable" */
1425 }
1426
1427 /* Adjust Txpower only if temperature variance is greater than threshold.
1428 *
1429 * Both are lower than older versions' 9 degrees */
1430 #define IWL_TEMPERATURE_LIMIT_TIMER 6
1431
1432 /**
1433 * is_temp_calib_needed - determines if new calibration is needed
1434 *
1435 * records new temperature in tx_mgr->temperature.
1436 * replaces tx_mgr->last_temperature *only* if calib needed
1437 * (assumes caller will actually do the calibration!). */
1438 static int is_temp_calib_needed(struct iwl_priv *priv)
1439 {
1440 int temp_diff;
1441
1442 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1443 temp_diff = priv->temperature - priv->last_temperature;
1444
1445 /* get absolute value */
1446 if (temp_diff < 0) {
1447 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1448 temp_diff = -temp_diff;
1449 } else if (temp_diff == 0)
1450 IWL_DEBUG_POWER("Same temp,\n");
1451 else
1452 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1453
1454 /* if we don't need calibration, *don't* update last_temperature */
1455 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1456 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1457 return 0;
1458 }
1459
1460 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1461
1462 /* assume that caller will actually do calib ...
1463 * update the "last temperature" value */
1464 priv->last_temperature = priv->temperature;
1465 return 1;
1466 }
1467
1468 #define IWL_MAX_GAIN_ENTRIES 78
1469 #define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1470 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1471
1472 /* radio and DSP power table, each step is 1/2 dB.
1473 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1474 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1475 {
1476 {251, 127}, /* 2.4 GHz, highest power */
1477 {251, 127},
1478 {251, 127},
1479 {251, 127},
1480 {251, 125},
1481 {251, 110},
1482 {251, 105},
1483 {251, 98},
1484 {187, 125},
1485 {187, 115},
1486 {187, 108},
1487 {187, 99},
1488 {243, 119},
1489 {243, 111},
1490 {243, 105},
1491 {243, 97},
1492 {243, 92},
1493 {211, 106},
1494 {211, 100},
1495 {179, 120},
1496 {179, 113},
1497 {179, 107},
1498 {147, 125},
1499 {147, 119},
1500 {147, 112},
1501 {147, 106},
1502 {147, 101},
1503 {147, 97},
1504 {147, 91},
1505 {115, 107},
1506 {235, 121},
1507 {235, 115},
1508 {235, 109},
1509 {203, 127},
1510 {203, 121},
1511 {203, 115},
1512 {203, 108},
1513 {203, 102},
1514 {203, 96},
1515 {203, 92},
1516 {171, 110},
1517 {171, 104},
1518 {171, 98},
1519 {139, 116},
1520 {227, 125},
1521 {227, 119},
1522 {227, 113},
1523 {227, 107},
1524 {227, 101},
1525 {227, 96},
1526 {195, 113},
1527 {195, 106},
1528 {195, 102},
1529 {195, 95},
1530 {163, 113},
1531 {163, 106},
1532 {163, 102},
1533 {163, 95},
1534 {131, 113},
1535 {131, 106},
1536 {131, 102},
1537 {131, 95},
1538 {99, 113},
1539 {99, 106},
1540 {99, 102},
1541 {99, 95},
1542 {67, 113},
1543 {67, 106},
1544 {67, 102},
1545 {67, 95},
1546 {35, 113},
1547 {35, 106},
1548 {35, 102},
1549 {35, 95},
1550 {3, 113},
1551 {3, 106},
1552 {3, 102},
1553 {3, 95} }, /* 2.4 GHz, lowest power */
1554 {
1555 {251, 127}, /* 5.x GHz, highest power */
1556 {251, 120},
1557 {251, 114},
1558 {219, 119},
1559 {219, 101},
1560 {187, 113},
1561 {187, 102},
1562 {155, 114},
1563 {155, 103},
1564 {123, 117},
1565 {123, 107},
1566 {123, 99},
1567 {123, 92},
1568 {91, 108},
1569 {59, 125},
1570 {59, 118},
1571 {59, 109},
1572 {59, 102},
1573 {59, 96},
1574 {59, 90},
1575 {27, 104},
1576 {27, 98},
1577 {27, 92},
1578 {115, 118},
1579 {115, 111},
1580 {115, 104},
1581 {83, 126},
1582 {83, 121},
1583 {83, 113},
1584 {83, 105},
1585 {83, 99},
1586 {51, 118},
1587 {51, 111},
1588 {51, 104},
1589 {51, 98},
1590 {19, 116},
1591 {19, 109},
1592 {19, 102},
1593 {19, 98},
1594 {19, 93},
1595 {171, 113},
1596 {171, 107},
1597 {171, 99},
1598 {139, 120},
1599 {139, 113},
1600 {139, 107},
1601 {139, 99},
1602 {107, 120},
1603 {107, 113},
1604 {107, 107},
1605 {107, 99},
1606 {75, 120},
1607 {75, 113},
1608 {75, 107},
1609 {75, 99},
1610 {43, 120},
1611 {43, 113},
1612 {43, 107},
1613 {43, 99},
1614 {11, 120},
1615 {11, 113},
1616 {11, 107},
1617 {11, 99},
1618 {131, 107},
1619 {131, 99},
1620 {99, 120},
1621 {99, 113},
1622 {99, 107},
1623 {99, 99},
1624 {67, 120},
1625 {67, 113},
1626 {67, 107},
1627 {67, 99},
1628 {35, 120},
1629 {35, 113},
1630 {35, 107},
1631 {35, 99},
1632 {3, 120} } /* 5.x GHz, lowest power */
1633 };
1634
1635 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1636 {
1637 if (index < 0)
1638 return 0;
1639 if (index >= IWL_MAX_GAIN_ENTRIES)
1640 return IWL_MAX_GAIN_ENTRIES - 1;
1641 return (u8) index;
1642 }
1643
1644 /* Kick off thermal recalibration check every 60 seconds */
1645 #define REG_RECALIB_PERIOD (60)
1646
1647 /**
1648 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1649 *
1650 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1651 * or 6 Mbit (OFDM) rates.
1652 */
1653 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1654 s32 rate_index, const s8 *clip_pwrs,
1655 struct iwl_channel_info *ch_info,
1656 int band_index)
1657 {
1658 struct iwl3945_scan_power_info *scan_power_info;
1659 s8 power;
1660 u8 power_index;
1661
1662 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1663
1664 /* use this channel group's 6Mbit clipping/saturation pwr,
1665 * but cap at regulatory scan power restriction (set during init
1666 * based on eeprom channel data) for this channel. */
1667 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1668
1669 /* further limit to user's max power preference.
1670 * FIXME: Other spectrum management power limitations do not
1671 * seem to apply?? */
1672 power = min(power, priv->user_txpower_limit);
1673 scan_power_info->requested_power = power;
1674
1675 /* find difference between new scan *power* and current "normal"
1676 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1677 * current "normal" temperature-compensated Tx power *index* for
1678 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1679 * *index*. */
1680 power_index = ch_info->power_info[rate_index].power_table_index
1681 - (power - ch_info->power_info
1682 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1683
1684 /* store reference index that we use when adjusting *all* scan
1685 * powers. So we can accommodate user (all channel) or spectrum
1686 * management (single channel) power changes "between" temperature
1687 * feedback compensation procedures.
1688 * don't force fit this reference index into gain table; it may be a
1689 * negative number. This will help avoid errors when we're at
1690 * the lower bounds (highest gains, for warmest temperatures)
1691 * of the table. */
1692
1693 /* don't exceed table bounds for "real" setting */
1694 power_index = iwl3945_hw_reg_fix_power_index(power_index);
1695
1696 scan_power_info->power_table_index = power_index;
1697 scan_power_info->tpc.tx_gain =
1698 power_gain_table[band_index][power_index].tx_gain;
1699 scan_power_info->tpc.dsp_atten =
1700 power_gain_table[band_index][power_index].dsp_atten;
1701 }
1702
1703 /**
1704 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1705 *
1706 * Configures power settings for all rates for the current channel,
1707 * using values from channel info struct, and send to NIC
1708 */
1709 int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
1710 {
1711 int rate_idx, i;
1712 const struct iwl_channel_info *ch_info = NULL;
1713 struct iwl3945_txpowertable_cmd txpower = {
1714 .channel = priv->active39_rxon.channel,
1715 };
1716
1717 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1718 ch_info = iwl3945_get_channel_info(priv,
1719 priv->band,
1720 le16_to_cpu(priv->active39_rxon.channel));
1721 if (!ch_info) {
1722 IWL_ERR(priv,
1723 "Failed to get channel info for channel %d [%d]\n",
1724 le16_to_cpu(priv->active39_rxon.channel), priv->band);
1725 return -EINVAL;
1726 }
1727
1728 if (!is_channel_valid(ch_info)) {
1729 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1730 "non-Tx channel.\n");
1731 return 0;
1732 }
1733
1734 /* fill cmd with power settings for all rates for current channel */
1735 /* Fill OFDM rate */
1736 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1737 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1738
1739 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1740 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1741
1742 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1743 le16_to_cpu(txpower.channel),
1744 txpower.band,
1745 txpower.power[i].tpc.tx_gain,
1746 txpower.power[i].tpc.dsp_atten,
1747 txpower.power[i].rate);
1748 }
1749 /* Fill CCK rates */
1750 for (rate_idx = IWL_FIRST_CCK_RATE;
1751 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1752 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1753 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1754
1755 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1756 le16_to_cpu(txpower.channel),
1757 txpower.band,
1758 txpower.power[i].tpc.tx_gain,
1759 txpower.power[i].tpc.dsp_atten,
1760 txpower.power[i].rate);
1761 }
1762
1763 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1764 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1765
1766 }
1767
1768 /**
1769 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1770 * @ch_info: Channel to update. Uses power_info.requested_power.
1771 *
1772 * Replace requested_power and base_power_index ch_info fields for
1773 * one channel.
1774 *
1775 * Called if user or spectrum management changes power preferences.
1776 * Takes into account h/w and modulation limitations (clip power).
1777 *
1778 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1779 *
1780 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1781 * properly fill out the scan powers, and actual h/w gain settings,
1782 * and send changes to NIC
1783 */
1784 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1785 struct iwl_channel_info *ch_info)
1786 {
1787 struct iwl3945_channel_power_info *power_info;
1788 int power_changed = 0;
1789 int i;
1790 const s8 *clip_pwrs;
1791 int power;
1792
1793 /* Get this chnlgrp's rate-to-max/clip-powers table */
1794 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1795
1796 /* Get this channel's rate-to-current-power settings table */
1797 power_info = ch_info->power_info;
1798
1799 /* update OFDM Txpower settings */
1800 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1801 i++, ++power_info) {
1802 int delta_idx;
1803
1804 /* limit new power to be no more than h/w capability */
1805 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1806 if (power == power_info->requested_power)
1807 continue;
1808
1809 /* find difference between old and new requested powers,
1810 * update base (non-temp-compensated) power index */
1811 delta_idx = (power - power_info->requested_power) * 2;
1812 power_info->base_power_index -= delta_idx;
1813
1814 /* save new requested power value */
1815 power_info->requested_power = power;
1816
1817 power_changed = 1;
1818 }
1819
1820 /* update CCK Txpower settings, based on OFDM 12M setting ...
1821 * ... all CCK power settings for a given channel are the *same*. */
1822 if (power_changed) {
1823 power =
1824 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1825 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1826
1827 /* do all CCK rates' iwl3945_channel_power_info structures */
1828 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1829 power_info->requested_power = power;
1830 power_info->base_power_index =
1831 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1832 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1833 ++power_info;
1834 }
1835 }
1836
1837 return 0;
1838 }
1839
1840 /**
1841 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1842 *
1843 * NOTE: Returned power limit may be less (but not more) than requested,
1844 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1845 * (no consideration for h/w clipping limitations).
1846 */
1847 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1848 {
1849 s8 max_power;
1850
1851 #if 0
1852 /* if we're using TGd limits, use lower of TGd or EEPROM */
1853 if (ch_info->tgd_data.max_power != 0)
1854 max_power = min(ch_info->tgd_data.max_power,
1855 ch_info->eeprom.max_power_avg);
1856
1857 /* else just use EEPROM limits */
1858 else
1859 #endif
1860 max_power = ch_info->eeprom.max_power_avg;
1861
1862 return min(max_power, ch_info->max_power_avg);
1863 }
1864
1865 /**
1866 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1867 *
1868 * Compensate txpower settings of *all* channels for temperature.
1869 * This only accounts for the difference between current temperature
1870 * and the factory calibration temperatures, and bases the new settings
1871 * on the channel's base_power_index.
1872 *
1873 * If RxOn is "associated", this sends the new Txpower to NIC!
1874 */
1875 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1876 {
1877 struct iwl_channel_info *ch_info = NULL;
1878 int delta_index;
1879 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1880 u8 a_band;
1881 u8 rate_index;
1882 u8 scan_tbl_index;
1883 u8 i;
1884 int ref_temp;
1885 int temperature = priv->temperature;
1886
1887 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1888 for (i = 0; i < priv->channel_count; i++) {
1889 ch_info = &priv->channel_info[i];
1890 a_band = is_channel_a_band(ch_info);
1891
1892 /* Get this chnlgrp's factory calibration temperature */
1893 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
1894 temperature;
1895
1896 /* get power index adjustment based on current and factory
1897 * temps */
1898 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1899 ref_temp);
1900
1901 /* set tx power value for all rates, OFDM and CCK */
1902 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1903 rate_index++) {
1904 int power_idx =
1905 ch_info->power_info[rate_index].base_power_index;
1906
1907 /* temperature compensate */
1908 power_idx += delta_index;
1909
1910 /* stay within table range */
1911 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1912 ch_info->power_info[rate_index].
1913 power_table_index = (u8) power_idx;
1914 ch_info->power_info[rate_index].tpc =
1915 power_gain_table[a_band][power_idx];
1916 }
1917
1918 /* Get this chnlgrp's rate-to-max/clip-powers table */
1919 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1920
1921 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1922 for (scan_tbl_index = 0;
1923 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1924 s32 actual_index = (scan_tbl_index == 0) ?
1925 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1926 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1927 actual_index, clip_pwrs,
1928 ch_info, a_band);
1929 }
1930 }
1931
1932 /* send Txpower command for current channel to ucode */
1933 return iwl3945_hw_reg_send_txpower(priv);
1934 }
1935
1936 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1937 {
1938 struct iwl_channel_info *ch_info;
1939 s8 max_power;
1940 u8 a_band;
1941 u8 i;
1942
1943 if (priv->user_txpower_limit == power) {
1944 IWL_DEBUG_POWER("Requested Tx power same as current "
1945 "limit: %ddBm.\n", power);
1946 return 0;
1947 }
1948
1949 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1950 priv->user_txpower_limit = power;
1951
1952 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1953
1954 for (i = 0; i < priv->channel_count; i++) {
1955 ch_info = &priv->channel_info[i];
1956 a_band = is_channel_a_band(ch_info);
1957
1958 /* find minimum power of all user and regulatory constraints
1959 * (does not consider h/w clipping limitations) */
1960 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1961 max_power = min(power, max_power);
1962 if (max_power != ch_info->curr_txpow) {
1963 ch_info->curr_txpow = max_power;
1964
1965 /* this considers the h/w clipping limitations */
1966 iwl3945_hw_reg_set_new_power(priv, ch_info);
1967 }
1968 }
1969
1970 /* update txpower settings for all channels,
1971 * send to NIC if associated. */
1972 is_temp_calib_needed(priv);
1973 iwl3945_hw_reg_comp_txpower_temp(priv);
1974
1975 return 0;
1976 }
1977
1978 /* will add 3945 channel switch cmd handling later */
1979 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1980 {
1981 return 0;
1982 }
1983
1984 /**
1985 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1986 *
1987 * -- reset periodic timer
1988 * -- see if temp has changed enough to warrant re-calibration ... if so:
1989 * -- correct coeffs for temp (can reset temp timer)
1990 * -- save this temp as "last",
1991 * -- send new set of gain settings to NIC
1992 * NOTE: This should continue working, even when we're not associated,
1993 * so we can keep our internal table of scan powers current. */
1994 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1995 {
1996 /* This will kick in the "brute force"
1997 * iwl3945_hw_reg_comp_txpower_temp() below */
1998 if (!is_temp_calib_needed(priv))
1999 goto reschedule;
2000
2001 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2002 * This is based *only* on current temperature,
2003 * ignoring any previous power measurements */
2004 iwl3945_hw_reg_comp_txpower_temp(priv);
2005
2006 reschedule:
2007 queue_delayed_work(priv->workqueue,
2008 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2009 }
2010
2011 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2012 {
2013 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2014 thermal_periodic.work);
2015
2016 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2017 return;
2018
2019 mutex_lock(&priv->mutex);
2020 iwl3945_reg_txpower_periodic(priv);
2021 mutex_unlock(&priv->mutex);
2022 }
2023
2024 /**
2025 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2026 * for the channel.
2027 *
2028 * This function is used when initializing channel-info structs.
2029 *
2030 * NOTE: These channel groups do *NOT* match the bands above!
2031 * These channel groups are based on factory-tested channels;
2032 * on A-band, EEPROM's "group frequency" entries represent the top
2033 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2034 */
2035 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2036 const struct iwl_channel_info *ch_info)
2037 {
2038 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
2039 u8 group;
2040 u16 group_index = 0; /* based on factory calib frequencies */
2041 u8 grp_channel;
2042
2043 /* Find the group index for the channel ... don't use index 1(?) */
2044 if (is_channel_a_band(ch_info)) {
2045 for (group = 1; group < 5; group++) {
2046 grp_channel = ch_grp[group].group_channel;
2047 if (ch_info->channel <= grp_channel) {
2048 group_index = group;
2049 break;
2050 }
2051 }
2052 /* group 4 has a few channels *above* its factory cal freq */
2053 if (group == 5)
2054 group_index = 4;
2055 } else
2056 group_index = 0; /* 2.4 GHz, group 0 */
2057
2058 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2059 group_index);
2060 return group_index;
2061 }
2062
2063 /**
2064 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2065 *
2066 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2067 * into radio/DSP gain settings table for requested power.
2068 */
2069 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2070 s8 requested_power,
2071 s32 setting_index, s32 *new_index)
2072 {
2073 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2074 s32 index0, index1;
2075 s32 power = 2 * requested_power;
2076 s32 i;
2077 const struct iwl3945_eeprom_txpower_sample *samples;
2078 s32 gains0, gains1;
2079 s32 res;
2080 s32 denominator;
2081
2082 chnl_grp = &priv->eeprom39.groups[setting_index];
2083 samples = chnl_grp->samples;
2084 for (i = 0; i < 5; i++) {
2085 if (power == samples[i].power) {
2086 *new_index = samples[i].gain_index;
2087 return 0;
2088 }
2089 }
2090
2091 if (power > samples[1].power) {
2092 index0 = 0;
2093 index1 = 1;
2094 } else if (power > samples[2].power) {
2095 index0 = 1;
2096 index1 = 2;
2097 } else if (power > samples[3].power) {
2098 index0 = 2;
2099 index1 = 3;
2100 } else {
2101 index0 = 3;
2102 index1 = 4;
2103 }
2104
2105 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2106 if (denominator == 0)
2107 return -EINVAL;
2108 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2109 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2110 res = gains0 + (gains1 - gains0) *
2111 ((s32) power - (s32) samples[index0].power) / denominator +
2112 (1 << 18);
2113 *new_index = res >> 19;
2114 return 0;
2115 }
2116
2117 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2118 {
2119 u32 i;
2120 s32 rate_index;
2121 const struct iwl3945_eeprom_txpower_group *group;
2122
2123 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2124
2125 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2126 s8 *clip_pwrs; /* table of power levels for each rate */
2127 s8 satur_pwr; /* saturation power for each chnl group */
2128 group = &priv->eeprom39.groups[i];
2129
2130 /* sanity check on factory saturation power value */
2131 if (group->saturation_power < 40) {
2132 IWL_WARN(priv, "Error: saturation power is %d, "
2133 "less than minimum expected 40\n",
2134 group->saturation_power);
2135 return;
2136 }
2137
2138 /*
2139 * Derive requested power levels for each rate, based on
2140 * hardware capabilities (saturation power for band).
2141 * Basic value is 3dB down from saturation, with further
2142 * power reductions for highest 3 data rates. These
2143 * backoffs provide headroom for high rate modulation
2144 * power peaks, without too much distortion (clipping).
2145 */
2146 /* we'll fill in this array with h/w max power levels */
2147 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2148
2149 /* divide factory saturation power by 2 to find -3dB level */
2150 satur_pwr = (s8) (group->saturation_power >> 1);
2151
2152 /* fill in channel group's nominal powers for each rate */
2153 for (rate_index = 0;
2154 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2155 switch (rate_index) {
2156 case IWL_RATE_36M_INDEX_TABLE:
2157 if (i == 0) /* B/G */
2158 *clip_pwrs = satur_pwr;
2159 else /* A */
2160 *clip_pwrs = satur_pwr - 5;
2161 break;
2162 case IWL_RATE_48M_INDEX_TABLE:
2163 if (i == 0)
2164 *clip_pwrs = satur_pwr - 7;
2165 else
2166 *clip_pwrs = satur_pwr - 10;
2167 break;
2168 case IWL_RATE_54M_INDEX_TABLE:
2169 if (i == 0)
2170 *clip_pwrs = satur_pwr - 9;
2171 else
2172 *clip_pwrs = satur_pwr - 12;
2173 break;
2174 default:
2175 *clip_pwrs = satur_pwr;
2176 break;
2177 }
2178 }
2179 }
2180 }
2181
2182 /**
2183 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2184 *
2185 * Second pass (during init) to set up priv->channel_info
2186 *
2187 * Set up Tx-power settings in our channel info database for each VALID
2188 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2189 * and current temperature.
2190 *
2191 * Since this is based on current temperature (at init time), these values may
2192 * not be valid for very long, but it gives us a starting/default point,
2193 * and allows us to active (i.e. using Tx) scan.
2194 *
2195 * This does *not* write values to NIC, just sets up our internal table.
2196 */
2197 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2198 {
2199 struct iwl_channel_info *ch_info = NULL;
2200 struct iwl3945_channel_power_info *pwr_info;
2201 int delta_index;
2202 u8 rate_index;
2203 u8 scan_tbl_index;
2204 const s8 *clip_pwrs; /* array of power levels for each rate */
2205 u8 gain, dsp_atten;
2206 s8 power;
2207 u8 pwr_index, base_pwr_index, a_band;
2208 u8 i;
2209 int temperature;
2210
2211 /* save temperature reference,
2212 * so we can determine next time to calibrate */
2213 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2214 priv->last_temperature = temperature;
2215
2216 iwl3945_hw_reg_init_channel_groups(priv);
2217
2218 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2219 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2220 i++, ch_info++) {
2221 a_band = is_channel_a_band(ch_info);
2222 if (!is_channel_valid(ch_info))
2223 continue;
2224
2225 /* find this channel's channel group (*not* "band") index */
2226 ch_info->group_index =
2227 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2228
2229 /* Get this chnlgrp's rate->max/clip-powers table */
2230 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2231
2232 /* calculate power index *adjustment* value according to
2233 * diff between current temperature and factory temperature */
2234 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2235 priv->eeprom39.groups[ch_info->group_index].
2236 temperature);
2237
2238 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2239 ch_info->channel, delta_index, temperature +
2240 IWL_TEMP_CONVERT);
2241
2242 /* set tx power value for all OFDM rates */
2243 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2244 rate_index++) {
2245 s32 uninitialized_var(power_idx);
2246 int rc;
2247
2248 /* use channel group's clip-power table,
2249 * but don't exceed channel's max power */
2250 s8 pwr = min(ch_info->max_power_avg,
2251 clip_pwrs[rate_index]);
2252
2253 pwr_info = &ch_info->power_info[rate_index];
2254
2255 /* get base (i.e. at factory-measured temperature)
2256 * power table index for this rate's power */
2257 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2258 ch_info->group_index,
2259 &power_idx);
2260 if (rc) {
2261 IWL_ERR(priv, "Invalid power index\n");
2262 return rc;
2263 }
2264 pwr_info->base_power_index = (u8) power_idx;
2265
2266 /* temperature compensate */
2267 power_idx += delta_index;
2268
2269 /* stay within range of gain table */
2270 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2271
2272 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2273 pwr_info->requested_power = pwr;
2274 pwr_info->power_table_index = (u8) power_idx;
2275 pwr_info->tpc.tx_gain =
2276 power_gain_table[a_band][power_idx].tx_gain;
2277 pwr_info->tpc.dsp_atten =
2278 power_gain_table[a_band][power_idx].dsp_atten;
2279 }
2280
2281 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2282 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2283 power = pwr_info->requested_power +
2284 IWL_CCK_FROM_OFDM_POWER_DIFF;
2285 pwr_index = pwr_info->power_table_index +
2286 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2287 base_pwr_index = pwr_info->base_power_index +
2288 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2289
2290 /* stay within table range */
2291 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2292 gain = power_gain_table[a_band][pwr_index].tx_gain;
2293 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2294
2295 /* fill each CCK rate's iwl3945_channel_power_info structure
2296 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2297 * NOTE: CCK rates start at end of OFDM rates! */
2298 for (rate_index = 0;
2299 rate_index < IWL_CCK_RATES; rate_index++) {
2300 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2301 pwr_info->requested_power = power;
2302 pwr_info->power_table_index = pwr_index;
2303 pwr_info->base_power_index = base_pwr_index;
2304 pwr_info->tpc.tx_gain = gain;
2305 pwr_info->tpc.dsp_atten = dsp_atten;
2306 }
2307
2308 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2309 for (scan_tbl_index = 0;
2310 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2311 s32 actual_index = (scan_tbl_index == 0) ?
2312 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2313 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2314 actual_index, clip_pwrs, ch_info, a_band);
2315 }
2316 }
2317
2318 return 0;
2319 }
2320
2321 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2322 {
2323 int rc;
2324 unsigned long flags;
2325
2326 spin_lock_irqsave(&priv->lock, flags);
2327 rc = iwl_grab_nic_access(priv);
2328 if (rc) {
2329 spin_unlock_irqrestore(&priv->lock, flags);
2330 return rc;
2331 }
2332
2333 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2334 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2335 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2336 if (rc < 0)
2337 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2338
2339 iwl_release_nic_access(priv);
2340 spin_unlock_irqrestore(&priv->lock, flags);
2341
2342 return 0;
2343 }
2344
2345 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2346 {
2347 int rc;
2348 unsigned long flags;
2349 int txq_id = txq->q.id;
2350
2351 struct iwl3945_shared *shared_data = priv->shared_virt;
2352
2353 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2354
2355 spin_lock_irqsave(&priv->lock, flags);
2356 rc = iwl_grab_nic_access(priv);
2357 if (rc) {
2358 spin_unlock_irqrestore(&priv->lock, flags);
2359 return rc;
2360 }
2361 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2362 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2363
2364 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2365 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2366 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2367 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2368 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2369 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2370 iwl_release_nic_access(priv);
2371
2372 /* fake read to flush all prev. writes */
2373 iwl_read32(priv, FH39_TSSR_CBB_BASE);
2374 spin_unlock_irqrestore(&priv->lock, flags);
2375
2376 return 0;
2377 }
2378
2379 /*
2380 * HCMD utils
2381 */
2382 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2383 {
2384 switch (cmd_id) {
2385 case REPLY_RXON:
2386 return (u16) sizeof(struct iwl3945_rxon_cmd);
2387 default:
2388 return len;
2389 }
2390 }
2391
2392 /**
2393 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2394 */
2395 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2396 {
2397 int rc, i, index, prev_index;
2398 struct iwl3945_rate_scaling_cmd rate_cmd = {
2399 .reserved = {0, 0, 0},
2400 };
2401 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2402
2403 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2404 index = iwl3945_rates[i].table_rs_index;
2405
2406 table[index].rate_n_flags =
2407 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2408 table[index].try_cnt = priv->retry_rate;
2409 prev_index = iwl3945_get_prev_ieee_rate(i);
2410 table[index].next_rate_index =
2411 iwl3945_rates[prev_index].table_rs_index;
2412 }
2413
2414 switch (priv->band) {
2415 case IEEE80211_BAND_5GHZ:
2416 IWL_DEBUG_RATE("Select A mode rate scale\n");
2417 /* If one of the following CCK rates is used,
2418 * have it fall back to the 6M OFDM rate */
2419 for (i = IWL_RATE_1M_INDEX_TABLE;
2420 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2421 table[i].next_rate_index =
2422 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2423
2424 /* Don't fall back to CCK rates */
2425 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2426 IWL_RATE_9M_INDEX_TABLE;
2427
2428 /* Don't drop out of OFDM rates */
2429 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2430 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2431 break;
2432
2433 case IEEE80211_BAND_2GHZ:
2434 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2435 /* If an OFDM rate is used, have it fall back to the
2436 * 1M CCK rates */
2437
2438 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2439 iwl3945_is_associated(priv)) {
2440
2441 index = IWL_FIRST_CCK_RATE;
2442 for (i = IWL_RATE_6M_INDEX_TABLE;
2443 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2444 table[i].next_rate_index =
2445 iwl3945_rates[index].table_rs_index;
2446
2447 index = IWL_RATE_11M_INDEX_TABLE;
2448 /* CCK shouldn't fall back to OFDM... */
2449 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2450 }
2451 break;
2452
2453 default:
2454 WARN_ON(1);
2455 break;
2456 }
2457
2458 /* Update the rate scaling for control frame Tx */
2459 rate_cmd.table_id = 0;
2460 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2461 &rate_cmd);
2462 if (rc)
2463 return rc;
2464
2465 /* Update the rate scaling for data frame Tx */
2466 rate_cmd.table_id = 1;
2467 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2468 &rate_cmd);
2469 }
2470
2471 /* Called when initializing driver */
2472 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2473 {
2474 memset((void *)&priv->hw_params, 0,
2475 sizeof(struct iwl_hw_params));
2476
2477 priv->shared_virt =
2478 pci_alloc_consistent(priv->pci_dev,
2479 sizeof(struct iwl3945_shared),
2480 &priv->shared_phys);
2481
2482 if (!priv->shared_virt) {
2483 IWL_ERR(priv, "failed to allocate pci memory\n");
2484 mutex_unlock(&priv->mutex);
2485 return -ENOMEM;
2486 }
2487
2488 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2489 priv->hw_params.max_pkt_size = 2342;
2490 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2491 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2492 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2493 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2494
2495 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2496
2497 return 0;
2498 }
2499
2500 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2501 struct iwl3945_frame *frame, u8 rate)
2502 {
2503 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2504 unsigned int frame_size;
2505
2506 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2507 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2508
2509 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2510 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2511
2512 frame_size = iwl3945_fill_beacon_frame(priv,
2513 tx_beacon_cmd->frame,
2514 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2515
2516 BUG_ON(frame_size > MAX_MPDU_SIZE);
2517 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2518
2519 tx_beacon_cmd->tx.rate = rate;
2520 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2521 TX_CMD_FLG_TSF_MSK);
2522
2523 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2524 tx_beacon_cmd->tx.supp_rates[0] =
2525 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2526
2527 tx_beacon_cmd->tx.supp_rates[1] =
2528 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2529
2530 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2531 }
2532
2533 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2534 {
2535 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2536 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2537 }
2538
2539 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2540 {
2541 INIT_DELAYED_WORK(&priv->thermal_periodic,
2542 iwl3945_bg_reg_txpower_periodic);
2543 }
2544
2545 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2546 {
2547 cancel_delayed_work(&priv->thermal_periodic);
2548 }
2549
2550 /* check contents of special bootstrap uCode SRAM */
2551 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2552 {
2553 __le32 *image = priv->ucode_boot.v_addr;
2554 u32 len = priv->ucode_boot.len;
2555 u32 reg;
2556 u32 val;
2557
2558 IWL_DEBUG_INFO("Begin verify bsm\n");
2559
2560 /* verify BSM SRAM contents */
2561 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2562 for (reg = BSM_SRAM_LOWER_BOUND;
2563 reg < BSM_SRAM_LOWER_BOUND + len;
2564 reg += sizeof(u32), image++) {
2565 val = iwl_read_prph(priv, reg);
2566 if (val != le32_to_cpu(*image)) {
2567 IWL_ERR(priv, "BSM uCode verification failed at "
2568 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2569 BSM_SRAM_LOWER_BOUND,
2570 reg - BSM_SRAM_LOWER_BOUND, len,
2571 val, le32_to_cpu(*image));
2572 return -EIO;
2573 }
2574 }
2575
2576 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2577
2578 return 0;
2579 }
2580
2581 /**
2582 * iwl3945_load_bsm - Load bootstrap instructions
2583 *
2584 * BSM operation:
2585 *
2586 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2587 * in special SRAM that does not power down during RFKILL. When powering back
2588 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2589 * the bootstrap program into the on-board processor, and starts it.
2590 *
2591 * The bootstrap program loads (via DMA) instructions and data for a new
2592 * program from host DRAM locations indicated by the host driver in the
2593 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2594 * automatically.
2595 *
2596 * When initializing the NIC, the host driver points the BSM to the
2597 * "initialize" uCode image. This uCode sets up some internal data, then
2598 * notifies host via "initialize alive" that it is complete.
2599 *
2600 * The host then replaces the BSM_DRAM_* pointer values to point to the
2601 * normal runtime uCode instructions and a backup uCode data cache buffer
2602 * (filled initially with starting data values for the on-board processor),
2603 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2604 * which begins normal operation.
2605 *
2606 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2607 * the backup data cache in DRAM before SRAM is powered down.
2608 *
2609 * When powering back up, the BSM loads the bootstrap program. This reloads
2610 * the runtime uCode instructions and the backup data cache into SRAM,
2611 * and re-launches the runtime uCode from where it left off.
2612 */
2613 static int iwl3945_load_bsm(struct iwl_priv *priv)
2614 {
2615 __le32 *image = priv->ucode_boot.v_addr;
2616 u32 len = priv->ucode_boot.len;
2617 dma_addr_t pinst;
2618 dma_addr_t pdata;
2619 u32 inst_len;
2620 u32 data_len;
2621 int rc;
2622 int i;
2623 u32 done;
2624 u32 reg_offset;
2625
2626 IWL_DEBUG_INFO("Begin load bsm\n");
2627
2628 /* make sure bootstrap program is no larger than BSM's SRAM size */
2629 if (len > IWL39_MAX_BSM_SIZE)
2630 return -EINVAL;
2631
2632 /* Tell bootstrap uCode where to find the "Initialize" uCode
2633 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2634 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2635 * after the "initialize" uCode has run, to point to
2636 * runtime/protocol instructions and backup data cache. */
2637 pinst = priv->ucode_init.p_addr;
2638 pdata = priv->ucode_init_data.p_addr;
2639 inst_len = priv->ucode_init.len;
2640 data_len = priv->ucode_init_data.len;
2641
2642 rc = iwl_grab_nic_access(priv);
2643 if (rc)
2644 return rc;
2645
2646 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2647 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2648 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2649 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2650
2651 /* Fill BSM memory with bootstrap instructions */
2652 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2653 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2654 reg_offset += sizeof(u32), image++)
2655 _iwl_write_prph(priv, reg_offset,
2656 le32_to_cpu(*image));
2657
2658 rc = iwl3945_verify_bsm(priv);
2659 if (rc) {
2660 iwl_release_nic_access(priv);
2661 return rc;
2662 }
2663
2664 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2665 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2666 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2667 IWL39_RTC_INST_LOWER_BOUND);
2668 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2669
2670 /* Load bootstrap code into instruction SRAM now,
2671 * to prepare to load "initialize" uCode */
2672 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2673 BSM_WR_CTRL_REG_BIT_START);
2674
2675 /* Wait for load of bootstrap uCode to finish */
2676 for (i = 0; i < 100; i++) {
2677 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2678 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2679 break;
2680 udelay(10);
2681 }
2682 if (i < 100)
2683 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2684 else {
2685 IWL_ERR(priv, "BSM write did not complete!\n");
2686 return -EIO;
2687 }
2688
2689 /* Enable future boot loads whenever power management unit triggers it
2690 * (e.g. when powering back up after power-save shutdown) */
2691 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2692 BSM_WR_CTRL_REG_BIT_START_EN);
2693
2694 iwl_release_nic_access(priv);
2695
2696 return 0;
2697 }
2698
2699 static struct iwl_lib_ops iwl3945_lib = {
2700 .load_ucode = iwl3945_load_bsm,
2701 .apm_ops = {
2702 .init = iwl3945_apm_init,
2703 .reset = iwl3945_apm_reset,
2704 .stop = iwl3945_apm_stop,
2705 .config = iwl3945_nic_config,
2706 .set_pwr_src = iwl3945_set_pwr_src,
2707 },
2708 };
2709
2710 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2711 .get_hcmd_size = iwl3945_get_hcmd_size,
2712 };
2713
2714 static struct iwl_ops iwl3945_ops = {
2715 .lib = &iwl3945_lib,
2716 .utils = &iwl3945_hcmd_utils,
2717 };
2718
2719 static struct iwl_cfg iwl3945_bg_cfg = {
2720 .name = "3945BG",
2721 .fw_name_pre = IWL3945_FW_PRE,
2722 .ucode_api_max = IWL3945_UCODE_API_MAX,
2723 .ucode_api_min = IWL3945_UCODE_API_MIN,
2724 .sku = IWL_SKU_G,
2725 .ops = &iwl3945_ops,
2726 .mod_params = &iwl3945_mod_params
2727 };
2728
2729 static struct iwl_cfg iwl3945_abg_cfg = {
2730 .name = "3945ABG",
2731 .fw_name_pre = IWL3945_FW_PRE,
2732 .ucode_api_max = IWL3945_UCODE_API_MAX,
2733 .ucode_api_min = IWL3945_UCODE_API_MIN,
2734 .sku = IWL_SKU_A|IWL_SKU_G,
2735 .ops = &iwl3945_ops,
2736 .mod_params = &iwl3945_mod_params
2737 };
2738
2739 struct pci_device_id iwl3945_hw_card_ids[] = {
2740 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2741 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2742 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2743 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2744 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2745 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2746 {0}
2747 };
2748
2749 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux with added FPC-III support