drivers/scsi/pas16.h

   1 /*
   2  * This driver adapted from Drew Eckhardt's Trantor T128 driver
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix and Linux consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 666-5836
   9  *
  10  *  ( Based on T128 - DISTRIBUTION RELEASE 3. )
  11  *
  12  * Modified to work with the Pro Audio Spectrum/Studio 16
  13  * by John Weidman.
  14  *
  15  *
  16  * For more information, please consult
  17  *
  18  * Media Vision
  19  * (510) 770-8600
  20  * (800) 348-7116
  21  */
  22
  23
  24 #ifndef PAS16_H
  25 #define PAS16_H
  26
  27 #define PAS16_DEFAULT_BASE_1  0x388
  28 #define PAS16_DEFAULT_BASE_2  0x384
  29 #define PAS16_DEFAULT_BASE_3  0x38c
  30 #define PAS16_DEFAULT_BASE_4  0x288
  31
  32 #define PAS16_DEFAULT_BOARD_1_IRQ 10
  33 #define PAS16_DEFAULT_BOARD_2_IRQ 12
  34 #define PAS16_DEFAULT_BOARD_3_IRQ 14
  35 #define PAS16_DEFAULT_BOARD_4_IRQ 15
  36
  37
  38 /*
  39  * The Pro Audio Spectrum boards are I/O mapped. They use a Zilog 5380
  40  * SCSI controller, which is the equivalent of NCR's 5380.  "Pseudo-DMA"
  41  * architecture is used, where a PAL drives the DMA signals on the 5380
  42  * allowing fast, blind transfers with proper handshaking.
  43  */
  44
  45
  46 /* The Time-out Counter register is used to safe-guard against a stuck
  47  * bus (in the case of RDY driven handshake) or a stuck byte (if 16-Bit
  48  * DMA conversion is used).  The counter uses a 28.224MHz clock
  49  * divided by 14 as its clock source.  In the case of a stuck byte in
  50  * the holding register, an interrupt is generated (and mixed with the
  51  * one with the drive) using the CD-ROM interrupt pointer.
  52  */
  53
  54 #define P_TIMEOUT_COUNTER_REG   0x4000
  55 #define P_TC_DISABLE    0x80    /* Set to 0 to enable timeout int. */
  56                                 /* Bits D6-D0 contain timeout count */
  57
  58
  59 #define P_TIMEOUT_STATUS_REG_OFFSET     0x4001
  60 #define P_TS_TIM                0x80    /* check timeout status */
  61                                         /* Bits D6-D4 N/U */
  62 #define P_TS_ARM_DRQ_INT        0x08    /* Arm DRQ Int.  When set high,
  63                                          * the next rising edge will
  64                                          * cause a CD-ROM interrupt.
  65                                          * When set low, the interrupt
  66                                          * will be cleared.  There is
  67                                          * no status available for
  68                                          * this interrupt.
  69                                          */
  70 #define P_TS_ENABLE_TO_ERR_INTERRUPT    /* Enable timeout error int. */
  71 #define P_TS_ENABLE_WAIT                /* Enable Wait */
  72
  73 #define P_TS_CT                 0x01    /* clear timeout. Note: writing
  74                                          * to this register clears the
  75                                          * timeout error int. or status
  76                                          */
  77
  78
  79 /*
  80  * The data register reads/writes to/from the 5380 in pseudo-DMA mode
  81  */
  82
  83 #define P_DATA_REG_OFFSET       0x5c00  /* rw */
  84
  85 #define P_STATUS_REG_OFFSET     0x5c01  /* ro */
  86 #define P_ST_RDY                0x80    /* 5380 DDRQ Status */
  87
  88 #define P_IRQ_STATUS            0x5c03
  89 #define P_IS_IRQ                0x80    /* DIRQ status */
  90
  91 #define PCB_CONFIG 0x803
  92 #define MASTER_ADDRESS_PTR 0x9a01  /* Fixed position - no relo */
  93 #define SYS_CONFIG_4 0x8003
  94 #define WAIT_STATE 0xbc00
  95 #define OPERATION_MODE_1 0xec03
  96 #define IO_CONFIG_3 0xf002
  97
  98 #define NCR5380_implementation_fields /* none */
  99
 100 #define PAS16_io_port(reg) (instance->io_port + pas16_offset[(reg)])
 101
 102 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) )
 103 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) )
 104
 105 #define NCR5380_dma_xfer_len(instance, cmd, phase)      (cmd->transfersize)
 106
 107 #define NCR5380_intr pas16_intr
 108 #define NCR5380_queue_command pas16_queue_command
 109 #define NCR5380_abort pas16_abort
 110 #define NCR5380_bus_reset pas16_bus_reset
 111 #define NCR5380_info pas16_info
 112 #define NCR5380_show_info pas16_show_info
 113 #define NCR5380_write_info pas16_write_info
 114
 115 /* 15 14 12 10 7 5 3
 116    1101 0100 1010 1000 */
 117
 118 #define PAS16_IRQS 0xd4a8
 119
 120 #endif /* PAS16_H */