?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.24.5
[linux/fpc-iii.git] / sound / pci / es1968.c
blobd69b11d1f993a0660e385ac28f5c68d3ca994fab
1 /*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97 #include <sound/driver.h>
98 #include <asm/io.h>
99 #include <linux/delay.h>
100 #include <linux/interrupt.h>
101 #include <linux/init.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/slab.h>
105 #include <linux/gameport.h>
106 #include <linux/moduleparam.h>
107 #include <linux/mutex.h>
108
109 #include <sound/core.h>
110 #include <sound/pcm.h>
111 #include <sound/mpu401.h>
112 #include <sound/ac97_codec.h>
113 #include <sound/initval.h>
114
115 #define CARD_NAME "ESS Maestro1/2"
116 #define DRIVER_NAME "ES1968"
117
118 MODULE_DESCRIPTION("ESS Maestro");
119 MODULE_LICENSE("GPL");
120 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
121 "{ESS,Maestro 2},"
122 "{ESS,Maestro 1},"
123 "{TerraTec,DMX}}");
124
125 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
126 #define SUPPORT_JOYSTICK 1
127 #endif
128
129 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
130 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
131 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
132 static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
133 static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
134 static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
135 static int clock[SNDRV_CARDS];
136 static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
137 static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
138 #ifdef SUPPORT_JOYSTICK
139 static int joystick[SNDRV_CARDS];
140 #endif
141
142 module_param_array(index, int, NULL, 0444);
143 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
144 module_param_array(id, charp, NULL, 0444);
145 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
146 module_param_array(enable, bool, NULL, 0444);
147 MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
148 module_param_array(total_bufsize, int, NULL, 0444);
149 MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
150 module_param_array(pcm_substreams_p, int, NULL, 0444);
151 MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
152 module_param_array(pcm_substreams_c, int, NULL, 0444);
153 MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
154 module_param_array(clock, int, NULL, 0444);
155 MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
156 module_param_array(use_pm, int, NULL, 0444);
157 MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
158 module_param_array(enable_mpu, int, NULL, 0444);
159 MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
160 #ifdef SUPPORT_JOYSTICK
161 module_param_array(joystick, bool, NULL, 0444);
162 MODULE_PARM_DESC(joystick, "Enable joystick.");
163 #endif
164
165
166 #define NR_APUS 64
167 #define NR_APU_REGS 16
168
169 /* NEC Versas ? */
170 #define NEC_VERSA_SUBID1 0x80581033
171 #define NEC_VERSA_SUBID2 0x803c1033
172
173 /* Mode Flags */
174 #define ESS_FMT_STEREO 0x01
175 #define ESS_FMT_16BIT 0x02
176
177 #define DAC_RUNNING 1
178 #define ADC_RUNNING 2
179
180 /* Values for the ESM_LEGACY_AUDIO_CONTROL */
181
182 #define ESS_DISABLE_AUDIO 0x8000
183 #define ESS_ENABLE_SERIAL_IRQ 0x4000
184 #define IO_ADRESS_ALIAS 0x0020
185 #define MPU401_IRQ_ENABLE 0x0010
186 #define MPU401_IO_ENABLE 0x0008
187 #define GAME_IO_ENABLE 0x0004
188 #define FM_IO_ENABLE 0x0002
189 #define SB_IO_ENABLE 0x0001
190
191 /* Values for the ESM_CONFIG_A */
192
193 #define PIC_SNOOP1 0x4000
194 #define PIC_SNOOP2 0x2000
195 #define SAFEGUARD 0x0800
196 #define DMA_CLEAR 0x0700
197 #define DMA_DDMA 0x0000
198 #define DMA_TDMA 0x0100
199 #define DMA_PCPCI 0x0200
200 #define POST_WRITE 0x0080
201 #define PCI_TIMING 0x0040
202 #define SWAP_LR 0x0020
203 #define SUBTR_DECODE 0x0002
204
205 /* Values for the ESM_CONFIG_B */
206
207 #define SPDIF_CONFB 0x0100
208 #define HWV_CONFB 0x0080
209 #define DEBOUNCE 0x0040
210 #define GPIO_CONFB 0x0020
211 #define CHI_CONFB 0x0010
212 #define IDMA_CONFB 0x0008 /*undoc */
213 #define MIDI_FIX 0x0004 /*undoc */
214 #define IRQ_TO_ISA 0x0001 /*undoc */
215
216 /* Values for Ring Bus Control B */
217 #define RINGB_2CODEC_ID_MASK 0x0003
218 #define RINGB_DIS_VALIDATION 0x0008
219 #define RINGB_EN_SPDIF 0x0010
220 #define RINGB_EN_2CODEC 0x0020
221 #define RINGB_SING_BIT_DUAL 0x0040
222
223 /* ****Port Adresses**** */
224
225 /* Write & Read */
226 #define ESM_INDEX 0x02
227 #define ESM_DATA 0x00
228
229 /* AC97 + RingBus */
230 #define ESM_AC97_INDEX 0x30
231 #define ESM_AC97_DATA 0x32
232 #define ESM_RING_BUS_DEST 0x34
233 #define ESM_RING_BUS_CONTR_A 0x36
234 #define ESM_RING_BUS_CONTR_B 0x38
235 #define ESM_RING_BUS_SDO 0x3A
236
237 /* WaveCache*/
238 #define WC_INDEX 0x10
239 #define WC_DATA 0x12
240 #define WC_CONTROL 0x14
241
242 /* ASSP*/
243 #define ASSP_INDEX 0x80
244 #define ASSP_MEMORY 0x82
245 #define ASSP_DATA 0x84
246 #define ASSP_CONTROL_A 0xA2
247 #define ASSP_CONTROL_B 0xA4
248 #define ASSP_CONTROL_C 0xA6
249 #define ASSP_HOSTW_INDEX 0xA8
250 #define ASSP_HOSTW_DATA 0xAA
251 #define ASSP_HOSTW_IRQ 0xAC
252 /* Midi */
253 #define ESM_MPU401_PORT 0x98
254 /* Others */
255 #define ESM_PORT_HOST_IRQ 0x18
256
257 #define IDR0_DATA_PORT 0x00
258 #define IDR1_CRAM_POINTER 0x01
259 #define IDR2_CRAM_DATA 0x02
260 #define IDR3_WAVE_DATA 0x03
261 #define IDR4_WAVE_PTR_LOW 0x04
262 #define IDR5_WAVE_PTR_HI 0x05
263 #define IDR6_TIMER_CTRL 0x06
264 #define IDR7_WAVE_ROMRAM 0x07
265
266 #define WRITEABLE_MAP 0xEFFFFF
267 #define READABLE_MAP 0x64003F
268
269 /* PCI Register */
270
271 #define ESM_LEGACY_AUDIO_CONTROL 0x40
272 #define ESM_ACPI_COMMAND 0x54
273 #define ESM_CONFIG_A 0x50
274 #define ESM_CONFIG_B 0x52
275 #define ESM_DDMA 0x60
276
277 /* Bob Bits */
278 #define ESM_BOB_ENABLE 0x0001
279 #define ESM_BOB_START 0x0001
280
281 /* Host IRQ Control Bits */
282 #define ESM_RESET_MAESTRO 0x8000
283 #define ESM_RESET_DIRECTSOUND 0x4000
284 #define ESM_HIRQ_ClkRun 0x0100
285 #define ESM_HIRQ_HW_VOLUME 0x0040
286 #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
287 #define ESM_HIRQ_ASSP 0x0010
288 #define ESM_HIRQ_DSIE 0x0004
289 #define ESM_HIRQ_MPU401 0x0002
290 #define ESM_HIRQ_SB 0x0001
291
292 /* Host IRQ Status Bits */
293 #define ESM_MPU401_IRQ 0x02
294 #define ESM_SB_IRQ 0x01
295 #define ESM_SOUND_IRQ 0x04
296 #define ESM_ASSP_IRQ 0x10
297 #define ESM_HWVOL_IRQ 0x40
298
299 #define ESS_SYSCLK 50000000
300 #define ESM_BOB_FREQ 200
301 #define ESM_BOB_FREQ_MAX 800
302
303 #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
304 #define ESM_FREQ_ESM2 (50000000L / 1024L)
305
306 /* APU Modes: reg 0x00, bit 4-7 */
307 #define ESM_APU_MODE_SHIFT 4
308 #define ESM_APU_MODE_MASK (0xf << 4)
309 #define ESM_APU_OFF 0x00
310 #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
311 #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
312 #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
313 #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
314 #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
315 #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
316 #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
317 #define ESM_APU_CORRELATOR 0x08 /* Correlator */
318 #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
319 #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
320 #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
321 #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
322 #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
323 #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
324 #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
325
326 /* reg 0x00 */
327 #define ESM_APU_FILTER_Q_SHIFT 0
328 #define ESM_APU_FILTER_Q_MASK (3 << 0)
329 /* APU Filtey Q Control */
330 #define ESM_APU_FILTER_LESSQ 0x00
331 #define ESM_APU_FILTER_MOREQ 0x03
332
333 #define ESM_APU_FILTER_TYPE_SHIFT 2
334 #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
335 #define ESM_APU_ENV_TYPE_SHIFT 8
336 #define ESM_APU_ENV_TYPE_MASK (3 << 8)
337 #define ESM_APU_ENV_STATE_SHIFT 10
338 #define ESM_APU_ENV_STATE_MASK (3 << 10)
339 #define ESM_APU_END_CURVE (1 << 12)
340 #define ESM_APU_INT_ON_LOOP (1 << 13)
341 #define ESM_APU_DMA_ENABLE (1 << 14)
342
343 /* reg 0x02 */
344 #define ESM_APU_SUBMIX_GROUP_SHIRT 0
345 #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
346 #define ESM_APU_SUBMIX_MODE (1 << 3)
347 #define ESM_APU_6dB (1 << 4)
348 #define ESM_APU_DUAL_EFFECT (1 << 5)
349 #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
350 #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
351
352 /* reg 0x03 */
353 #define ESM_APU_STEP_SIZE_MASK 0x0fff
354
355 /* reg 0x04 */
356 #define ESM_APU_PHASE_SHIFT 0
357 #define ESM_APU_PHASE_MASK (0xff << 0)
358 #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
359 #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
360
361 /* reg 0x05 - wave start offset */
362 /* reg 0x06 - wave end offset */
363 /* reg 0x07 - wave loop length */
364
365 /* reg 0x08 */
366 #define ESM_APU_EFFECT_GAIN_SHIFT 0
367 #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
368 #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
369 #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
370 #define ESM_APU_TREMOLO_RATE_SHIFT 12
371 #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
372
373 /* reg 0x09 */
374 /* bit 0-7 amplitude dest? */
375 #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
376 #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
377
378 /* reg 0x0a */
379 #define ESM_APU_POLAR_PAN_SHIFT 0
380 #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
381 /* Polar Pan Control */
382 #define ESM_APU_PAN_CENTER_CIRCLE 0x00
383 #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
384 #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
385
386 #define ESM_APU_FILTER_TUNING_SHIFT 8
387 #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
388
389 /* reg 0x0b */
390 #define ESM_APU_DATA_SRC_A_SHIFT 0
391 #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
392 #define ESM_APU_INV_POL_A (1 << 7)
393 #define ESM_APU_DATA_SRC_B_SHIFT 8
394 #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
395 #define ESM_APU_INV_POL_B (1 << 15)
396
397 #define ESM_APU_VIBRATO_RATE_SHIFT 0
398 #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
399 #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
400 #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
401 #define ESM_APU_VIBRATO_PHASE_SHIFT 8
402 #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
403
404 /* reg 0x0c */
405 #define ESM_APU_RADIUS_SELECT (1 << 6)
406
407 /* APU Filter Control */
408 #define ESM_APU_FILTER_2POLE_LOPASS 0x00
409 #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
410 #define ESM_APU_FILTER_2POLE_HIPASS 0x02
411 #define ESM_APU_FILTER_1POLE_LOPASS 0x03
412 #define ESM_APU_FILTER_1POLE_HIPASS 0x04
413 #define ESM_APU_FILTER_OFF 0x05
414
415 /* APU ATFP Type */
416 #define ESM_APU_ATFP_AMPLITUDE 0x00
417 #define ESM_APU_ATFP_TREMELO 0x01
418 #define ESM_APU_ATFP_FILTER 0x02
419 #define ESM_APU_ATFP_PAN 0x03
420
421 /* APU ATFP Flags */
422 #define ESM_APU_ATFP_FLG_OFF 0x00
423 #define ESM_APU_ATFP_FLG_WAIT 0x01
424 #define ESM_APU_ATFP_FLG_DONE 0x02
425 #define ESM_APU_ATFP_FLG_INPROCESS 0x03
426
427
428 /* capture mixing buffer size */
429 #define ESM_MEM_ALIGN 0x1000
430 #define ESM_MIXBUF_SIZE 0x400
431
432 #define ESM_MODE_PLAY 0
433 #define ESM_MODE_CAPTURE 1
434
435
436 /* APU use in the driver */
437 enum snd_enum_apu_type {
438 ESM_APU_PCM_PLAY,
439 ESM_APU_PCM_CAPTURE,
440 ESM_APU_PCM_RATECONV,
441 ESM_APU_FREE
442 };
443
444 /* chip type */
445 enum {
446 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
447 };
448
449 /* DMA Hack! */
450 struct esm_memory {
451 struct snd_dma_buffer buf;
452 int empty; /* status */
453 struct list_head list;
454 };
455
456 /* Playback Channel */
457 struct esschan {
458 int running;
459
460 u8 apu[4];
461 u8 apu_mode[4];
462
463 /* playback/capture pcm buffer */
464 struct esm_memory *memory;
465 /* capture mixer buffer */
466 struct esm_memory *mixbuf;
467
468 unsigned int hwptr; /* current hw pointer in bytes */
469 unsigned int count; /* sample counter in bytes */
470 unsigned int dma_size; /* total buffer size in bytes */
471 unsigned int frag_size; /* period size in bytes */
472 unsigned int wav_shift;
473 u16 base[4]; /* offset for ptr */
474
475 /* stereo/16bit flag */
476 unsigned char fmt;
477 int mode; /* playback / capture */
478
479 int bob_freq; /* required timer frequency */
480
481 struct snd_pcm_substream *substream;
482
483 /* linked list */
484 struct list_head list;
485
486 #ifdef CONFIG_PM
487 u16 wc_map[4];
488 #endif
489 };
490
491 struct es1968 {
492 /* Module Config */
493 int total_bufsize; /* in bytes */
494
495 int playback_streams, capture_streams;
496
497 unsigned int clock; /* clock */
498 /* for clock measurement */
499 unsigned int in_measurement: 1;
500 unsigned int measure_apu;
501 unsigned int measure_lastpos;
502 unsigned int measure_count;
503
504 /* buffer */
505 struct snd_dma_buffer dma;
506
507 /* Resources... */
508 int irq;
509 unsigned long io_port;
510 int type;
511 struct pci_dev *pci;
512 struct snd_card *card;
513 struct snd_pcm *pcm;
514 int do_pm; /* power-management enabled */
515
516 /* DMA memory block */
517 struct list_head buf_list;
518
519 /* ALSA Stuff */
520 struct snd_ac97 *ac97;
521 struct snd_kcontrol *master_switch; /* for h/w volume control */
522 struct snd_kcontrol *master_volume;
523
524 struct snd_rawmidi *rmidi;
525
526 spinlock_t reg_lock;
527 spinlock_t ac97_lock;
528 struct tasklet_struct hwvol_tq;
529 unsigned int in_suspend;
530
531 /* Maestro Stuff */
532 u16 maestro_map[32];
533 int bobclient; /* active timer instancs */
534 int bob_freq; /* timer frequency */
535 struct mutex memory_mutex; /* memory lock */
536
537 /* APU states */
538 unsigned char apu[NR_APUS];
539
540 /* active substreams */
541 struct list_head substream_list;
542 spinlock_t substream_lock;
543
544 #ifdef CONFIG_PM
545 u16 apu_map[NR_APUS][NR_APU_REGS];
546 #endif
547
548 #ifdef SUPPORT_JOYSTICK
549 struct gameport *gameport;
550 #endif
551 };
552
553 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
554
555 static struct pci_device_id snd_es1968_ids[] = {
556 /* Maestro 1 */
557 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
558 /* Maestro 2 */
559 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
560 /* Maestro 2E */
561 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
562 { 0, }
563 };
564
565 MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
566
567 /* *********************
568 * Low Level Funcs! *
569 *********************/
570
571 /* no spinlock */
572 static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
573 {
574 outw(reg, chip->io_port + ESM_INDEX);
575 outw(data, chip->io_port + ESM_DATA);
576 chip->maestro_map[reg] = data;
577 }
578
579 static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
580 {
581 unsigned long flags;
582 spin_lock_irqsave(&chip->reg_lock, flags);
583 __maestro_write(chip, reg, data);
584 spin_unlock_irqrestore(&chip->reg_lock, flags);
585 }
586
587 /* no spinlock */
588 static u16 __maestro_read(struct es1968 *chip, u16 reg)
589 {
590 if (READABLE_MAP & (1 << reg)) {
591 outw(reg, chip->io_port + ESM_INDEX);
592 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
593 }
594 return chip->maestro_map[reg];
595 }
596
597 static inline u16 maestro_read(struct es1968 *chip, u16 reg)
598 {
599 unsigned long flags;
600 u16 result;
601 spin_lock_irqsave(&chip->reg_lock, flags);
602 result = __maestro_read(chip, reg);
603 spin_unlock_irqrestore(&chip->reg_lock, flags);
604 return result;
605 }
606
607 /* Wait for the codec bus to be free */
608 static int snd_es1968_ac97_wait(struct es1968 *chip)
609 {
610 int timeout = 100000;
611
612 while (timeout-- > 0) {
613 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
614 return 0;
615 cond_resched();
616 }
617 snd_printd("es1968: ac97 timeout\n");
618 return 1; /* timeout */
619 }
620
621 static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
622 {
623 struct es1968 *chip = ac97->private_data;
624 unsigned long flags;
625
626 snd_es1968_ac97_wait(chip);
627
628 /* Write the bus */
629 spin_lock_irqsave(&chip->ac97_lock, flags);
630 outw(val, chip->io_port + ESM_AC97_DATA);
631 /*msleep(1);*/
632 outb(reg, chip->io_port + ESM_AC97_INDEX);
633 /*msleep(1);*/
634 spin_unlock_irqrestore(&chip->ac97_lock, flags);
635 }
636
637 static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
638 {
639 u16 data = 0;
640 struct es1968 *chip = ac97->private_data;
641 unsigned long flags;
642
643 snd_es1968_ac97_wait(chip);
644
645 spin_lock_irqsave(&chip->ac97_lock, flags);
646 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
647 /*msleep(1);*/
648
649 if (! snd_es1968_ac97_wait(chip)) {
650 data = inw(chip->io_port + ESM_AC97_DATA);
651 /*msleep(1);*/
652 }
653 spin_unlock_irqrestore(&chip->ac97_lock, flags);
654
655 return data;
656 }
657
658 /* no spinlock */
659 static void apu_index_set(struct es1968 *chip, u16 index)
660 {
661 int i;
662 __maestro_write(chip, IDR1_CRAM_POINTER, index);
663 for (i = 0; i < 1000; i++)
664 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
665 return;
666 snd_printd("es1968: APU register select failed. (Timeout)\n");
667 }
668
669 /* no spinlock */
670 static void apu_data_set(struct es1968 *chip, u16 data)
671 {
672 int i;
673 for (i = 0; i < 1000; i++) {
674 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
675 return;
676 __maestro_write(chip, IDR0_DATA_PORT, data);
677 }
678 snd_printd("es1968: APU register set probably failed (Timeout)!\n");
679 }
680
681 /* no spinlock */
682 static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
683 {
684 snd_assert(channel < NR_APUS, return);
685 #ifdef CONFIG_PM
686 chip->apu_map[channel][reg] = data;
687 #endif
688 reg |= (channel << 4);
689 apu_index_set(chip, reg);
690 apu_data_set(chip, data);
691 }
692
693 static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
694 {
695 unsigned long flags;
696 spin_lock_irqsave(&chip->reg_lock, flags);
697 __apu_set_register(chip, channel, reg, data);
698 spin_unlock_irqrestore(&chip->reg_lock, flags);
699 }
700
701 static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
702 {
703 snd_assert(channel < NR_APUS, return 0);
704 reg |= (channel << 4);
705 apu_index_set(chip, reg);
706 return __maestro_read(chip, IDR0_DATA_PORT);
707 }
708
709 static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
710 {
711 unsigned long flags;
712 u16 v;
713 spin_lock_irqsave(&chip->reg_lock, flags);
714 v = __apu_get_register(chip, channel, reg);
715 spin_unlock_irqrestore(&chip->reg_lock, flags);
716 return v;
717 }
718
719 #if 0 /* ASSP is not supported */
720
721 static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
722 {
723 unsigned long flags;
724
725 spin_lock_irqsave(&chip->reg_lock, flags);
726 outl(reg, chip->io_port + ASSP_INDEX);
727 outl(value, chip->io_port + ASSP_DATA);
728 spin_unlock_irqrestore(&chip->reg_lock, flags);
729 }
730
731 static u32 assp_get_register(struct es1968 *chip, u32 reg)
732 {
733 unsigned long flags;
734 u32 value;
735
736 spin_lock_irqsave(&chip->reg_lock, flags);
737 outl(reg, chip->io_port + ASSP_INDEX);
738 value = inl(chip->io_port + ASSP_DATA);
739 spin_unlock_irqrestore(&chip->reg_lock, flags);
740
741 return value;
742 }
743
744 #endif
745
746 static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
747 {
748 unsigned long flags;
749
750 spin_lock_irqsave(&chip->reg_lock, flags);
751 outw(reg, chip->io_port + WC_INDEX);
752 outw(value, chip->io_port + WC_DATA);
753 spin_unlock_irqrestore(&chip->reg_lock, flags);
754 }
755
756 static u16 wave_get_register(struct es1968 *chip, u16 reg)
757 {
758 unsigned long flags;
759 u16 value;
760
761 spin_lock_irqsave(&chip->reg_lock, flags);
762 outw(reg, chip->io_port + WC_INDEX);
763 value = inw(chip->io_port + WC_DATA);
764 spin_unlock_irqrestore(&chip->reg_lock, flags);
765
766 return value;
767 }
768
769 /* *******************
770 * Bob the Timer! *
771 *******************/
772
773 static void snd_es1968_bob_stop(struct es1968 *chip)
774 {
775 u16 reg;
776
777 reg = __maestro_read(chip, 0x11);
778 reg &= ~ESM_BOB_ENABLE;
779 __maestro_write(chip, 0x11, reg);
780 reg = __maestro_read(chip, 0x17);
781 reg &= ~ESM_BOB_START;
782 __maestro_write(chip, 0x17, reg);
783 }
784
785 static void snd_es1968_bob_start(struct es1968 *chip)
786 {
787 int prescale;
788 int divide;
789
790 /* compute ideal interrupt frequency for buffer size & play rate */
791 /* first, find best prescaler value to match freq */
792 for (prescale = 5; prescale < 12; prescale++)
793 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
794 break;
795
796 /* next, back off prescaler whilst getting divider into optimum range */
797 divide = 1;
798 while ((prescale > 5) && (divide < 32)) {
799 prescale--;
800 divide <<= 1;
801 }
802 divide >>= 1;
803
804 /* now fine-tune the divider for best match */
805 for (; divide < 31; divide++)
806 if (chip->bob_freq >
807 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
808
809 /* divide = 0 is illegal, but don't let prescale = 4! */
810 if (divide == 0) {
811 divide++;
812 if (prescale > 5)
813 prescale--;
814 } else if (divide > 1)
815 divide--;
816
817 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
818
819 /* Now set IDR 11/17 */
820 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
821 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
822 }
823
824 /* call with substream spinlock */
825 static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
826 {
827 chip->bobclient++;
828 if (chip->bobclient == 1) {
829 chip->bob_freq = freq;
830 snd_es1968_bob_start(chip);
831 } else if (chip->bob_freq < freq) {
832 snd_es1968_bob_stop(chip);
833 chip->bob_freq = freq;
834 snd_es1968_bob_start(chip);
835 }
836 }
837
838 /* call with substream spinlock */
839 static void snd_es1968_bob_dec(struct es1968 *chip)
840 {
841 chip->bobclient--;
842 if (chip->bobclient <= 0)
843 snd_es1968_bob_stop(chip);
844 else if (chip->bob_freq > ESM_BOB_FREQ) {
845 /* check reduction of timer frequency */
846 int max_freq = ESM_BOB_FREQ;
847 struct esschan *es;
848 list_for_each_entry(es, &chip->substream_list, list) {
849 if (max_freq < es->bob_freq)
850 max_freq = es->bob_freq;
851 }
852 if (max_freq != chip->bob_freq) {
853 snd_es1968_bob_stop(chip);
854 chip->bob_freq = max_freq;
855 snd_es1968_bob_start(chip);
856 }
857 }
858 }
859
860 static int
861 snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
862 struct snd_pcm_runtime *runtime)
863 {
864 /* we acquire 4 interrupts per period for precise control.. */
865 int freq = runtime->rate * 4;
866 if (es->fmt & ESS_FMT_STEREO)
867 freq <<= 1;
868 if (es->fmt & ESS_FMT_16BIT)
869 freq <<= 1;
870 freq /= es->frag_size;
871 if (freq < ESM_BOB_FREQ)
872 freq = ESM_BOB_FREQ;
873 else if (freq > ESM_BOB_FREQ_MAX)
874 freq = ESM_BOB_FREQ_MAX;
875 return freq;
876 }
877
878
879 /*************
880 * PCM Part *
881 *************/
882
883 static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
884 {
885 u32 rate = (freq << 16) / chip->clock;
886 #if 0 /* XXX: do we need this? */
887 if (rate > 0x10000)
888 rate = 0x10000;
889 #endif
890 return rate;
891 }
892
893 /* get current pointer */
894 static inline unsigned int
895 snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
896 {
897 unsigned int offset;
898
899 offset = apu_get_register(chip, es->apu[0], 5);
900
901 offset -= es->base[0];
902
903 return (offset & 0xFFFE); /* hardware is in words */
904 }
905
906 static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
907 {
908 apu_set_register(chip, apu, 2,
909 (apu_get_register(chip, apu, 2) & 0x00FF) |
910 ((freq & 0xff) << 8) | 0x10);
911 apu_set_register(chip, apu, 3, freq >> 8);
912 }
913
914 /* spin lock held */
915 static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
916 {
917 /* set the APU mode */
918 __apu_set_register(esm, apu, 0,
919 (__apu_get_register(esm, apu, 0) & 0xff0f) |
920 (mode << 4));
921 }
922
923 static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
924 {
925 spin_lock(&chip->reg_lock);
926 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
927 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
928 if (es->mode == ESM_MODE_CAPTURE) {
929 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
930 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
931 }
932 if (es->fmt & ESS_FMT_STEREO) {
933 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
934 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
935 if (es->mode == ESM_MODE_CAPTURE) {
936 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
937 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
938 }
939 }
940 spin_unlock(&chip->reg_lock);
941 }
942
943 static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
944 {
945 spin_lock(&chip->reg_lock);
946 snd_es1968_trigger_apu(chip, es->apu[0], 0);
947 snd_es1968_trigger_apu(chip, es->apu[1], 0);
948 if (es->mode == ESM_MODE_CAPTURE) {
949 snd_es1968_trigger_apu(chip, es->apu[2], 0);
950 snd_es1968_trigger_apu(chip, es->apu[3], 0);
951 }
952 spin_unlock(&chip->reg_lock);
953 }
954
955 /* set the wavecache control reg */
956 static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
957 int channel, u32 addr, int capture)
958 {
959 u32 tmpval = (addr - 0x10) & 0xFFF8;
960
961 if (! capture) {
962 if (!(es->fmt & ESS_FMT_16BIT))
963 tmpval |= 4; /* 8bit */
964 if (es->fmt & ESS_FMT_STEREO)
965 tmpval |= 2; /* stereo */
966 }
967
968 /* set the wavecache control reg */
969 wave_set_register(chip, es->apu[channel] << 3, tmpval);
970
971 #ifdef CONFIG_PM
972 es->wc_map[channel] = tmpval;
973 #endif
974 }
975
976
977 static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
978 struct snd_pcm_runtime *runtime)
979 {
980 u32 pa;
981 int high_apu = 0;
982 int channel, apu;
983 int i, size;
984 unsigned long flags;
985 u32 freq;
986
987 size = es->dma_size >> es->wav_shift;
988
989 if (es->fmt & ESS_FMT_STEREO)
990 high_apu++;
991
992 for (channel = 0; channel <= high_apu; channel++) {
993 apu = es->apu[channel];
994
995 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
996
997 /* Offset to PCMBAR */
998 pa = es->memory->buf.addr;
999 pa -= chip->dma.addr;
1000 pa >>= 1; /* words */
1001
1002 pa |= 0x00400000; /* System RAM (Bit 22) */
1003
1004 if (es->fmt & ESS_FMT_STEREO) {
1005 /* Enable stereo */
1006 if (channel)
1007 pa |= 0x00800000; /* (Bit 23) */
1008 if (es->fmt & ESS_FMT_16BIT)
1009 pa >>= 1;
1010 }
1011
1012 /* base offset of dma calcs when reading the pointer
1013 on this left one */
1014 es->base[channel] = pa & 0xFFFF;
1015
1016 for (i = 0; i < 16; i++)
1017 apu_set_register(chip, apu, i, 0x0000);
1018
1019 /* Load the buffer into the wave engine */
1020 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1021 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1022 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1023 /* setting loop == sample len */
1024 apu_set_register(chip, apu, 7, size);
1025
1026 /* clear effects/env.. */
1027 apu_set_register(chip, apu, 8, 0x0000);
1028 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1029 apu_set_register(chip, apu, 9, 0xD000);
1030
1031 /* clear routing stuff */
1032 apu_set_register(chip, apu, 11, 0x0000);
1033 /* dma on, no envelopes, filter to all 1s) */
1034 apu_set_register(chip, apu, 0, 0x400F);
1035
1036 if (es->fmt & ESS_FMT_16BIT)
1037 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1038 else
1039 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1040
1041 if (es->fmt & ESS_FMT_STEREO) {
1042 /* set panning: left or right */
1043 /* Check: different panning. On my Canyon 3D Chipset the
1044 Channels are swapped. I don't know, about the output
1045 to the SPDif Link. Perhaps you have to change this
1046 and not the APU Regs 4-5. */
1047 apu_set_register(chip, apu, 10,
1048 0x8F00 | (channel ? 0 : 0x10));
1049 es->apu_mode[channel] += 1; /* stereo */
1050 } else
1051 apu_set_register(chip, apu, 10, 0x8F08);
1052 }
1053
1054 spin_lock_irqsave(&chip->reg_lock, flags);
1055 /* clear WP interrupts */
1056 outw(1, chip->io_port + 0x04);
1057 /* enable WP ints */
1058 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1059 spin_unlock_irqrestore(&chip->reg_lock, flags);
1060
1061 freq = runtime->rate;
1062 /* set frequency */
1063 if (freq > 48000)
1064 freq = 48000;
1065 if (freq < 4000)
1066 freq = 4000;
1067
1068 /* hmmm.. */
1069 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1070 freq >>= 1;
1071
1072 freq = snd_es1968_compute_rate(chip, freq);
1073
1074 /* Load the frequency, turn on 6dB */
1075 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1076 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1077 }
1078
1079
1080 static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1081 unsigned int pa, unsigned int bsize,
1082 int mode, int route)
1083 {
1084 int i, apu = es->apu[channel];
1085
1086 es->apu_mode[channel] = mode;
1087
1088 /* set the wavecache control reg */
1089 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1090
1091 /* Offset to PCMBAR */
1092 pa -= chip->dma.addr;
1093 pa >>= 1; /* words */
1094
1095 /* base offset of dma calcs when reading the pointer
1096 on this left one */
1097 es->base[channel] = pa & 0xFFFF;
1098 pa |= 0x00400000; /* bit 22 -> System RAM */
1099
1100 /* Begin loading the APU */
1101 for (i = 0; i < 16; i++)
1102 apu_set_register(chip, apu, i, 0x0000);
1103
1104 /* need to enable subgroups.. and we should probably
1105 have different groups for different /dev/dsps.. */
1106 apu_set_register(chip, apu, 2, 0x8);
1107
1108 /* Load the buffer into the wave engine */
1109 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1110 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1111 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1112 apu_set_register(chip, apu, 7, bsize);
1113 /* clear effects/env.. */
1114 apu_set_register(chip, apu, 8, 0x00F0);
1115 /* amplitude now? sure. why not. */
1116 apu_set_register(chip, apu, 9, 0x0000);
1117 /* set filter tune, radius, polar pan */
1118 apu_set_register(chip, apu, 10, 0x8F08);
1119 /* route input */
1120 apu_set_register(chip, apu, 11, route);
1121 /* dma on, no envelopes, filter to all 1s) */
1122 apu_set_register(chip, apu, 0, 0x400F);
1123 }
1124
1125 static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1126 struct snd_pcm_runtime *runtime)
1127 {
1128 int size;
1129 u32 freq;
1130 unsigned long flags;
1131
1132 size = es->dma_size >> es->wav_shift;
1133
1134 /* APU assignments:
1135 0 = mono/left SRC
1136 1 = right SRC
1137 2 = mono/left Input Mixer
1138 3 = right Input Mixer
1139 */
1140 /* data seems to flow from the codec, through an apu into
1141 the 'mixbuf' bit of page, then through the SRC apu
1142 and out to the real 'buffer'. ok. sure. */
1143
1144 /* input mixer (left/mono) */
1145 /* parallel in crap, see maestro reg 0xC [8-11] */
1146 init_capture_apu(chip, es, 2,
1147 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1148 ESM_APU_INPUTMIXER, 0x14);
1149 /* SRC (left/mono); get input from inputing apu */
1150 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1151 ESM_APU_SRCONVERTOR, es->apu[2]);
1152 if (es->fmt & ESS_FMT_STEREO) {
1153 /* input mixer (right) */
1154 init_capture_apu(chip, es, 3,
1155 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1156 ESM_MIXBUF_SIZE/4, /* in words */
1157 ESM_APU_INPUTMIXER, 0x15);
1158 /* SRC (right) */
1159 init_capture_apu(chip, es, 1,
1160 es->memory->buf.addr + size*2, size,
1161 ESM_APU_SRCONVERTOR, es->apu[3]);
1162 }
1163
1164 freq = runtime->rate;
1165 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1166 if (freq > 47999)
1167 freq = 47999;
1168 if (freq < 4000)
1169 freq = 4000;
1170
1171 freq = snd_es1968_compute_rate(chip, freq);
1172
1173 /* Load the frequency, turn on 6dB */
1174 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1175 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1176
1177 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1178 freq = 0x10000;
1179 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1180 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1181
1182 spin_lock_irqsave(&chip->reg_lock, flags);
1183 /* clear WP interrupts */
1184 outw(1, chip->io_port + 0x04);
1185 /* enable WP ints */
1186 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1187 spin_unlock_irqrestore(&chip->reg_lock, flags);
1188 }
1189
1190 /*******************
1191 * ALSA Interface *
1192 *******************/
1193
1194 static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1195 {
1196 struct es1968 *chip = snd_pcm_substream_chip(substream);
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 struct esschan *es = runtime->private_data;
1199
1200 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1201 es->frag_size = snd_pcm_lib_period_bytes(substream);
1202
1203 es->wav_shift = 1; /* maestro handles always 16bit */
1204 es->fmt = 0;
1205 if (snd_pcm_format_width(runtime->format) == 16)
1206 es->fmt |= ESS_FMT_16BIT;
1207 if (runtime->channels > 1) {
1208 es->fmt |= ESS_FMT_STEREO;
1209 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1210 es->wav_shift++;
1211 }
1212 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1213
1214 switch (es->mode) {
1215 case ESM_MODE_PLAY:
1216 snd_es1968_playback_setup(chip, es, runtime);
1217 break;
1218 case ESM_MODE_CAPTURE:
1219 snd_es1968_capture_setup(chip, es, runtime);
1220 break;
1221 }
1222
1223 return 0;
1224 }
1225
1226 static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1227 {
1228 struct es1968 *chip = snd_pcm_substream_chip(substream);
1229 struct esschan *es = substream->runtime->private_data;
1230
1231 spin_lock(&chip->substream_lock);
1232 switch (cmd) {
1233 case SNDRV_PCM_TRIGGER_START:
1234 case SNDRV_PCM_TRIGGER_RESUME:
1235 if (es->running)
1236 break;
1237 snd_es1968_bob_inc(chip, es->bob_freq);
1238 es->count = 0;
1239 es->hwptr = 0;
1240 snd_es1968_pcm_start(chip, es);
1241 es->running = 1;
1242 break;
1243 case SNDRV_PCM_TRIGGER_STOP:
1244 case SNDRV_PCM_TRIGGER_SUSPEND:
1245 if (! es->running)
1246 break;
1247 snd_es1968_pcm_stop(chip, es);
1248 es->running = 0;
1249 snd_es1968_bob_dec(chip);
1250 break;
1251 }
1252 spin_unlock(&chip->substream_lock);
1253 return 0;
1254 }
1255
1256 static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1257 {
1258 struct es1968 *chip = snd_pcm_substream_chip(substream);
1259 struct esschan *es = substream->runtime->private_data;
1260 unsigned int ptr;
1261
1262 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1263
1264 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1265 }
1266
1267 static struct snd_pcm_hardware snd_es1968_playback = {
1268 .info = (SNDRV_PCM_INFO_MMAP |
1269 SNDRV_PCM_INFO_MMAP_VALID |
1270 SNDRV_PCM_INFO_INTERLEAVED |
1271 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1272 /*SNDRV_PCM_INFO_PAUSE |*/
1273 SNDRV_PCM_INFO_RESUME),
1274 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1275 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1276 .rate_min = 4000,
1277 .rate_max = 48000,
1278 .channels_min = 1,
1279 .channels_max = 2,
1280 .buffer_bytes_max = 65536,
1281 .period_bytes_min = 256,
1282 .period_bytes_max = 65536,
1283 .periods_min = 1,
1284 .periods_max = 1024,
1285 .fifo_size = 0,
1286 };
1287
1288 static struct snd_pcm_hardware snd_es1968_capture = {
1289 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1290 SNDRV_PCM_INFO_MMAP |
1291 SNDRV_PCM_INFO_MMAP_VALID |
1292 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1293 /*SNDRV_PCM_INFO_PAUSE |*/
1294 SNDRV_PCM_INFO_RESUME),
1295 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1296 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1297 .rate_min = 4000,
1298 .rate_max = 48000,
1299 .channels_min = 1,
1300 .channels_max = 2,
1301 .buffer_bytes_max = 65536,
1302 .period_bytes_min = 256,
1303 .period_bytes_max = 65536,
1304 .periods_min = 1,
1305 .periods_max = 1024,
1306 .fifo_size = 0,
1307 };
1308
1309 /* *************************
1310 * DMA memory management *
1311 *************************/
1312
1313 /* Because the Maestro can only take addresses relative to the PCM base address
1314 register :( */
1315
1316 static int calc_available_memory_size(struct es1968 *chip)
1317 {
1318 int max_size = 0;
1319 struct esm_memory *buf;
1320
1321 mutex_lock(&chip->memory_mutex);
1322 list_for_each_entry(buf, &chip->buf_list, list) {
1323 if (buf->empty && buf->buf.bytes > max_size)
1324 max_size = buf->buf.bytes;
1325 }
1326 mutex_unlock(&chip->memory_mutex);
1327 if (max_size >= 128*1024)
1328 max_size = 127*1024;
1329 return max_size;
1330 }
1331
1332 /* allocate a new memory chunk with the specified size */
1333 static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1334 {
1335 struct esm_memory *buf;
1336
1337 size = ALIGN(size, ESM_MEM_ALIGN);
1338 mutex_lock(&chip->memory_mutex);
1339 list_for_each_entry(buf, &chip->buf_list, list) {
1340 if (buf->empty && buf->buf.bytes >= size)
1341 goto __found;
1342 }
1343 mutex_unlock(&chip->memory_mutex);
1344 return NULL;
1345
1346 __found:
1347 if (buf->buf.bytes > size) {
1348 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1349 if (chunk == NULL) {
1350 mutex_unlock(&chip->memory_mutex);
1351 return NULL;
1352 }
1353 chunk->buf = buf->buf;
1354 chunk->buf.bytes -= size;
1355 chunk->buf.area += size;
1356 chunk->buf.addr += size;
1357 chunk->empty = 1;
1358 buf->buf.bytes = size;
1359 list_add(&chunk->list, &buf->list);
1360 }
1361 buf->empty = 0;
1362 mutex_unlock(&chip->memory_mutex);
1363 return buf;
1364 }
1365
1366 /* free a memory chunk */
1367 static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1368 {
1369 struct esm_memory *chunk;
1370
1371 mutex_lock(&chip->memory_mutex);
1372 buf->empty = 1;
1373 if (buf->list.prev != &chip->buf_list) {
1374 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1375 if (chunk->empty) {
1376 chunk->buf.bytes += buf->buf.bytes;
1377 list_del(&buf->list);
1378 kfree(buf);
1379 buf = chunk;
1380 }
1381 }
1382 if (buf->list.next != &chip->buf_list) {
1383 chunk = list_entry(buf->list.next, struct esm_memory, list);
1384 if (chunk->empty) {
1385 buf->buf.bytes += chunk->buf.bytes;
1386 list_del(&chunk->list);
1387 kfree(chunk);
1388 }
1389 }
1390 mutex_unlock(&chip->memory_mutex);
1391 }
1392
1393 static void snd_es1968_free_dmabuf(struct es1968 *chip)
1394 {
1395 struct list_head *p;
1396
1397 if (! chip->dma.area)
1398 return;
1399 snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
1400 while ((p = chip->buf_list.next) != &chip->buf_list) {
1401 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1402 list_del(p);
1403 kfree(chunk);
1404 }
1405 }
1406
1407 static int __devinit
1408 snd_es1968_init_dmabuf(struct es1968 *chip)
1409 {
1410 int err;
1411 struct esm_memory *chunk;
1412
1413 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1414 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1415 if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
1416 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1417 snd_dma_pci_data(chip->pci),
1418 chip->total_bufsize, &chip->dma);
1419 if (err < 0 || ! chip->dma.area) {
1420 snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
1421 chip->total_bufsize);
1422 return -ENOMEM;
1423 }
1424 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1425 snd_dma_free_pages(&chip->dma);
1426 snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
1427 return -ENOMEM;
1428 }
1429 }
1430
1431 INIT_LIST_HEAD(&chip->buf_list);
1432 /* allocate an empty chunk */
1433 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1434 if (chunk == NULL) {
1435 snd_es1968_free_dmabuf(chip);
1436 return -ENOMEM;
1437 }
1438 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1439 chunk->buf = chip->dma;
1440 chunk->buf.area += ESM_MEM_ALIGN;
1441 chunk->buf.addr += ESM_MEM_ALIGN;
1442 chunk->buf.bytes -= ESM_MEM_ALIGN;
1443 chunk->empty = 1;
1444 list_add(&chunk->list, &chip->buf_list);
1445
1446 return 0;
1447 }
1448
1449 /* setup the dma_areas */
1450 /* buffer is extracted from the pre-allocated memory chunk */
1451 static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1452 struct snd_pcm_hw_params *hw_params)
1453 {
1454 struct es1968 *chip = snd_pcm_substream_chip(substream);
1455 struct snd_pcm_runtime *runtime = substream->runtime;
1456 struct esschan *chan = runtime->private_data;
1457 int size = params_buffer_bytes(hw_params);
1458
1459 if (chan->memory) {
1460 if (chan->memory->buf.bytes >= size) {
1461 runtime->dma_bytes = size;
1462 return 0;
1463 }
1464 snd_es1968_free_memory(chip, chan->memory);
1465 }
1466 chan->memory = snd_es1968_new_memory(chip, size);
1467 if (chan->memory == NULL) {
1468 // snd_printd("cannot allocate dma buffer: size = %d\n", size);
1469 return -ENOMEM;
1470 }
1471 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1472 return 1; /* area was changed */
1473 }
1474
1475 /* remove dma areas if allocated */
1476 static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1477 {
1478 struct es1968 *chip = snd_pcm_substream_chip(substream);
1479 struct snd_pcm_runtime *runtime = substream->runtime;
1480 struct esschan *chan;
1481
1482 if (runtime->private_data == NULL)
1483 return 0;
1484 chan = runtime->private_data;
1485 if (chan->memory) {
1486 snd_es1968_free_memory(chip, chan->memory);
1487 chan->memory = NULL;
1488 }
1489 return 0;
1490 }
1491
1492
1493 /*
1494 * allocate APU pair
1495 */
1496 static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1497 {
1498 int apu;
1499
1500 for (apu = 0; apu < NR_APUS; apu += 2) {
1501 if (chip->apu[apu] == ESM_APU_FREE &&
1502 chip->apu[apu + 1] == ESM_APU_FREE) {
1503 chip->apu[apu] = chip->apu[apu + 1] = type;
1504 return apu;
1505 }
1506 }
1507 return -EBUSY;
1508 }
1509
1510 /*
1511 * release APU pair
1512 */
1513 static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1514 {
1515 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1516 }
1517
1518
1519 /******************
1520 * PCM open/close *
1521 ******************/
1522
1523 static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1524 {
1525 struct es1968 *chip = snd_pcm_substream_chip(substream);
1526 struct snd_pcm_runtime *runtime = substream->runtime;
1527 struct esschan *es;
1528 int apu1;
1529
1530 /* search 2 APUs */
1531 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1532 if (apu1 < 0)
1533 return apu1;
1534
1535 es = kzalloc(sizeof(*es), GFP_KERNEL);
1536 if (!es) {
1537 snd_es1968_free_apu_pair(chip, apu1);
1538 return -ENOMEM;
1539 }
1540
1541 es->apu[0] = apu1;
1542 es->apu[1] = apu1 + 1;
1543 es->apu_mode[0] = 0;
1544 es->apu_mode[1] = 0;
1545 es->running = 0;
1546 es->substream = substream;
1547 es->mode = ESM_MODE_PLAY;
1548
1549 runtime->private_data = es;
1550 runtime->hw = snd_es1968_playback;
1551 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1552 calc_available_memory_size(chip);
1553
1554 spin_lock_irq(&chip->substream_lock);
1555 list_add(&es->list, &chip->substream_list);
1556 spin_unlock_irq(&chip->substream_lock);
1557
1558 return 0;
1559 }
1560
1561 static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1562 {
1563 struct snd_pcm_runtime *runtime = substream->runtime;
1564 struct es1968 *chip = snd_pcm_substream_chip(substream);
1565 struct esschan *es;
1566 int apu1, apu2;
1567
1568 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1569 if (apu1 < 0)
1570 return apu1;
1571 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1572 if (apu2 < 0) {
1573 snd_es1968_free_apu_pair(chip, apu1);
1574 return apu2;
1575 }
1576
1577 es = kzalloc(sizeof(*es), GFP_KERNEL);
1578 if (!es) {
1579 snd_es1968_free_apu_pair(chip, apu1);
1580 snd_es1968_free_apu_pair(chip, apu2);
1581 return -ENOMEM;
1582 }
1583
1584 es->apu[0] = apu1;
1585 es->apu[1] = apu1 + 1;
1586 es->apu[2] = apu2;
1587 es->apu[3] = apu2 + 1;
1588 es->apu_mode[0] = 0;
1589 es->apu_mode[1] = 0;
1590 es->apu_mode[2] = 0;
1591 es->apu_mode[3] = 0;
1592 es->running = 0;
1593 es->substream = substream;
1594 es->mode = ESM_MODE_CAPTURE;
1595
1596 /* get mixbuffer */
1597 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1598 snd_es1968_free_apu_pair(chip, apu1);
1599 snd_es1968_free_apu_pair(chip, apu2);
1600 kfree(es);
1601 return -ENOMEM;
1602 }
1603 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1604
1605 runtime->private_data = es;
1606 runtime->hw = snd_es1968_capture;
1607 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1608 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1609 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1610
1611 spin_lock_irq(&chip->substream_lock);
1612 list_add(&es->list, &chip->substream_list);
1613 spin_unlock_irq(&chip->substream_lock);
1614
1615 return 0;
1616 }
1617
1618 static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1619 {
1620 struct es1968 *chip = snd_pcm_substream_chip(substream);
1621 struct esschan *es;
1622
1623 if (substream->runtime->private_data == NULL)
1624 return 0;
1625 es = substream->runtime->private_data;
1626 spin_lock_irq(&chip->substream_lock);
1627 list_del(&es->list);
1628 spin_unlock_irq(&chip->substream_lock);
1629 snd_es1968_free_apu_pair(chip, es->apu[0]);
1630 kfree(es);
1631
1632 return 0;
1633 }
1634
1635 static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1636 {
1637 struct es1968 *chip = snd_pcm_substream_chip(substream);
1638 struct esschan *es;
1639
1640 if (substream->runtime->private_data == NULL)
1641 return 0;
1642 es = substream->runtime->private_data;
1643 spin_lock_irq(&chip->substream_lock);
1644 list_del(&es->list);
1645 spin_unlock_irq(&chip->substream_lock);
1646 snd_es1968_free_memory(chip, es->mixbuf);
1647 snd_es1968_free_apu_pair(chip, es->apu[0]);
1648 snd_es1968_free_apu_pair(chip, es->apu[2]);
1649 kfree(es);
1650
1651 return 0;
1652 }
1653
1654 static struct snd_pcm_ops snd_es1968_playback_ops = {
1655 .open = snd_es1968_playback_open,
1656 .close = snd_es1968_playback_close,
1657 .ioctl = snd_pcm_lib_ioctl,
1658 .hw_params = snd_es1968_hw_params,
1659 .hw_free = snd_es1968_hw_free,
1660 .prepare = snd_es1968_pcm_prepare,
1661 .trigger = snd_es1968_pcm_trigger,
1662 .pointer = snd_es1968_pcm_pointer,
1663 };
1664
1665 static struct snd_pcm_ops snd_es1968_capture_ops = {
1666 .open = snd_es1968_capture_open,
1667 .close = snd_es1968_capture_close,
1668 .ioctl = snd_pcm_lib_ioctl,
1669 .hw_params = snd_es1968_hw_params,
1670 .hw_free = snd_es1968_hw_free,
1671 .prepare = snd_es1968_pcm_prepare,
1672 .trigger = snd_es1968_pcm_trigger,
1673 .pointer = snd_es1968_pcm_pointer,
1674 };
1675
1676
1677 /*
1678 * measure clock
1679 */
1680 #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1681
1682 static void __devinit es1968_measure_clock(struct es1968 *chip)
1683 {
1684 int i, apu;
1685 unsigned int pa, offset, t;
1686 struct esm_memory *memory;
1687 struct timeval start_time, stop_time;
1688
1689 if (chip->clock == 0)
1690 chip->clock = 48000; /* default clock value */
1691
1692 /* search 2 APUs (although one apu is enough) */
1693 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1694 snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
1695 return;
1696 }
1697 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1698 snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
1699 snd_es1968_free_apu_pair(chip, apu);
1700 return;
1701 }
1702
1703 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1704
1705 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1706
1707 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1708 pa |= 0x00400000; /* System RAM (Bit 22) */
1709
1710 /* initialize apu */
1711 for (i = 0; i < 16; i++)
1712 apu_set_register(chip, apu, i, 0x0000);
1713
1714 apu_set_register(chip, apu, 0, 0x400f);
1715 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1716 apu_set_register(chip, apu, 5, pa & 0xffff);
1717 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1718 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1719 apu_set_register(chip, apu, 8, 0x0000);
1720 apu_set_register(chip, apu, 9, 0xD000);
1721 apu_set_register(chip, apu, 10, 0x8F08);
1722 apu_set_register(chip, apu, 11, 0x0000);
1723 spin_lock_irq(&chip->reg_lock);
1724 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1725 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1726 spin_unlock_irq(&chip->reg_lock);
1727
1728 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1729
1730 chip->in_measurement = 1;
1731 chip->measure_apu = apu;
1732 spin_lock_irq(&chip->reg_lock);
1733 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1734 __apu_set_register(chip, apu, 5, pa & 0xffff);
1735 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1736 do_gettimeofday(&start_time);
1737 spin_unlock_irq(&chip->reg_lock);
1738 msleep(50);
1739 spin_lock_irq(&chip->reg_lock);
1740 offset = __apu_get_register(chip, apu, 5);
1741 do_gettimeofday(&stop_time);
1742 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1743 snd_es1968_bob_dec(chip);
1744 chip->in_measurement = 0;
1745 spin_unlock_irq(&chip->reg_lock);
1746
1747 /* check the current position */
1748 offset -= (pa & 0xffff);
1749 offset &= 0xfffe;
1750 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1751
1752 t = stop_time.tv_sec - start_time.tv_sec;
1753 t *= 1000000;
1754 if (stop_time.tv_usec < start_time.tv_usec)
1755 t -= start_time.tv_usec - stop_time.tv_usec;
1756 else
1757 t += stop_time.tv_usec - start_time.tv_usec;
1758 if (t == 0) {
1759 snd_printk(KERN_ERR "?? calculation error..\n");
1760 } else {
1761 offset *= 1000;
1762 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1763 if (offset < 47500 || offset > 48500) {
1764 if (offset >= 40000 && offset <= 50000)
1765 chip->clock = (chip->clock * offset) / 48000;
1766 }
1767 printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
1768 }
1769 snd_es1968_free_memory(chip, memory);
1770 snd_es1968_free_apu_pair(chip, apu);
1771 }
1772
1773
1774 /*
1775 */
1776
1777 static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1778 {
1779 struct es1968 *esm = pcm->private_data;
1780 snd_es1968_free_dmabuf(esm);
1781 esm->pcm = NULL;
1782 }
1783
1784 static int __devinit
1785 snd_es1968_pcm(struct es1968 *chip, int device)
1786 {
1787 struct snd_pcm *pcm;
1788 int err;
1789
1790 /* get DMA buffer */
1791 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1792 return err;
1793
1794 /* set PCMBAR */
1795 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1796 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1797 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1798 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1799
1800 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1801 chip->playback_streams,
1802 chip->capture_streams, &pcm)) < 0)
1803 return err;
1804
1805 pcm->private_data = chip;
1806 pcm->private_free = snd_es1968_pcm_free;
1807
1808 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1809 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1810
1811 pcm->info_flags = 0;
1812
1813 strcpy(pcm->name, "ESS Maestro");
1814
1815 chip->pcm = pcm;
1816
1817 return 0;
1818 }
1819
1820 /*
1821 * update pointer
1822 */
1823 static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1824 {
1825 unsigned int hwptr;
1826 unsigned int diff;
1827 struct snd_pcm_substream *subs = es->substream;
1828
1829 if (subs == NULL || !es->running)
1830 return;
1831
1832 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1833 hwptr %= es->dma_size;
1834
1835 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1836
1837 es->hwptr = hwptr;
1838 es->count += diff;
1839
1840 if (es->count > es->frag_size) {
1841 spin_unlock(&chip->substream_lock);
1842 snd_pcm_period_elapsed(subs);
1843 spin_lock(&chip->substream_lock);
1844 es->count %= es->frag_size;
1845 }
1846 }
1847
1848 /*
1849 */
1850 static void es1968_update_hw_volume(unsigned long private_data)
1851 {
1852 struct es1968 *chip = (struct es1968 *) private_data;
1853 int x, val;
1854 unsigned long flags;
1855
1856 /* Figure out which volume control button was pushed,
1857 based on differences from the default register
1858 values. */
1859 x = inb(chip->io_port + 0x1c) & 0xee;
1860 /* Reset the volume control registers. */
1861 outb(0x88, chip->io_port + 0x1c);
1862 outb(0x88, chip->io_port + 0x1d);
1863 outb(0x88, chip->io_port + 0x1e);
1864 outb(0x88, chip->io_port + 0x1f);
1865
1866 if (chip->in_suspend)
1867 return;
1868
1869 if (! chip->master_switch || ! chip->master_volume)
1870 return;
1871
1872 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1873 spin_lock_irqsave(&chip->ac97_lock, flags);
1874 val = chip->ac97->regs[AC97_MASTER];
1875 switch (x) {
1876 case 0x88:
1877 /* mute */
1878 val ^= 0x8000;
1879 chip->ac97->regs[AC97_MASTER] = val;
1880 outw(val, chip->io_port + ESM_AC97_DATA);
1881 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1882 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1883 &chip->master_switch->id);
1884 break;
1885 case 0xaa:
1886 /* volume up */
1887 if ((val & 0x7f) > 0)
1888 val--;
1889 if ((val & 0x7f00) > 0)
1890 val -= 0x0100;
1891 chip->ac97->regs[AC97_MASTER] = val;
1892 outw(val, chip->io_port + ESM_AC97_DATA);
1893 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1894 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1895 &chip->master_volume->id);
1896 break;
1897 case 0x66:
1898 /* volume down */
1899 if ((val & 0x7f) < 0x1f)
1900 val++;
1901 if ((val & 0x7f00) < 0x1f00)
1902 val += 0x0100;
1903 chip->ac97->regs[AC97_MASTER] = val;
1904 outw(val, chip->io_port + ESM_AC97_DATA);
1905 outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
1906 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1907 &chip->master_volume->id);
1908 break;
1909 }
1910 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1911 }
1912
1913 /*
1914 * interrupt handler
1915 */
1916 static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1917 {
1918 struct es1968 *chip = dev_id;
1919 u32 event;
1920
1921 if (!(event = inb(chip->io_port + 0x1A)))
1922 return IRQ_NONE;
1923
1924 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1925
1926 if (event & ESM_HWVOL_IRQ)
1927 tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
1928
1929 /* else ack 'em all, i imagine */
1930 outb(0xFF, chip->io_port + 0x1A);
1931
1932 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1933 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1934 }
1935
1936 if (event & ESM_SOUND_IRQ) {
1937 struct esschan *es;
1938 spin_lock(&chip->substream_lock);
1939 list_for_each_entry(es, &chip->substream_list, list) {
1940 if (es->running)
1941 snd_es1968_update_pcm(chip, es);
1942 }
1943 spin_unlock(&chip->substream_lock);
1944 if (chip->in_measurement) {
1945 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1946 if (curp < chip->measure_lastpos)
1947 chip->measure_count++;
1948 chip->measure_lastpos = curp;
1949 }
1950 }
1951
1952 return IRQ_HANDLED;
1953 }
1954
1955 /*
1956 * Mixer stuff
1957 */
1958
1959 static int __devinit
1960 snd_es1968_mixer(struct es1968 *chip)
1961 {
1962 struct snd_ac97_bus *pbus;
1963 struct snd_ac97_template ac97;
1964 struct snd_ctl_elem_id id;
1965 int err;
1966 static struct snd_ac97_bus_ops ops = {
1967 .write = snd_es1968_ac97_write,
1968 .read = snd_es1968_ac97_read,
1969 };
1970
1971 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
1972 return err;
1973 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
1974
1975 memset(&ac97, 0, sizeof(ac97));
1976 ac97.private_data = chip;
1977 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
1978 return err;
1979
1980 /* attach master switch / volumes for h/w volume control */
1981 memset(&id, 0, sizeof(id));
1982 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1983 strcpy(id.name, "Master Playback Switch");
1984 chip->master_switch = snd_ctl_find_id(chip->card, &id);
1985 memset(&id, 0, sizeof(id));
1986 id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1987 strcpy(id.name, "Master Playback Volume");
1988 chip->master_volume = snd_ctl_find_id(chip->card, &id);
1989
1990 return 0;
1991 }
1992
1993 /*
1994 * reset ac97 codec
1995 */
1996
1997 static void snd_es1968_ac97_reset(struct es1968 *chip)
1998 {
1999 unsigned long ioaddr = chip->io_port;
2000
2001 unsigned short save_ringbus_a;
2002 unsigned short save_68;
2003 unsigned short w;
2004 unsigned int vend;
2005
2006 /* save configuration */
2007 save_ringbus_a = inw(ioaddr + 0x36);
2008
2009 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2010 /* set command/status address i/o to 1st codec */
2011 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2012 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2013
2014 /* disable ac link */
2015 outw(0x0000, ioaddr + 0x36);
2016 save_68 = inw(ioaddr + 0x68);
2017 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2018 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2019 if (w & 1)
2020 save_68 |= 0x10;
2021 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2022 outw(0x0001, ioaddr + 0x68); /* gpio write */
2023 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2024 udelay(20);
2025 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2026 msleep(20);
2027
2028 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2029 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2030 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2031 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2032
2033 /* now the second codec */
2034 /* disable ac link */
2035 outw(0x0000, ioaddr + 0x36);
2036 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2037 save_68 = inw(ioaddr + 0x68);
2038 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2039 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2040 udelay(20);
2041 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2042 msleep(500);
2043 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2044 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2045 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2046
2047 #if 0 /* the loop here needs to be much better if we want it.. */
2048 snd_printk(KERN_INFO "trying software reset\n");
2049 /* try and do a software reset */
2050 outb(0x80 | 0x7c, ioaddr + 0x30);
2051 for (w = 0;; w++) {
2052 if ((inw(ioaddr + 0x30) & 1) == 0) {
2053 if (inb(ioaddr + 0x32) != 0)
2054 break;
2055
2056 outb(0x80 | 0x7d, ioaddr + 0x30);
2057 if (((inw(ioaddr + 0x30) & 1) == 0)
2058 && (inb(ioaddr + 0x32) != 0))
2059 break;
2060 outb(0x80 | 0x7f, ioaddr + 0x30);
2061 if (((inw(ioaddr + 0x30) & 1) == 0)
2062 && (inb(ioaddr + 0x32) != 0))
2063 break;
2064 }
2065
2066 if (w > 10000) {
2067 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2068 msleep(500); /* oh my.. */
2069 outb(inb(ioaddr + 0x37) & ~0x08,
2070 ioaddr + 0x37);
2071 udelay(1);
2072 outw(0x80, ioaddr + 0x30);
2073 for (w = 0; w < 10000; w++) {
2074 if ((inw(ioaddr + 0x30) & 1) == 0)
2075 break;
2076 }
2077 }
2078 }
2079 #endif
2080 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2081 /* turn on external amp? */
2082 outw(0xf9ff, ioaddr + 0x64);
2083 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2084 outw(0x0209, ioaddr + 0x60);
2085 }
2086
2087 /* restore.. */
2088 outw(save_ringbus_a, ioaddr + 0x36);
2089
2090 /* Turn on the 978 docking chip.
2091 First frob the "master output enable" bit,
2092 then set most of the playback volume control registers to max. */
2093 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2094 outb(0xff, ioaddr+0xc3);
2095 outb(0xff, ioaddr+0xc4);
2096 outb(0xff, ioaddr+0xc6);
2097 outb(0xff, ioaddr+0xc8);
2098 outb(0x3f, ioaddr+0xcf);
2099 outb(0x3f, ioaddr+0xd0);
2100 }
2101
2102 static void snd_es1968_reset(struct es1968 *chip)
2103 {
2104 /* Reset */
2105 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2106 chip->io_port + ESM_PORT_HOST_IRQ);
2107 udelay(10);
2108 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2109 udelay(10);
2110 }
2111
2112 /*
2113 * initialize maestro chip
2114 */
2115 static void snd_es1968_chip_init(struct es1968 *chip)
2116 {
2117 struct pci_dev *pci = chip->pci;
2118 int i;
2119 unsigned long iobase = chip->io_port;
2120 u16 w;
2121 u32 n;
2122
2123 /* We used to muck around with pci config space that
2124 * we had no business messing with. We don't know enough
2125 * about the machine to know which DMA mode is appropriate,
2126 * etc. We were guessing wrong on some machines and making
2127 * them unhappy. We now trust in the BIOS to do things right,
2128 * which almost certainly means a new host of problems will
2129 * arise with broken BIOS implementations. screw 'em.
2130 * We're already intolerant of machines that don't assign
2131 * IRQs.
2132 */
2133
2134 /* Config Reg A */
2135 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2136
2137 w &= ~DMA_CLEAR; /* Clear DMA bits */
2138 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2139 w &= ~SAFEGUARD; /* Safeguard off */
2140 w |= POST_WRITE; /* Posted write */
2141 w |= PCI_TIMING; /* PCI timing on */
2142 /* XXX huh? claims to be reserved.. */
2143 w &= ~SWAP_LR; /* swap left/right
2144 seems to only have effect on SB
2145 Emulation */
2146 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2147
2148 pci_write_config_word(pci, ESM_CONFIG_A, w);
2149
2150 /* Config Reg B */
2151
2152 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2153
2154 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2155 /* XXX how do we know which to use? */
2156 w &= ~(1 << 14); /* External clock */
2157
2158 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2159 w |= HWV_CONFB; /* HWV on */
2160 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2161 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2162 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2163 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2164 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2165 w &= ~(1 << 1); /* reserved, always write 0 */
2166 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2167
2168 pci_write_config_word(pci, ESM_CONFIG_B, w);
2169
2170 /* DDMA off */
2171
2172 pci_read_config_word(pci, ESM_DDMA, &w);
2173 w &= ~(1 << 0);
2174 pci_write_config_word(pci, ESM_DDMA, w);
2175
2176 /*
2177 * Legacy mode
2178 */
2179
2180 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2181
2182 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2183 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2184 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2185
2186 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2187
2188 /* Set up 978 docking control chip. */
2189 pci_read_config_word(pci, 0x58, &w);
2190 w|=1<<2; /* Enable 978. */
2191 w|=1<<3; /* Turn on 978 hardware volume control. */
2192 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2193 pci_write_config_word(pci, 0x58, w);
2194
2195 /* Sound Reset */
2196
2197 snd_es1968_reset(chip);
2198
2199 /*
2200 * Ring Bus Setup
2201 */
2202
2203 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2204 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2205 udelay(20);
2206 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2207 udelay(20);
2208
2209 /*
2210 * Reset the CODEC
2211 */
2212
2213 snd_es1968_ac97_reset(chip);
2214
2215 /* Ring Bus Control B */
2216
2217 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2218 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2219 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2220 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2221
2222 /* Set hardware volume control registers to midpoints.
2223 We can tell which button was pushed based on how they change. */
2224 outb(0x88, iobase+0x1c);
2225 outb(0x88, iobase+0x1d);
2226 outb(0x88, iobase+0x1e);
2227 outb(0x88, iobase+0x1f);
2228
2229 /* it appears some maestros (dell 7500) only work if these are set,
2230 regardless of wether we use the assp or not. */
2231
2232 outb(0, iobase + ASSP_CONTROL_B);
2233 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2234 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2235
2236 /*
2237 * set up wavecache
2238 */
2239 for (i = 0; i < 16; i++) {
2240 /* Write 0 into the buffer area 0x1E0->1EF */
2241 outw(0x01E0 + i, iobase + WC_INDEX);
2242 outw(0x0000, iobase + WC_DATA);
2243
2244 /* The 1.10 test program seem to write 0 into the buffer area
2245 * 0x1D0-0x1DF too.*/
2246 outw(0x01D0 + i, iobase + WC_INDEX);
2247 outw(0x0000, iobase + WC_DATA);
2248 }
2249 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2250 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2251 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2252 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2253 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2254 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2255 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2256 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2257
2258
2259 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2260 /* Now back to the DirectSound stuff */
2261 /* audio serial configuration.. ? */
2262 maestro_write(chip, 0x08, 0xB004);
2263 maestro_write(chip, 0x09, 0x001B);
2264 maestro_write(chip, 0x0A, 0x8000);
2265 maestro_write(chip, 0x0B, 0x3F37);
2266 maestro_write(chip, 0x0C, 0x0098);
2267
2268 /* parallel in, has something to do with recording :) */
2269 maestro_write(chip, 0x0C,
2270 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2271 /* parallel out */
2272 maestro_write(chip, 0x0C,
2273 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2274
2275 maestro_write(chip, 0x0D, 0x7632);
2276
2277 /* Wave cache control on - test off, sg off,
2278 enable, enable extra chans 1Mb */
2279
2280 w = inw(iobase + WC_CONTROL);
2281
2282 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2283 w |= 0xA000; /* reserved... I don't know */
2284 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2285 Seems to crash the Computer if enabled... */
2286 w |= 0x0100; /* Wave Cache Operation Enabled */
2287 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2288 w &= ~0x0060; /* Clear Wavtable Size */
2289 w |= 0x0020; /* Wavetable Size : 1MB */
2290 /* Bit 4 is reserved */
2291 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2292 /* Bit 1 is reserved */
2293 w &= ~0x0001; /* Test Mode off */
2294
2295 outw(w, iobase + WC_CONTROL);
2296
2297 /* Now clear the APU control ram */
2298 for (i = 0; i < NR_APUS; i++) {
2299 for (w = 0; w < NR_APU_REGS; w++)
2300 apu_set_register(chip, i, w, 0);
2301
2302 }
2303 }
2304
2305 /* Enable IRQ's */
2306 static void snd_es1968_start_irq(struct es1968 *chip)
2307 {
2308 unsigned short w;
2309 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2310 if (chip->rmidi)
2311 w |= ESM_HIRQ_MPU401;
2312 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2313 }
2314
2315 #ifdef CONFIG_PM
2316 /*
2317 * PM support
2318 */
2319 static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
2320 {
2321 struct snd_card *card = pci_get_drvdata(pci);
2322 struct es1968 *chip = card->private_data;
2323
2324 if (! chip->do_pm)
2325 return 0;
2326
2327 chip->in_suspend = 1;
2328 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2329 snd_pcm_suspend_all(chip->pcm);
2330 snd_ac97_suspend(chip->ac97);
2331 snd_es1968_bob_stop(chip);
2332
2333 pci_disable_device(pci);
2334 pci_save_state(pci);
2335 pci_set_power_state(pci, pci_choose_state(pci, state));
2336 return 0;
2337 }
2338
2339 static int es1968_resume(struct pci_dev *pci)
2340 {
2341 struct snd_card *card = pci_get_drvdata(pci);
2342 struct es1968 *chip = card->private_data;
2343 struct esschan *es;
2344
2345 if (! chip->do_pm)
2346 return 0;
2347
2348 /* restore all our config */
2349 pci_set_power_state(pci, PCI_D0);
2350 pci_restore_state(pci);
2351 if (pci_enable_device(pci) < 0) {
2352 printk(KERN_ERR "es1968: pci_enable_device failed, "
2353 "disabling device\n");
2354 snd_card_disconnect(card);
2355 return -EIO;
2356 }
2357 pci_set_master(pci);
2358
2359 snd_es1968_chip_init(chip);
2360
2361 /* need to restore the base pointers.. */
2362 if (chip->dma.addr) {
2363 /* set PCMBAR */
2364 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2365 }
2366
2367 snd_es1968_start_irq(chip);
2368
2369 /* restore ac97 state */
2370 snd_ac97_resume(chip->ac97);
2371
2372 list_for_each_entry(es, &chip->substream_list, list) {
2373 switch (es->mode) {
2374 case ESM_MODE_PLAY:
2375 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2376 break;
2377 case ESM_MODE_CAPTURE:
2378 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2379 break;
2380 }
2381 }
2382
2383 /* start timer again */
2384 if (chip->bobclient)
2385 snd_es1968_bob_start(chip);
2386
2387 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2388 chip->in_suspend = 0;
2389 return 0;
2390 }
2391 #endif /* CONFIG_PM */
2392
2393 #ifdef SUPPORT_JOYSTICK
2394 #define JOYSTICK_ADDR 0x200
2395 static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
2396 {
2397 struct gameport *gp;
2398 struct resource *r;
2399 u16 val;
2400
2401 if (!joystick[dev])
2402 return -ENODEV;
2403
2404 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2405 if (!r)
2406 return -EBUSY;
2407
2408 chip->gameport = gp = gameport_allocate_port();
2409 if (!gp) {
2410 printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
2411 release_and_free_resource(r);
2412 return -ENOMEM;
2413 }
2414
2415 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2416 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2417
2418 gameport_set_name(gp, "ES1968 Gameport");
2419 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2420 gameport_set_dev_parent(gp, &chip->pci->dev);
2421 gp->io = JOYSTICK_ADDR;
2422 gameport_set_port_data(gp, r);
2423
2424 gameport_register_port(gp);
2425
2426 return 0;
2427 }
2428
2429 static void snd_es1968_free_gameport(struct es1968 *chip)
2430 {
2431 if (chip->gameport) {
2432 struct resource *r = gameport_get_port_data(chip->gameport);
2433
2434 gameport_unregister_port(chip->gameport);
2435 chip->gameport = NULL;
2436
2437 release_and_free_resource(r);
2438 }
2439 }
2440 #else
2441 static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2442 static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2443 #endif
2444
2445 static int snd_es1968_free(struct es1968 *chip)
2446 {
2447 if (chip->io_port) {
2448 synchronize_irq(chip->irq);
2449 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2450 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2451 }
2452
2453 if (chip->irq >= 0)
2454 free_irq(chip->irq, chip);
2455 snd_es1968_free_gameport(chip);
2456 chip->master_switch = NULL;
2457 chip->master_volume = NULL;
2458 pci_release_regions(chip->pci);
2459 pci_disable_device(chip->pci);
2460 kfree(chip);
2461 return 0;
2462 }
2463
2464 static int snd_es1968_dev_free(struct snd_device *device)
2465 {
2466 struct es1968 *chip = device->device_data;
2467 return snd_es1968_free(chip);
2468 }
2469
2470 struct ess_device_list {
2471 unsigned short type; /* chip type */
2472 unsigned short vendor; /* subsystem vendor id */
2473 };
2474
2475 static struct ess_device_list pm_whitelist[] __devinitdata = {
2476 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2477 { TYPE_MAESTRO2E, 0x1028 },
2478 { TYPE_MAESTRO2E, 0x103c },
2479 { TYPE_MAESTRO2E, 0x1179 },
2480 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2481 { TYPE_MAESTRO2E, 0x1558 },
2482 };
2483
2484 static struct ess_device_list mpu_blacklist[] __devinitdata = {
2485 { TYPE_MAESTRO2, 0x125d },
2486 };
2487
2488 static int __devinit snd_es1968_create(struct snd_card *card,
2489 struct pci_dev *pci,
2490 int total_bufsize,
2491 int play_streams,
2492 int capt_streams,
2493 int chip_type,
2494 int do_pm,
2495 struct es1968 **chip_ret)
2496 {
2497 static struct snd_device_ops ops = {
2498 .dev_free = snd_es1968_dev_free,
2499 };
2500 struct es1968 *chip;
2501 int i, err;
2502
2503 *chip_ret = NULL;
2504
2505 /* enable PCI device */
2506 if ((err = pci_enable_device(pci)) < 0)
2507 return err;
2508 /* check, if we can restrict PCI DMA transfers to 28 bits */
2509 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2510 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2511 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2512 pci_disable_device(pci);
2513 return -ENXIO;
2514 }
2515
2516 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2517 if (! chip) {
2518 pci_disable_device(pci);
2519 return -ENOMEM;
2520 }
2521
2522 /* Set Vars */
2523 chip->type = chip_type;
2524 spin_lock_init(&chip->reg_lock);
2525 spin_lock_init(&chip->substream_lock);
2526 INIT_LIST_HEAD(&chip->buf_list);
2527 INIT_LIST_HEAD(&chip->substream_list);
2528 spin_lock_init(&chip->ac97_lock);
2529 mutex_init(&chip->memory_mutex);
2530 tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
2531 chip->card = card;
2532 chip->pci = pci;
2533 chip->irq = -1;
2534 chip->total_bufsize = total_bufsize; /* in bytes */
2535 chip->playback_streams = play_streams;
2536 chip->capture_streams = capt_streams;
2537
2538 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2539 kfree(chip);
2540 pci_disable_device(pci);
2541 return err;
2542 }
2543 chip->io_port = pci_resource_start(pci, 0);
2544 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2545 "ESS Maestro", chip)) {
2546 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2547 snd_es1968_free(chip);
2548 return -EBUSY;
2549 }
2550 chip->irq = pci->irq;
2551
2552 /* Clear Maestro_map */
2553 for (i = 0; i < 32; i++)
2554 chip->maestro_map[i] = 0;
2555
2556 /* Clear Apu Map */
2557 for (i = 0; i < NR_APUS; i++)
2558 chip->apu[i] = ESM_APU_FREE;
2559
2560 /* just to be sure */
2561 pci_set_master(pci);
2562
2563 if (do_pm > 1) {
2564 /* disable power-management if not on the whitelist */
2565 unsigned short vend;
2566 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2567 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2568 if (chip->type == pm_whitelist[i].type &&
2569 vend == pm_whitelist[i].vendor) {
2570 do_pm = 1;
2571 break;
2572 }
2573 }
2574 if (do_pm > 1) {
2575 /* not matched; disabling pm */
2576 printk(KERN_INFO "es1968: not attempting power management.\n");
2577 do_pm = 0;
2578 }
2579 }
2580 chip->do_pm = do_pm;
2581
2582 snd_es1968_chip_init(chip);
2583
2584 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2585 snd_es1968_free(chip);
2586 return err;
2587 }
2588
2589 snd_card_set_dev(card, &pci->dev);
2590
2591 *chip_ret = chip;
2592
2593 return 0;
2594 }
2595
2596
2597 /*
2598 */
2599 static int __devinit snd_es1968_probe(struct pci_dev *pci,
2600 const struct pci_device_id *pci_id)
2601 {
2602 static int dev;
2603 struct snd_card *card;
2604 struct es1968 *chip;
2605 unsigned int i;
2606 int err;
2607
2608 if (dev >= SNDRV_CARDS)
2609 return -ENODEV;
2610 if (!enable[dev]) {
2611 dev++;
2612 return -ENOENT;
2613 }
2614
2615 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2616 if (!card)
2617 return -ENOMEM;
2618
2619 if (total_bufsize[dev] < 128)
2620 total_bufsize[dev] = 128;
2621 if (total_bufsize[dev] > 4096)
2622 total_bufsize[dev] = 4096;
2623 if ((err = snd_es1968_create(card, pci,
2624 total_bufsize[dev] * 1024, /* in bytes */
2625 pcm_substreams_p[dev],
2626 pcm_substreams_c[dev],
2627 pci_id->driver_data,
2628 use_pm[dev],
2629 &chip)) < 0) {
2630 snd_card_free(card);
2631 return err;
2632 }
2633 card->private_data = chip;
2634
2635 switch (chip->type) {
2636 case TYPE_MAESTRO2E:
2637 strcpy(card->driver, "ES1978");
2638 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2639 break;
2640 case TYPE_MAESTRO2:
2641 strcpy(card->driver, "ES1968");
2642 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2643 break;
2644 case TYPE_MAESTRO:
2645 strcpy(card->driver, "ESM1");
2646 strcpy(card->shortname, "ESS Maestro 1");
2647 break;
2648 }
2649
2650 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2651 snd_card_free(card);
2652 return err;
2653 }
2654
2655 if ((err = snd_es1968_mixer(chip)) < 0) {
2656 snd_card_free(card);
2657 return err;
2658 }
2659
2660 if (enable_mpu[dev] == 2) {
2661 /* check the black list */
2662 unsigned short vend;
2663 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2664 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2665 if (chip->type == mpu_blacklist[i].type &&
2666 vend == mpu_blacklist[i].vendor) {
2667 enable_mpu[dev] = 0;
2668 break;
2669 }
2670 }
2671 }
2672 if (enable_mpu[dev]) {
2673 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2674 chip->io_port + ESM_MPU401_PORT,
2675 MPU401_INFO_INTEGRATED,
2676 chip->irq, 0, &chip->rmidi)) < 0) {
2677 printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
2678 }
2679 }
2680
2681 snd_es1968_create_gameport(chip, dev);
2682
2683 snd_es1968_start_irq(chip);
2684
2685 chip->clock = clock[dev];
2686 if (! chip->clock)
2687 es1968_measure_clock(chip);
2688
2689 sprintf(card->longname, "%s at 0x%lx, irq %i",
2690 card->shortname, chip->io_port, chip->irq);
2691
2692 if ((err = snd_card_register(card)) < 0) {
2693 snd_card_free(card);
2694 return err;
2695 }
2696 pci_set_drvdata(pci, card);
2697 dev++;
2698 return 0;
2699 }
2700
2701 static void __devexit snd_es1968_remove(struct pci_dev *pci)
2702 {
2703 snd_card_free(pci_get_drvdata(pci));
2704 pci_set_drvdata(pci, NULL);
2705 }
2706
2707 static struct pci_driver driver = {
2708 .name = "ES1968 (ESS Maestro)",
2709 .id_table = snd_es1968_ids,
2710 .probe = snd_es1968_probe,
2711 .remove = __devexit_p(snd_es1968_remove),
2712 #ifdef CONFIG_PM
2713 .suspend = es1968_suspend,
2714 .resume = es1968_resume,
2715 #endif
2716 };
2717
2718 static int __init alsa_card_es1968_init(void)
2719 {
2720 return pci_register_driver(&driver);
2721 }
2722
2723 static void __exit alsa_card_es1968_exit(void)
2724 {
2725 pci_unregister_driver(&driver);
2726 }
2727
2728 module_init(alsa_card_es1968_init)
2729 module_exit(alsa_card_es1968_exit)
Linux with added FPC-III support