arch/arm/kernel/perf_event.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
  11  * code.
  12  */
  13 #define pr_fmt(fmt) "hw perfevents: " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/uaccess.h>
  19
  20 #include <asm/irq_regs.h>
  21 #include <asm/pmu.h>
  22 #include <asm/stacktrace.h>
  23
  24 static int
  25 armpmu_map_cache_event(const unsigned (*cache_map)
  26                                       [PERF_COUNT_HW_CACHE_MAX]
  27                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  28                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  29                        u64 config)
  30 {
  31         unsigned int cache_type, cache_op, cache_result, ret;
  32
  33         cache_type = (config >>  0) & 0xff;
  34         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  35                 return -EINVAL;
  36
  37         cache_op = (config >>  8) & 0xff;
  38         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  39                 return -EINVAL;
  40
  41         cache_result = (config >> 16) & 0xff;
  42         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  43                 return -EINVAL;
  44
  45         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  46
  47         if (ret == CACHE_OP_UNSUPPORTED)
  48                 return -ENOENT;
  49
  50         return ret;
  51 }
  52
  53 static int
  54 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  55 {
  56         int mapping;
  57
  58         if (config >= PERF_COUNT_HW_MAX)
  59                 return -EINVAL;
  60
  61         mapping = (*event_map)[config];
  62         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  63 }
  64
  65 static int
  66 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  67 {
  68         return (int)(config & raw_event_mask);
  69 }
  70
  71 int
  72 armpmu_map_event(struct perf_event *event,
  73                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  74                  const unsigned (*cache_map)
  75                                 [PERF_COUNT_HW_CACHE_MAX]
  76                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  77                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  78                  u32 raw_event_mask)
  79 {
  80         u64 config = event->attr.config;
  81
  82         switch (event->attr.type) {
  83         case PERF_TYPE_HARDWARE:
  84                 return armpmu_map_hw_event(event_map, config);
  85         case PERF_TYPE_HW_CACHE:
  86                 return armpmu_map_cache_event(cache_map, config);
  87         case PERF_TYPE_RAW:
  88                 return armpmu_map_raw_event(raw_event_mask, config);
  89         }
  90
  91         return -ENOENT;
  92 }
  93
  94 int armpmu_event_set_period(struct perf_event *event)
  95 {
  96         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
  97         struct hw_perf_event *hwc = &event->hw;
  98         s64 left = local64_read(&hwc->period_left);
  99         s64 period = hwc->sample_period;
 100         int ret = 0;
 101
 102         /* The period may have been changed by PERF_EVENT_IOC_PERIOD */
 103         if (unlikely(period != hwc->last_period))
 104                 left = period - (hwc->last_period - left);
 105
 106         if (unlikely(left <= -period)) {
 107                 left = period;
 108                 local64_set(&hwc->period_left, left);
 109                 hwc->last_period = period;
 110                 ret = 1;
 111         }
 112
 113         if (unlikely(left <= 0)) {
 114                 left += period;
 115                 local64_set(&hwc->period_left, left);
 116                 hwc->last_period = period;
 117                 ret = 1;
 118         }
 119
 120         if (left > (s64)armpmu->max_period)
 121                 left = armpmu->max_period;
 122
 123         local64_set(&hwc->prev_count, (u64)-left);
 124
 125         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 126
 127         perf_event_update_userpage(event);
 128
 129         return ret;
 130 }
 131
 132 u64 armpmu_event_update(struct perf_event *event)
 133 {
 134         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 135         struct hw_perf_event *hwc = &event->hw;
 136         u64 delta, prev_raw_count, new_raw_count;
 137
 138 again:
 139         prev_raw_count = local64_read(&hwc->prev_count);
 140         new_raw_count = armpmu->read_counter(event);
 141
 142         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 143                              new_raw_count) != prev_raw_count)
 144                 goto again;
 145
 146         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 147
 148         local64_add(delta, &event->count);
 149         local64_sub(delta, &hwc->period_left);
 150
 151         return new_raw_count;
 152 }
 153
 154 static void
 155 armpmu_read(struct perf_event *event)
 156 {
 157         armpmu_event_update(event);
 158 }
 159
 160 static void
 161 armpmu_stop(struct perf_event *event, int flags)
 162 {
 163         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 164         struct hw_perf_event *hwc = &event->hw;
 165
 166         /*
 167          * ARM pmu always has to update the counter, so ignore
 168          * PERF_EF_UPDATE, see comments in armpmu_start().
 169          */
 170         if (!(hwc->state & PERF_HES_STOPPED)) {
 171                 armpmu->disable(event);
 172                 armpmu_event_update(event);
 173                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 174         }
 175 }
 176
 177 static void armpmu_start(struct perf_event *event, int flags)
 178 {
 179         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 180         struct hw_perf_event *hwc = &event->hw;
 181
 182         /*
 183          * ARM pmu always has to reprogram the period, so ignore
 184          * PERF_EF_RELOAD, see the comment below.
 185          */
 186         if (flags & PERF_EF_RELOAD)
 187                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 188
 189         hwc->state = 0;
 190         /*
 191          * Set the period again. Some counters can't be stopped, so when we
 192          * were stopped we simply disabled the IRQ source and the counter
 193          * may have been left counting. If we don't do this step then we may
 194          * get an interrupt too soon or *way* too late if the overflow has
 195          * happened since disabling.
 196          */
 197         armpmu_event_set_period(event);
 198         armpmu->enable(event);
 199 }
 200
 201 static void
 202 armpmu_del(struct perf_event *event, int flags)
 203 {
 204         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 205         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 206         struct hw_perf_event *hwc = &event->hw;
 207         int idx = hwc->idx;
 208
 209         armpmu_stop(event, PERF_EF_UPDATE);
 210         hw_events->events[idx] = NULL;
 211         clear_bit(idx, hw_events->used_mask);
 212
 213         perf_event_update_userpage(event);
 214 }
 215
 216 static int
 217 armpmu_add(struct perf_event *event, int flags)
 218 {
 219         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 220         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 221         struct hw_perf_event *hwc = &event->hw;
 222         int idx;
 223         int err = 0;
 224
 225         perf_pmu_disable(event->pmu);
 226
 227         /* If we don't have a space for the counter then finish early. */
 228         idx = armpmu->get_event_idx(hw_events, event);
 229         if (idx < 0) {
 230                 err = idx;
 231                 goto out;
 232         }
 233
 234         /*
 235          * If there is an event in the counter we are going to use then make
 236          * sure it is disabled.
 237          */
 238         event->hw.idx = idx;
 239         armpmu->disable(event);
 240         hw_events->events[idx] = event;
 241
 242         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 243         if (flags & PERF_EF_START)
 244                 armpmu_start(event, PERF_EF_RELOAD);
 245
 246         /* Propagate our changes to the userspace mapping. */
 247         perf_event_update_userpage(event);
 248
 249 out:
 250         perf_pmu_enable(event->pmu);
 251         return err;
 252 }
 253
 254 static int
 255 validate_event(struct pmu_hw_events *hw_events,
 256                struct perf_event *event)
 257 {
 258         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 259
 260         if (is_software_event(event))
 261                 return 1;
 262
 263         if (event->state < PERF_EVENT_STATE_OFF)
 264                 return 1;
 265
 266         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 267                 return 1;
 268
 269         return armpmu->get_event_idx(hw_events, event) >= 0;
 270 }
 271
 272 static int
 273 validate_group(struct perf_event *event)
 274 {
 275         struct perf_event *sibling, *leader = event->group_leader;
 276         struct pmu_hw_events fake_pmu;
 277         DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS);
 278
 279         /*
 280          * Initialise the fake PMU. We only need to populate the
 281          * used_mask for the purposes of validation.
 282          */
 283         memset(fake_used_mask, 0, sizeof(fake_used_mask));
 284         fake_pmu.used_mask = fake_used_mask;
 285
 286         if (!validate_event(&fake_pmu, leader))
 287                 return -EINVAL;
 288
 289         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 290                 if (!validate_event(&fake_pmu, sibling))
 291                         return -EINVAL;
 292         }
 293
 294         if (!validate_event(&fake_pmu, event))
 295                 return -EINVAL;
 296
 297         return 0;
 298 }
 299
 300 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 301 {
 302         struct arm_pmu *armpmu = (struct arm_pmu *) dev;
 303         struct platform_device *plat_device = armpmu->plat_device;
 304         struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
 305
 306         if (plat && plat->handle_irq)
 307                 return plat->handle_irq(irq, dev, armpmu->handle_irq);
 308         else
 309                 return armpmu->handle_irq(irq, dev);
 310 }
 311
 312 static void
 313 armpmu_release_hardware(struct arm_pmu *armpmu)
 314 {
 315         armpmu->free_irq(armpmu);
 316         pm_runtime_put_sync(&armpmu->plat_device->dev);
 317 }
 318
 319 static int
 320 armpmu_reserve_hardware(struct arm_pmu *armpmu)
 321 {
 322         int err;
 323         struct platform_device *pmu_device = armpmu->plat_device;
 324
 325         if (!pmu_device)
 326                 return -ENODEV;
 327
 328         pm_runtime_get_sync(&pmu_device->dev);
 329         err = armpmu->request_irq(armpmu, armpmu_dispatch_irq);
 330         if (err) {
 331                 armpmu_release_hardware(armpmu);
 332                 return err;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static void
 339 hw_perf_event_destroy(struct perf_event *event)
 340 {
 341         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 342         atomic_t *active_events  = &armpmu->active_events;
 343         struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
 344
 345         if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
 346                 armpmu_release_hardware(armpmu);
 347                 mutex_unlock(pmu_reserve_mutex);
 348         }
 349 }
 350
 351 static int
 352 event_requires_mode_exclusion(struct perf_event_attr *attr)
 353 {
 354         return attr->exclude_idle || attr->exclude_user ||
 355                attr->exclude_kernel || attr->exclude_hv;
 356 }
 357
 358 static int
 359 __hw_perf_event_init(struct perf_event *event)
 360 {
 361         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 362         struct hw_perf_event *hwc = &event->hw;
 363         int mapping;
 364
 365         mapping = armpmu->map_event(event);
 366
 367         if (mapping < 0) {
 368                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 369                          event->attr.config);
 370                 return mapping;
 371         }
 372
 373         /*
 374          * We don't assign an index until we actually place the event onto
 375          * hardware. Use -1 to signify that we haven't decided where to put it
 376          * yet. For SMP systems, each core has it's own PMU so we can't do any
 377          * clever allocation or constraints checking at this point.
 378          */
 379         hwc->idx                = -1;
 380         hwc->config_base        = 0;
 381         hwc->config             = 0;
 382         hwc->event_base         = 0;
 383
 384         /*
 385          * Check whether we need to exclude the counter from certain modes.
 386          */
 387         if ((!armpmu->set_event_filter ||
 388              armpmu->set_event_filter(hwc, &event->attr)) &&
 389              event_requires_mode_exclusion(&event->attr)) {
 390                 pr_debug("ARM performance counters do not support "
 391                          "mode exclusion\n");
 392                 return -EOPNOTSUPP;
 393         }
 394
 395         /*
 396          * Store the event encoding into the config_base field.
 397          */
 398         hwc->config_base            |= (unsigned long)mapping;
 399
 400         if (!hwc->sample_period) {
 401                 /*
 402                  * For non-sampling runs, limit the sample_period to half
 403                  * of the counter width. That way, the new counter value
 404                  * is far less likely to overtake the previous one unless
 405                  * you have some serious IRQ latency issues.
 406                  */
 407                 hwc->sample_period  = armpmu->max_period >> 1;
 408                 hwc->last_period    = hwc->sample_period;
 409                 local64_set(&hwc->period_left, hwc->sample_period);
 410         }
 411
 412         if (event->group_leader != event) {
 413                 if (validate_group(event) != 0)
 414                         return -EINVAL;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static int armpmu_event_init(struct perf_event *event)
 421 {
 422         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 423         int err = 0;
 424         atomic_t *active_events = &armpmu->active_events;
 425
 426         /* does not support taken branch sampling */
 427         if (has_branch_stack(event))
 428                 return -EOPNOTSUPP;
 429
 430         if (armpmu->map_event(event) == -ENOENT)
 431                 return -ENOENT;
 432
 433         event->destroy = hw_perf_event_destroy;
 434
 435         if (!atomic_inc_not_zero(active_events)) {
 436                 mutex_lock(&armpmu->reserve_mutex);
 437                 if (atomic_read(active_events) == 0)
 438                         err = armpmu_reserve_hardware(armpmu);
 439
 440                 if (!err)
 441                         atomic_inc(active_events);
 442                 mutex_unlock(&armpmu->reserve_mutex);
 443         }
 444
 445         if (err)
 446                 return err;
 447
 448         err = __hw_perf_event_init(event);
 449         if (err)
 450                 hw_perf_event_destroy(event);
 451
 452         return err;
 453 }
 454
 455 static void armpmu_enable(struct pmu *pmu)
 456 {
 457         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 458         struct pmu_hw_events *hw_events = armpmu->get_hw_events();
 459         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 460
 461         if (enabled)
 462                 armpmu->start(armpmu);
 463 }
 464
 465 static void armpmu_disable(struct pmu *pmu)
 466 {
 467         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 468         armpmu->stop(armpmu);
 469 }
 470
 471 #ifdef CONFIG_PM_RUNTIME
 472 static int armpmu_runtime_resume(struct device *dev)
 473 {
 474         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 475
 476         if (plat && plat->runtime_resume)
 477                 return plat->runtime_resume(dev);
 478
 479         return 0;
 480 }
 481
 482 static int armpmu_runtime_suspend(struct device *dev)
 483 {
 484         struct arm_pmu_platdata *plat = dev_get_platdata(dev);
 485
 486         if (plat && plat->runtime_suspend)
 487                 return plat->runtime_suspend(dev);
 488
 489         return 0;
 490 }
 491 #endif
 492
 493 const struct dev_pm_ops armpmu_dev_pm_ops = {
 494         SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
 495 };
 496
 497 static void armpmu_init(struct arm_pmu *armpmu)
 498 {
 499         atomic_set(&armpmu->active_events, 0);
 500         mutex_init(&armpmu->reserve_mutex);
 501
 502         armpmu->pmu = (struct pmu) {
 503                 .pmu_enable     = armpmu_enable,
 504                 .pmu_disable    = armpmu_disable,
 505                 .event_init     = armpmu_event_init,
 506                 .add            = armpmu_add,
 507                 .del            = armpmu_del,
 508                 .start          = armpmu_start,
 509                 .stop           = armpmu_stop,
 510                 .read           = armpmu_read,
 511         };
 512 }
 513
 514 int armpmu_register(struct arm_pmu *armpmu, int type)
 515 {
 516         armpmu_init(armpmu);
 517         pm_runtime_enable(&armpmu->plat_device->dev);
 518         pr_info("enabled with %s PMU driver, %d counters available\n",
 519                         armpmu->name, armpmu->num_events);
 520         return perf_pmu_register(&armpmu->pmu, armpmu->name, type);
 521 }
 522
 523 /*
 524  * Callchain handling code.
 525  */
 526
 527 /*
 528  * The registers we're interested in are at the end of the variable
 529  * length saved register structure. The fp points at the end of this
 530  * structure so the address of this struct is:
 531  * (struct frame_tail *)(xxx->fp)-1
 532  *
 533  * This code has been adapted from the ARM OProfile support.
 534  */
 535 struct frame_tail {
 536         struct frame_tail __user *fp;
 537         unsigned long sp;
 538         unsigned long lr;
 539 } __attribute__((packed));
 540
 541 /*
 542  * Get the return address for a single stackframe and return a pointer to the
 543  * next frame tail.
 544  */
 545 static struct frame_tail __user *
 546 user_backtrace(struct frame_tail __user *tail,
 547                struct perf_callchain_entry *entry)
 548 {
 549         struct frame_tail buftail;
 550
 551         /* Also check accessibility of one struct frame_tail beyond */
 552         if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
 553                 return NULL;
 554         if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
 555                 return NULL;
 556
 557         perf_callchain_store(entry, buftail.lr);
 558
 559         /*
 560          * Frame pointers should strictly progress back up the stack
 561          * (towards higher addresses).
 562          */
 563         if (tail + 1 >= buftail.fp)
 564                 return NULL;
 565
 566         return buftail.fp - 1;
 567 }
 568
 569 void
 570 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 571 {
 572         struct frame_tail __user *tail;
 573
 574         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 575                 /* We don't support guest os callchain now */
 576                 return;
 577         }
 578
 579         perf_callchain_store(entry, regs->ARM_pc);
 580         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 581
 582         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
 583                tail && !((unsigned long)tail & 0x3))
 584                 tail = user_backtrace(tail, entry);
 585 }
 586
 587 /*
 588  * Gets called by walk_stackframe() for every stackframe. This will be called
 589  * whist unwinding the stackframe and is like a subroutine return so we use
 590  * the PC.
 591  */
 592 static int
 593 callchain_trace(struct stackframe *fr,
 594                 void *data)
 595 {
 596         struct perf_callchain_entry *entry = data;
 597         perf_callchain_store(entry, fr->pc);
 598         return 0;
 599 }
 600
 601 void
 602 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 603 {
 604         struct stackframe fr;
 605
 606         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 607                 /* We don't support guest os callchain now */
 608                 return;
 609         }
 610
 611         fr.fp = regs->ARM_fp;
 612         fr.sp = regs->ARM_sp;
 613         fr.lr = regs->ARM_lr;
 614         fr.pc = regs->ARM_pc;
 615         walk_stackframe(&fr, callchain_trace, entry);
 616 }
 617
 618 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 619 {
 620         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
 621                 return perf_guest_cbs->get_guest_ip();
 622
 623         return instruction_pointer(regs);
 624 }
 625
 626 unsigned long perf_misc_flags(struct pt_regs *regs)
 627 {
 628         int misc = 0;
 629
 630         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
 631                 if (perf_guest_cbs->is_user_mode())
 632                         misc |= PERF_RECORD_MISC_GUEST_USER;
 633                 else
 634                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
 635         } else {
 636                 if (user_mode(regs))
 637                         misc |= PERF_RECORD_MISC_USER;
 638                 else
 639                         misc |= PERF_RECORD_MISC_KERNEL;
 640         }
 641
 642         return misc;
 643 }