arch/arm/mm/nommu.c

   1 /*
   2  *  linux/arch/arm/mm/nommu.c
   3  *
   4  * ARM uCLinux supporting functions.
   5  */
   6 #include <linux/module.h>
   7 #include <linux/mm.h>
   8 #include <linux/pagemap.h>
   9 #include <linux/io.h>
  10 #include <linux/memblock.h>
  11 #include <linux/kernel.h>
  12
  13 #include <asm/cacheflush.h>
  14 #include <asm/sections.h>
  15 #include <asm/page.h>
  16 #include <asm/setup.h>
  17 #include <asm/traps.h>
  18 #include <asm/mach/arch.h>
  19 #include <asm/cputype.h>
  20 #include <asm/mpu.h>
  21 #include <asm/procinfo.h>
  22
  23 #include "mm.h"
  24
  25 #ifdef CONFIG_ARM_MPU
  26 struct mpu_rgn_info mpu_rgn_info;
  27
  28 /* Region number */
  29 static void rgnr_write(u32 v)
  30 {
  31         asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
  32 }
  33
  34 /* Data-side / unified region attributes */
  35
  36 /* Region access control register */
  37 static void dracr_write(u32 v)
  38 {
  39         asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
  40 }
  41
  42 /* Region size register */
  43 static void drsr_write(u32 v)
  44 {
  45         asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
  46 }
  47
  48 /* Region base address register */
  49 static void drbar_write(u32 v)
  50 {
  51         asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
  52 }
  53
  54 static u32 drbar_read(void)
  55 {
  56         u32 v;
  57         asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
  58         return v;
  59 }
  60 /* Optional instruction-side region attributes */
  61
  62 /* I-side Region access control register */
  63 static void iracr_write(u32 v)
  64 {
  65         asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
  66 }
  67
  68 /* I-side Region size register */
  69 static void irsr_write(u32 v)
  70 {
  71         asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
  72 }
  73
  74 /* I-side Region base address register */
  75 static void irbar_write(u32 v)
  76 {
  77         asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
  78 }
  79
  80 static unsigned long irbar_read(void)
  81 {
  82         unsigned long v;
  83         asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
  84         return v;
  85 }
  86
  87 /* MPU initialisation functions */
  88 void __init sanity_check_meminfo_mpu(void)
  89 {
  90         int i;
  91         struct membank *bank = meminfo.bank;
  92         phys_addr_t phys_offset = PHYS_OFFSET;
  93         phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
  94
  95         /* Initially only use memory continuous from PHYS_OFFSET */
  96         if (bank_phys_start(&bank[0]) != phys_offset)
  97                 panic("First memory bank must be contiguous from PHYS_OFFSET");
  98
  99         /* Banks have already been sorted by start address */
 100         for (i = 1; i < meminfo.nr_banks; i++) {
 101                 if (bank[i].start <= bank_phys_end(&bank[0]) &&
 102                     bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
 103                         bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
 104                 } else {
 105                         pr_notice("Ignoring RAM after 0x%.8lx. "
 106                         "First non-contiguous (ignored) bank start: 0x%.8lx\n",
 107                                 (unsigned long)bank_phys_end(&bank[0]),
 108                                 (unsigned long)bank_phys_start(&bank[i]));
 109                         break;
 110                 }
 111         }
 112         /* All contiguous banks are now merged in to the first bank */
 113         meminfo.nr_banks = 1;
 114         specified_mem_size = bank[0].size;
 115
 116         /*
 117          * MPU has curious alignment requirements: Size must be power of 2, and
 118          * region start must be aligned to the region size
 119          */
 120         if (phys_offset != 0)
 121                 pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
 122
 123         /*
 124          * Maximum aligned region might overflow phys_addr_t if phys_offset is
 125          * 0. Hence we keep everything below 4G until we take the smaller of
 126          * the aligned_region_size and rounded_mem_size, one of which is
 127          * guaranteed to be smaller than the maximum physical address.
 128          */
 129         aligned_region_size = (phys_offset - 1) ^ (phys_offset);
 130         /* Find the max power-of-two sized region that fits inside our bank */
 131         rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
 132
 133         /* The actual region size is the smaller of the two */
 134         aligned_region_size = aligned_region_size < rounded_mem_size
 135                                 ? aligned_region_size + 1
 136                                 : rounded_mem_size + 1;
 137
 138         if (aligned_region_size != specified_mem_size)
 139                 pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
 140                                 (unsigned long)specified_mem_size,
 141                                 (unsigned long)aligned_region_size);
 142
 143         meminfo.bank[0].size = aligned_region_size;
 144         pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
 145                 (unsigned long)phys_offset,
 146                 (unsigned long)aligned_region_size,
 147                 (unsigned long)bank_phys_end(&bank[0]));
 148
 149 }
 150
 151 static int mpu_present(void)
 152 {
 153         return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
 154 }
 155
 156 static int mpu_max_regions(void)
 157 {
 158         /*
 159          * We don't support a different number of I/D side regions so if we
 160          * have separate instruction and data memory maps then return
 161          * whichever side has a smaller number of supported regions.
 162          */
 163         u32 dregions, iregions, mpuir;
 164         mpuir = read_cpuid(CPUID_MPUIR);
 165
 166         dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
 167
 168         /* Check for separate d-side and i-side memory maps */
 169         if (mpuir & MPUIR_nU)
 170                 iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
 171
 172         /* Use the smallest of the two maxima */
 173         return min(dregions, iregions);
 174 }
 175
 176 static int mpu_iside_independent(void)
 177 {
 178         /* MPUIR.nU specifies whether there is *not* a unified memory map */
 179         return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
 180 }
 181
 182 static int mpu_min_region_order(void)
 183 {
 184         u32 drbar_result, irbar_result;
 185         /* We've kept a region free for this probing */
 186         rgnr_write(MPU_PROBE_REGION);
 187         isb();
 188         /*
 189          * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
 190          * region order
 191         */
 192         drbar_write(0xFFFFFFFC);
 193         drbar_result = irbar_result = drbar_read();
 194         drbar_write(0x0);
 195         /* If the MPU is non-unified, we use the larger of the two minima*/
 196         if (mpu_iside_independent()) {
 197                 irbar_write(0xFFFFFFFC);
 198                 irbar_result = irbar_read();
 199                 irbar_write(0x0);
 200         }
 201         isb(); /* Ensure that MPU region operations have completed */
 202         /* Return whichever result is larger */
 203         return __ffs(max(drbar_result, irbar_result));
 204 }
 205
 206 static int mpu_setup_region(unsigned int number, phys_addr_t start,
 207                         unsigned int size_order, unsigned int properties)
 208 {
 209         u32 size_data;
 210
 211         /* We kept a region free for probing resolution of MPU regions*/
 212         if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
 213                 return -ENOENT;
 214
 215         if (size_order > 32)
 216                 return -ENOMEM;
 217
 218         if (size_order < mpu_min_region_order())
 219                 return -ENOMEM;
 220
 221         /* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
 222         size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
 223
 224         dsb(); /* Ensure all previous data accesses occur with old mappings */
 225         rgnr_write(number);
 226         isb();
 227         drbar_write(start);
 228         dracr_write(properties);
 229         isb(); /* Propagate properties before enabling region */
 230         drsr_write(size_data);
 231
 232         /* Check for independent I-side registers */
 233         if (mpu_iside_independent()) {
 234                 irbar_write(start);
 235                 iracr_write(properties);
 236                 isb();
 237                 irsr_write(size_data);
 238         }
 239         isb();
 240
 241         /* Store region info (we treat i/d side the same, so only store d) */
 242         mpu_rgn_info.rgns[number].dracr = properties;
 243         mpu_rgn_info.rgns[number].drbar = start;
 244         mpu_rgn_info.rgns[number].drsr = size_data;
 245         return 0;
 246 }
 247
 248 /*
 249 * Set up default MPU regions, doing nothing if there is no MPU
 250 */
 251 void __init mpu_setup(void)
 252 {
 253         int region_err;
 254         if (!mpu_present())
 255                 return;
 256
 257         region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
 258                                         ilog2(meminfo.bank[0].size),
 259                                         MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
 260         if (region_err) {
 261                 panic("MPU region initialization failure! %d", region_err);
 262         } else {
 263                 pr_info("Using ARMv7 PMSA Compliant MPU. "
 264                          "Region independence: %s, Max regions: %d\n",
 265                         mpu_iside_independent() ? "Yes" : "No",
 266                         mpu_max_regions());
 267         }
 268 }
 269 #else
 270 static void sanity_check_meminfo_mpu(void) {}
 271 static void __init mpu_setup(void) {}
 272 #endif /* CONFIG_ARM_MPU */
 273
 274 void __init arm_mm_memblock_reserve(void)
 275 {
 276 #ifndef CONFIG_CPU_V7M
 277         /*
 278          * Register the exception vector page.
 279          * some architectures which the DRAM is the exception vector to trap,
 280          * alloc_page breaks with error, although it is not NULL, but "0."
 281          */
 282         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
 283 #else /* ifndef CONFIG_CPU_V7M */
 284         /*
 285          * There is no dedicated vector page on V7-M. So nothing needs to be
 286          * reserved here.
 287          */
 288 #endif
 289 }
 290
 291 void __init sanity_check_meminfo(void)
 292 {
 293         phys_addr_t end;
 294         sanity_check_meminfo_mpu();
 295         end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
 296         high_memory = __va(end - 1) + 1;
 297 }
 298
 299 /*
 300  * early_paging_init() recreates boot time page table setup, allowing machines
 301  * to switch over to a high (>4G) address space on LPAE systems
 302  */
 303 void __init early_paging_init(const struct machine_desc *mdesc,
 304                               struct proc_info_list *procinfo)
 305 {
 306 }
 307
 308 /*
 309  * paging_init() sets up the page tables, initialises the zone memory
 310  * maps, and sets up the zero page, bad page and bad page tables.
 311  */
 312 void __init paging_init(const struct machine_desc *mdesc)
 313 {
 314         early_trap_init((void *)CONFIG_VECTORS_BASE);
 315         mpu_setup();
 316         bootmem_init();
 317 }
 318
 319 /*
 320  * We don't need to do anything here for nommu machines.
 321  */
 322 void setup_mm_for_reboot(void)
 323 {
 324 }
 325
 326 void flush_dcache_page(struct page *page)
 327 {
 328         __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 329 }
 330 EXPORT_SYMBOL(flush_dcache_page);
 331
 332 void flush_kernel_dcache_page(struct page *page)
 333 {
 334         __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 335 }
 336 EXPORT_SYMBOL(flush_kernel_dcache_page);
 337
 338 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 339                        unsigned long uaddr, void *dst, const void *src,
 340                        unsigned long len)
 341 {
 342         memcpy(dst, src, len);
 343         if (vma->vm_flags & VM_EXEC)
 344                 __cpuc_coherent_user_range(uaddr, uaddr + len);
 345 }
 346
 347 void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
 348                                 size_t size, unsigned int mtype)
 349 {
 350         if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
 351                 return NULL;
 352         return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
 353 }
 354 EXPORT_SYMBOL(__arm_ioremap_pfn);
 355
 356 void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
 357                            size_t size, unsigned int mtype, void *caller)
 358 {
 359         return __arm_ioremap_pfn(pfn, offset, size, mtype);
 360 }
 361
 362 void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
 363                             unsigned int mtype)
 364 {
 365         return (void __iomem *)phys_addr;
 366 }
 367 EXPORT_SYMBOL(__arm_ioremap);
 368
 369 void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 370
 371 void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
 372                                    unsigned int mtype, void *caller)
 373 {
 374         return __arm_ioremap(phys_addr, size, mtype);
 375 }
 376
 377 void (*arch_iounmap)(volatile void __iomem *);
 378
 379 void __arm_iounmap(volatile void __iomem *addr)
 380 {
 381 }
 382 EXPORT_SYMBOL(__arm_iounmap);