drivers/misc/mei/pci-me.c

   1 /*
   2  *
   3  * Intel Management Engine Interface (Intel MEI) Linux driver
   4  * Copyright (c) 2003-2012, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/fs.h>
  21 #include <linux/errno.h>
  22 #include <linux/types.h>
  23 #include <linux/fcntl.h>
  24 #include <linux/pci.h>
  25 #include <linux/poll.h>
  26 #include <linux/ioctl.h>
  27 #include <linux/cdev.h>
  28 #include <linux/sched.h>
  29 #include <linux/uuid.h>
  30 #include <linux/compat.h>
  31 #include <linux/jiffies.h>
  32 #include <linux/interrupt.h>
  33
  34 #include <linux/pm_domain.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <linux/mei.h>
  38
  39 #include "mei_dev.h"
  40 #include "client.h"
  41 #include "hw-me-regs.h"
  42 #include "hw-me.h"
  43
  44 /* mei_pci_tbl - PCI Device ID Table */
  45 static const struct pci_device_id mei_me_pci_tbl[] = {
  46         {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
  47         {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
  48         {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
  49         {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
  50         {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
  51         {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
  52         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
  53         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
  54         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
  55         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
  56         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
  57
  58         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
  59         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
  60         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
  61         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
  62         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
  63         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
  64         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
  65         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
  66         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
  67
  68         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
  69         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
  70         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
  71         {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
  72
  73         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
  74         {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
  75         {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
  76         {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
  77         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
  78         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
  79         {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
  80         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
  81         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
  82         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
  83         {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
  84         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
  85         {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
  86
  87         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
  88         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
  89         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
  90         {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
  91         {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_CFG)},
  92
  93         {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
  94         {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
  95
  96         {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
  97
  98         {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
  99
 100         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
 101         {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
 102
 103         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH8_CFG)},
 104         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_4, MEI_ME_PCH8_CFG)},
 105         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH8_CFG)},
 106         {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_4, MEI_ME_PCH8_CFG)},
 107
 108         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
 109         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_CFG)},
 110         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
 111         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
 112         {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_CFG)},
 113
 114         {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
 115
 116         {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH12_CFG)},
 117
 118         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH12_CFG)},
 119         {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
 120
 121         {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
 122
 123         /* required last entry */
 124         {0, }
 125 };
 126
 127 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
 128
 129 #ifdef CONFIG_PM
 130 static inline void mei_me_set_pm_domain(struct mei_device *dev);
 131 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
 132 #else
 133 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
 134 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
 135 #endif /* CONFIG_PM */
 136
 137 /**
 138  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
 139  *
 140  * @pdev: PCI device structure
 141  * @cfg: per generation config
 142  *
 143  * Return: true if ME Interface is valid, false otherwise
 144  */
 145 static bool mei_me_quirk_probe(struct pci_dev *pdev,
 146                                 const struct mei_cfg *cfg)
 147 {
 148         if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
 149                 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
 150                 return false;
 151         }
 152
 153         return true;
 154 }
 155
 156 /**
 157  * mei_me_probe - Device Initialization Routine
 158  *
 159  * @pdev: PCI device structure
 160  * @ent: entry in kcs_pci_tbl
 161  *
 162  * Return: 0 on success, <0 on failure.
 163  */
 164 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 165 {
 166         const struct mei_cfg *cfg;
 167         struct mei_device *dev;
 168         struct mei_me_hw *hw;
 169         unsigned int irqflags;
 170         int err;
 171
 172         cfg = mei_me_get_cfg(ent->driver_data);
 173         if (!cfg)
 174                 return -ENODEV;
 175
 176         if (!mei_me_quirk_probe(pdev, cfg))
 177                 return -ENODEV;
 178
 179         /* enable pci dev */
 180         err = pcim_enable_device(pdev);
 181         if (err) {
 182                 dev_err(&pdev->dev, "failed to enable pci device.\n");
 183                 goto end;
 184         }
 185         /* set PCI host mastering  */
 186         pci_set_master(pdev);
 187         /* pci request regions and mapping IO device memory for mei driver */
 188         err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
 189         if (err) {
 190                 dev_err(&pdev->dev, "failed to get pci regions.\n");
 191                 goto end;
 192         }
 193
 194         if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
 195             dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
 196
 197                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
 198                 if (err)
 199                         err = dma_set_coherent_mask(&pdev->dev,
 200                                                     DMA_BIT_MASK(32));
 201         }
 202         if (err) {
 203                 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
 204                 goto end;
 205         }
 206
 207         /* allocates and initializes the mei dev structure */
 208         dev = mei_me_dev_init(pdev, cfg);
 209         if (!dev) {
 210                 err = -ENOMEM;
 211                 goto end;
 212         }
 213         hw = to_me_hw(dev);
 214         hw->mem_addr = pcim_iomap_table(pdev)[0];
 215
 216         pci_enable_msi(pdev);
 217
 218          /* request and enable interrupt */
 219         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 220
 221         err = request_threaded_irq(pdev->irq,
 222                         mei_me_irq_quick_handler,
 223                         mei_me_irq_thread_handler,
 224                         irqflags, KBUILD_MODNAME, dev);
 225         if (err) {
 226                 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
 227                        pdev->irq);
 228                 goto end;
 229         }
 230
 231         if (mei_start(dev)) {
 232                 dev_err(&pdev->dev, "init hw failure.\n");
 233                 err = -ENODEV;
 234                 goto release_irq;
 235         }
 236
 237         pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
 238         pm_runtime_use_autosuspend(&pdev->dev);
 239
 240         err = mei_register(dev, &pdev->dev);
 241         if (err)
 242                 goto stop;
 243
 244         pci_set_drvdata(pdev, dev);
 245
 246         /*
 247          * MEI requires to resume from runtime suspend mode
 248          * in order to perform link reset flow upon system suspend.
 249          */
 250         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
 251
 252         /*
 253          * ME maps runtime suspend/resume to D0i states,
 254          * hence we need to go around native PCI runtime service which
 255          * eventually brings the device into D3cold/hot state,
 256          * but the mei device cannot wake up from D3 unlike from D0i3.
 257          * To get around the PCI device native runtime pm,
 258          * ME uses runtime pm domain handlers which take precedence
 259          * over the driver's pm handlers.
 260          */
 261         mei_me_set_pm_domain(dev);
 262
 263         if (mei_pg_is_enabled(dev)) {
 264                 pm_runtime_put_noidle(&pdev->dev);
 265                 if (hw->d0i3_supported)
 266                         pm_runtime_allow(&pdev->dev);
 267         }
 268
 269         dev_dbg(&pdev->dev, "initialization successful.\n");
 270
 271         return 0;
 272
 273 stop:
 274         mei_stop(dev);
 275 release_irq:
 276         mei_cancel_work(dev);
 277         mei_disable_interrupts(dev);
 278         free_irq(pdev->irq, dev);
 279 end:
 280         dev_err(&pdev->dev, "initialization failed.\n");
 281         return err;
 282 }
 283
 284 /**
 285  * mei_me_shutdown - Device Removal Routine
 286  *
 287  * @pdev: PCI device structure
 288  *
 289  * mei_me_shutdown is called from the reboot notifier
 290  * it's a simplified version of remove so we go down
 291  * faster.
 292  */
 293 static void mei_me_shutdown(struct pci_dev *pdev)
 294 {
 295         struct mei_device *dev;
 296
 297         dev = pci_get_drvdata(pdev);
 298         if (!dev)
 299                 return;
 300
 301         dev_dbg(&pdev->dev, "shutdown\n");
 302         mei_stop(dev);
 303
 304         mei_me_unset_pm_domain(dev);
 305
 306         mei_disable_interrupts(dev);
 307         free_irq(pdev->irq, dev);
 308 }
 309
 310 /**
 311  * mei_me_remove - Device Removal Routine
 312  *
 313  * @pdev: PCI device structure
 314  *
 315  * mei_me_remove is called by the PCI subsystem to alert the driver
 316  * that it should release a PCI device.
 317  */
 318 static void mei_me_remove(struct pci_dev *pdev)
 319 {
 320         struct mei_device *dev;
 321
 322         dev = pci_get_drvdata(pdev);
 323         if (!dev)
 324                 return;
 325
 326         if (mei_pg_is_enabled(dev))
 327                 pm_runtime_get_noresume(&pdev->dev);
 328
 329         dev_dbg(&pdev->dev, "stop\n");
 330         mei_stop(dev);
 331
 332         mei_me_unset_pm_domain(dev);
 333
 334         mei_disable_interrupts(dev);
 335
 336         free_irq(pdev->irq, dev);
 337
 338         mei_deregister(dev);
 339 }
 340
 341 #ifdef CONFIG_PM_SLEEP
 342 static int mei_me_pci_suspend(struct device *device)
 343 {
 344         struct pci_dev *pdev = to_pci_dev(device);
 345         struct mei_device *dev = pci_get_drvdata(pdev);
 346
 347         if (!dev)
 348                 return -ENODEV;
 349
 350         dev_dbg(&pdev->dev, "suspend\n");
 351
 352         mei_stop(dev);
 353
 354         mei_disable_interrupts(dev);
 355
 356         free_irq(pdev->irq, dev);
 357         pci_disable_msi(pdev);
 358
 359         return 0;
 360 }
 361
 362 static int mei_me_pci_resume(struct device *device)
 363 {
 364         struct pci_dev *pdev = to_pci_dev(device);
 365         struct mei_device *dev;
 366         unsigned int irqflags;
 367         int err;
 368
 369         dev = pci_get_drvdata(pdev);
 370         if (!dev)
 371                 return -ENODEV;
 372
 373         pci_enable_msi(pdev);
 374
 375         irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
 376
 377         /* request and enable interrupt */
 378         err = request_threaded_irq(pdev->irq,
 379                         mei_me_irq_quick_handler,
 380                         mei_me_irq_thread_handler,
 381                         irqflags, KBUILD_MODNAME, dev);
 382
 383         if (err) {
 384                 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
 385                                 pdev->irq);
 386                 return err;
 387         }
 388
 389         err = mei_restart(dev);
 390         if (err)
 391                 return err;
 392
 393         /* Start timer if stopped in suspend */
 394         schedule_delayed_work(&dev->timer_work, HZ);
 395
 396         return 0;
 397 }
 398 #endif /* CONFIG_PM_SLEEP */
 399
 400 #ifdef CONFIG_PM
 401 static int mei_me_pm_runtime_idle(struct device *device)
 402 {
 403         struct pci_dev *pdev = to_pci_dev(device);
 404         struct mei_device *dev;
 405
 406         dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
 407
 408         dev = pci_get_drvdata(pdev);
 409         if (!dev)
 410                 return -ENODEV;
 411         if (mei_write_is_idle(dev))
 412                 pm_runtime_autosuspend(device);
 413
 414         return -EBUSY;
 415 }
 416
 417 static int mei_me_pm_runtime_suspend(struct device *device)
 418 {
 419         struct pci_dev *pdev = to_pci_dev(device);
 420         struct mei_device *dev;
 421         int ret;
 422
 423         dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
 424
 425         dev = pci_get_drvdata(pdev);
 426         if (!dev)
 427                 return -ENODEV;
 428
 429         mutex_lock(&dev->device_lock);
 430
 431         if (mei_write_is_idle(dev))
 432                 ret = mei_me_pg_enter_sync(dev);
 433         else
 434                 ret = -EAGAIN;
 435
 436         mutex_unlock(&dev->device_lock);
 437
 438         dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
 439
 440         if (ret && ret != -EAGAIN)
 441                 schedule_work(&dev->reset_work);
 442
 443         return ret;
 444 }
 445
 446 static int mei_me_pm_runtime_resume(struct device *device)
 447 {
 448         struct pci_dev *pdev = to_pci_dev(device);
 449         struct mei_device *dev;
 450         int ret;
 451
 452         dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
 453
 454         dev = pci_get_drvdata(pdev);
 455         if (!dev)
 456                 return -ENODEV;
 457
 458         mutex_lock(&dev->device_lock);
 459
 460         ret = mei_me_pg_exit_sync(dev);
 461
 462         mutex_unlock(&dev->device_lock);
 463
 464         dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
 465
 466         if (ret)
 467                 schedule_work(&dev->reset_work);
 468
 469         return ret;
 470 }
 471
 472 /**
 473  * mei_me_set_pm_domain - fill and set pm domain structure for device
 474  *
 475  * @dev: mei_device
 476  */
 477 static inline void mei_me_set_pm_domain(struct mei_device *dev)
 478 {
 479         struct pci_dev *pdev  = to_pci_dev(dev->dev);
 480
 481         if (pdev->dev.bus && pdev->dev.bus->pm) {
 482                 dev->pg_domain.ops = *pdev->dev.bus->pm;
 483
 484                 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
 485                 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
 486                 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
 487
 488                 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
 489         }
 490 }
 491
 492 /**
 493  * mei_me_unset_pm_domain - clean pm domain structure for device
 494  *
 495  * @dev: mei_device
 496  */
 497 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
 498 {
 499         /* stop using pm callbacks if any */
 500         dev_pm_domain_set(dev->dev, NULL);
 501 }
 502
 503 static const struct dev_pm_ops mei_me_pm_ops = {
 504         SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
 505                                 mei_me_pci_resume)
 506         SET_RUNTIME_PM_OPS(
 507                 mei_me_pm_runtime_suspend,
 508                 mei_me_pm_runtime_resume,
 509                 mei_me_pm_runtime_idle)
 510 };
 511
 512 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
 513 #else
 514 #define MEI_ME_PM_OPS   NULL
 515 #endif /* CONFIG_PM */
 516 /*
 517  *  PCI driver structure
 518  */
 519 static struct pci_driver mei_me_driver = {
 520         .name = KBUILD_MODNAME,
 521         .id_table = mei_me_pci_tbl,
 522         .probe = mei_me_probe,
 523         .remove = mei_me_remove,
 524         .shutdown = mei_me_shutdown,
 525         .driver.pm = MEI_ME_PM_OPS,
 526         .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 527 };
 528
 529 module_pci_driver(mei_me_driver);
 530
 531 MODULE_AUTHOR("Intel Corporation");
 532 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
 533 MODULE_LICENSE("GPL v2");