drivers/irqchip/irq-gic-common.c

   1 /*
   2  * Copyright (C) 2002 ARM Limited, All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/irq.h>
  20 #include <linux/irqchip/arm-gic.h>
  21
  22 #include "irq-gic-common.h"
  23
  24 void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
  25                 void *data)
  26 {
  27         for (; quirks->desc; quirks++) {
  28                 if (quirks->iidr != (quirks->mask & iidr))
  29                         continue;
  30                 quirks->init(data);
  31                 pr_info("GIC: enabling workaround for %s\n", quirks->desc);
  32         }
  33 }
  34
  35 int gic_configure_irq(unsigned int irq, unsigned int type,
  36                        void __iomem *base, void (*sync_access)(void))
  37 {
  38         u32 confmask = 0x2 << ((irq % 16) * 2);
  39         u32 confoff = (irq / 16) * 4;
  40         u32 val, oldval;
  41         int ret = 0;
  42
  43         /*
  44          * Read current configuration register, and insert the config
  45          * for "irq", depending on "type".
  46          */
  47         val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
  48         if (type & IRQ_TYPE_LEVEL_MASK)
  49                 val &= ~confmask;
  50         else if (type & IRQ_TYPE_EDGE_BOTH)
  51                 val |= confmask;
  52
  53         /*
  54          * Write back the new configuration, and possibly re-enable
  55          * the interrupt. If we tried to write a new configuration and failed,
  56          * return an error.
  57          */
  58         writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
  59         if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval)
  60                 ret = -EINVAL;
  61
  62         if (sync_access)
  63                 sync_access();
  64
  65         return ret;
  66 }
  67
  68 void __init gic_dist_config(void __iomem *base, int gic_irqs,
  69                             void (*sync_access)(void))
  70 {
  71         unsigned int i;
  72
  73         /*
  74          * Set all global interrupts to be level triggered, active low.
  75          */
  76         for (i = 32; i < gic_irqs; i += 16)
  77                 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
  78                                         base + GIC_DIST_CONFIG + i / 4);
  79
  80         /*
  81          * Set priority on all global interrupts.
  82          */
  83         for (i = 32; i < gic_irqs; i += 4)
  84                 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
  85
  86         /*
  87          * Deactivate and disable all SPIs. Leave the PPI and SGIs
  88          * alone as they are in the redistributor registers on GICv3.
  89          */
  90         for (i = 32; i < gic_irqs; i += 32) {
  91                 writel_relaxed(GICD_INT_EN_CLR_X32,
  92                                base + GIC_DIST_ACTIVE_CLEAR + i / 8);
  93                 writel_relaxed(GICD_INT_EN_CLR_X32,
  94                                base + GIC_DIST_ENABLE_CLEAR + i / 8);
  95         }
  96
  97         if (sync_access)
  98                 sync_access();
  99 }
 100
 101 void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
 102 {
 103         int i;
 104
 105         /*
 106          * Deal with the banked PPI and SGI interrupts - disable all
 107          * PPI interrupts, ensure all SGI interrupts are enabled.
 108          * Make sure everything is deactivated.
 109          */
 110         writel_relaxed(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
 111         writel_relaxed(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
 112         writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
 113
 114         /*
 115          * Set priority on PPI and SGI interrupts
 116          */
 117         for (i = 0; i < 32; i += 4)
 118                 writel_relaxed(GICD_INT_DEF_PRI_X4,
 119                                         base + GIC_DIST_PRI + i * 4 / 4);
 120
 121         if (sync_access)
 122                 sync_access();
 123 }