arch/mips/dec/ecc-berr.c

   1 /*
   2  *      Bus error event handling code for systems equipped with ECC
   3  *      handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
   4  *      5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
   5  *      5900/260 (KN05) systems.
   6  *
   7  *      Copyright (c) 2003, 2005  Maciej W. Rozycki
   8  *
   9  *      This program is free software; you can redistribute it and/or
  10  *      modify it under the terms of the GNU General Public License
  11  *      as published by the Free Software Foundation; either version
  12  *      2 of the License, or (at your option) any later version.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/types.h>
  20
  21 #include <asm/addrspace.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/irq_regs.h>
  26 #include <asm/processor.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/traps.h>
  29
  30 #include <asm/dec/ecc.h>
  31 #include <asm/dec/kn02.h>
  32 #include <asm/dec/kn03.h>
  33 #include <asm/dec/kn05.h>
  34
  35 static volatile u32 *kn0x_erraddr;
  36 static volatile u32 *kn0x_chksyn;
  37
  38 static inline void dec_ecc_be_ack(void)
  39 {
  40         *kn0x_erraddr = 0;                      /* any write clears the IRQ */
  41         iob();
  42 }
  43
  44 static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
  45 {
  46         static const char excstr[] = "exception";
  47         static const char intstr[] = "interrupt";
  48         static const char cpustr[] = "CPU";
  49         static const char dmastr[] = "DMA";
  50         static const char readstr[] = "read";
  51         static const char mreadstr[] = "memory read";
  52         static const char writestr[] = "write";
  53         static const char mwritstr[] = "partial memory write";
  54         static const char timestr[] = "timeout";
  55         static const char overstr[] = "overrun";
  56         static const char eccstr[] = "ECC error";
  57
  58         const char *kind, *agent, *cycle, *event;
  59         const char *status = "", *xbit = "", *fmt = "";
  60         unsigned long address;
  61         u16 syn = 0, sngl;
  62
  63         int i = 0;
  64
  65         u32 erraddr = *kn0x_erraddr;
  66         u32 chksyn = *kn0x_chksyn;
  67         int action = MIPS_BE_FATAL;
  68
  69         /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
  70         if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
  71                 dec_ecc_be_ack();
  72
  73         kind = invoker ? intstr : excstr;
  74
  75         if (!(erraddr & KN0X_EAR_VALID)) {
  76                 /* No idea what happened. */
  77                 printk(KERN_ALERT "Unidentified bus error %s\n", kind);
  78                 return action;
  79         }
  80
  81         agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;
  82
  83         if (erraddr & KN0X_EAR_ECCERR) {
  84                 /* An ECC error on a CPU or DMA transaction. */
  85                 cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
  86                 event = eccstr;
  87         } else {
  88                 /* A CPU timeout or a DMA overrun. */
  89                 cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
  90                 event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
  91         }
  92
  93         address = erraddr & KN0X_EAR_ADDRESS;
  94         /* For ECC errors on reads adjust for MT pipelining. */
  95         if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
  96                 address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL);
  97         address <<= 2;
  98
  99         /* Only CPU errors are fixable. */
 100         if (erraddr & KN0X_EAR_CPU && is_fixup)
 101                 action = MIPS_BE_FIXUP;
 102
 103         if (erraddr & KN0X_EAR_ECCERR) {
 104                 static const u8 data_sbit[32] = {
 105                         0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
 106                         0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
 107                         0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
 108                         0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
 109                 };
 110                 static const u8 data_mbit[25] = {
 111                         0x07, 0x0d, 0x1f,
 112                         0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
 113                         0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
 114                         0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
 115                 };
 116                 static const char sbestr[] = "corrected single";
 117                 static const char dbestr[] = "uncorrectable double";
 118                 static const char mbestr[] = "uncorrectable multiple";
 119
 120                 if (!(address & 0x4))
 121                         syn = chksyn;                   /* Low bank. */
 122                 else
 123                         syn = chksyn >> 16;             /* High bank. */
 124
 125                 if (!(syn & KN0X_ESR_VLDLO)) {
 126                         /* Ack now, no rewrite will happen. */
 127                         dec_ecc_be_ack();
 128
 129                         fmt = KERN_ALERT "%s" "invalid\n";
 130                 } else {
 131                         sngl = syn & KN0X_ESR_SNGLO;
 132                         syn &= KN0X_ESR_SYNLO;
 133
 134                         /*
 135                          * Multibit errors may be tagged incorrectly;
 136                          * check the syndrome explicitly.
 137                          */
 138                         for (i = 0; i < 25; i++)
 139                                 if (syn == data_mbit[i])
 140                                         break;
 141
 142                         if (i < 25) {
 143                                 status = mbestr;
 144                         } else if (!sngl) {
 145                                 status = dbestr;
 146                         } else {
 147                                 volatile u32 *ptr =
 148                                         (void *)CKSEG1ADDR(address);
 149
 150                                 *ptr = *ptr;            /* Rewrite. */
 151                                 iob();
 152
 153                                 status = sbestr;
 154                                 action = MIPS_BE_DISCARD;
 155                         }
 156
 157                         /* Ack now, now we've rewritten (or not). */
 158                         dec_ecc_be_ack();
 159
 160                         if (syn && syn == (syn & -syn)) {
 161                                 if (syn == 0x01) {
 162                                         fmt = KERN_ALERT "%s"
 163                                               "%#04x -- %s bit error "
 164                                               "at check bit C%s\n";
 165                                         xbit = "X";
 166                                 } else {
 167                                         fmt = KERN_ALERT "%s"
 168                                               "%#04x -- %s bit error "
 169                                               "at check bit C%s%u\n";
 170                                 }
 171                                 i = syn >> 2;
 172                         } else {
 173                                 for (i = 0; i < 32; i++)
 174                                         if (syn == data_sbit[i])
 175                                                 break;
 176                                 if (i < 32)
 177                                         fmt = KERN_ALERT "%s"
 178                                               "%#04x -- %s bit error "
 179                                               "at data bit D%s%u\n";
 180                                 else
 181                                         fmt = KERN_ALERT "%s"
 182                                               "%#04x -- %s bit error\n";
 183                         }
 184                 }
 185         }
 186
 187         if (action != MIPS_BE_FIXUP)
 188                 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
 189                         kind, agent, cycle, event, address);
 190
 191         if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
 192                 printk(fmt, "  ECC syndrome ", syn, status, xbit, i);
 193
 194         return action;
 195 }
 196
 197 int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
 198 {
 199         return dec_ecc_be_backend(regs, is_fixup, 0);
 200 }
 201
 202 irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
 203 {
 204         struct pt_regs *regs = get_irq_regs();
 205
 206         int action = dec_ecc_be_backend(regs, 0, 1);
 207
 208         if (action == MIPS_BE_DISCARD)
 209                 return IRQ_HANDLED;
 210
 211         /*
 212          * FIXME: Find the affected processes and kill them, otherwise
 213          * we must die.
 214          *
 215          * The interrupt is asynchronously delivered thus EPC and RA
 216          * may be irrelevant, but are printed for a reference.
 217          */
 218         printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
 219                regs->cp0_epc, regs->regs[31]);
 220         die("Unrecoverable bus error", regs);
 221 }
 222
 223
 224 /*
 225  * Initialization differs a bit between KN02 and KN03/KN05, so we
 226  * need two variants.  Once set up, all systems can be handled the
 227  * same way.
 228  */
 229 static inline void dec_kn02_be_init(void)
 230 {
 231         volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
 232
 233         kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
 234         kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
 235
 236         /* Preset write-only bits of the Control Register cache. */
 237         cached_kn02_csr = *csr | KN02_CSR_LEDS;
 238
 239         /* Set normal ECC detection and generation. */
 240         cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
 241         /* Enable ECC correction. */
 242         cached_kn02_csr |= KN02_CSR_CORRECT;
 243         *csr = cached_kn02_csr;
 244         iob();
 245 }
 246
 247 static inline void dec_kn03_be_init(void)
 248 {
 249         volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
 250         volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 251
 252         kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
 253         kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
 254
 255         /*
 256          * Set normal ECC detection and generation, enable ECC correction.
 257          * For KN05 we also need to make sure EE (?) is enabled in the MB.
 258          * Otherwise DBE/IBE exceptions would be masked but bus error
 259          * interrupts would still arrive, resulting in an inevitable crash
 260          * if get_dbe() triggers one.
 261          */
 262         *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
 263                KN03_MCR_CORRECT;
 264         if (current_cpu_type() == CPU_R4400SC)
 265                 *mbcs |= KN4K_MB_CSR_EE;
 266         fast_iob();
 267 }
 268
 269 void __init dec_ecc_be_init(void)
 270 {
 271         if (mips_machtype == MACH_DS5000_200)
 272                 dec_kn02_be_init();
 273         else
 274                 dec_kn03_be_init();
 275
 276         /* Clear any leftover errors from the firmware. */
 277         dec_ecc_be_ack();
 278 }