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powercap: restrict energy meter to root access
[linux/fpc-iii.git] / drivers / dma / pxa_dma.c
blob3f56f9ca44824d90d67c47ce78841d223a963ba3
1 /*
2 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9 #include <linux/err.h>
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/types.h>
13 #include <linux/interrupt.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/slab.h>
16 #include <linux/dmaengine.h>
17 #include <linux/platform_device.h>
18 #include <linux/device.h>
19 #include <linux/platform_data/mmp_dma.h>
20 #include <linux/dmapool.h>
21 #include <linux/of_device.h>
22 #include <linux/of_dma.h>
23 #include <linux/of.h>
24 #include <linux/wait.h>
25 #include <linux/dma/pxa-dma.h>
26
27 #include "dmaengine.h"
28 #include "virt-dma.h"
29
30 #define DCSR(n) (0x0000 + ((n) << 2))
31 #define DALGN(n) 0x00a0
32 #define DINT 0x00f0
33 #define DDADR(n) (0x0200 + ((n) << 4))
34 #define DSADR(n) (0x0204 + ((n) << 4))
35 #define DTADR(n) (0x0208 + ((n) << 4))
36 #define DCMD(n) (0x020c + ((n) << 4))
37
38 #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */
39 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */
40 #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */
41 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */
42 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */
43 #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */
44 #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */
45 #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */
46
47 #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */
48 #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */
49 #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */
50 #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */
51 #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */
52 #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */
53 #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */
54
55 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */
56 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
57
58 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
59 #define DDADR_STOP BIT(0) /* Stop (read / write) */
60
61 #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */
62 #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */
63 #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */
64 #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */
65 #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */
66 #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */
67 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */
68 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */
69 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */
70 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */
71 #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */
72 #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
73 #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
74 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
75
76 #define PDMA_ALIGNMENT 3
77 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
78
79 struct pxad_desc_hw {
80 u32 ddadr; /* Points to the next descriptor + flags */
81 u32 dsadr; /* DSADR value for the current transfer */
82 u32 dtadr; /* DTADR value for the current transfer */
83 u32 dcmd; /* DCMD value for the current transfer */
84 } __aligned(16);
85
86 struct pxad_desc_sw {
87 struct virt_dma_desc vd; /* Virtual descriptor */
88 int nb_desc; /* Number of hw. descriptors */
89 size_t len; /* Number of bytes xfered */
90 dma_addr_t first; /* First descriptor's addr */
91
92 /* At least one descriptor has an src/dst address not multiple of 8 */
93 bool misaligned;
94 bool cyclic;
95 struct dma_pool *desc_pool; /* Channel's used allocator */
96
97 struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */
98 };
99
100 struct pxad_phy {
101 int idx;
102 void __iomem *base;
103 struct pxad_chan *vchan;
104 };
105
106 struct pxad_chan {
107 struct virt_dma_chan vc; /* Virtual channel */
108 u32 drcmr; /* Requestor of the channel */
109 enum pxad_chan_prio prio; /* Required priority of phy */
110 /*
111 * At least one desc_sw in submitted or issued transfers on this channel
112 * has one address such as: addr % 8 != 0. This implies the DALGN
113 * setting on the phy.
114 */
115 bool misaligned;
116 struct dma_slave_config cfg; /* Runtime config */
117
118 /* protected by vc->lock */
119 struct pxad_phy *phy;
120 struct dma_pool *desc_pool; /* Descriptors pool */
121 dma_cookie_t bus_error;
122
123 wait_queue_head_t wq_state;
124 };
125
126 struct pxad_device {
127 struct dma_device slave;
128 int nr_chans;
129 int nr_requestors;
130 void __iomem *base;
131 struct pxad_phy *phys;
132 spinlock_t phy_lock; /* Phy association */
133 #ifdef CONFIG_DEBUG_FS
134 struct dentry *dbgfs_root;
135 struct dentry *dbgfs_state;
136 struct dentry **dbgfs_chan;
137 #endif
138 };
139
140 #define tx_to_pxad_desc(tx) \
141 container_of(tx, struct pxad_desc_sw, async_tx)
142 #define to_pxad_chan(dchan) \
143 container_of(dchan, struct pxad_chan, vc.chan)
144 #define to_pxad_dev(dmadev) \
145 container_of(dmadev, struct pxad_device, slave)
146 #define to_pxad_sw_desc(_vd) \
147 container_of((_vd), struct pxad_desc_sw, vd)
148
149 #define _phy_readl_relaxed(phy, _reg) \
150 readl_relaxed((phy)->base + _reg((phy)->idx))
151 #define phy_readl_relaxed(phy, _reg) \
152 ({ \
153 u32 _v; \
154 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \
155 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
156 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \
157 _v); \
158 _v; \
159 })
160 #define phy_writel(phy, val, _reg) \
161 do { \
162 writel((val), (phy)->base + _reg((phy)->idx)); \
163 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
164 "%s(): writel(0x%08x, %s)\n", \
165 __func__, (u32)(val), #_reg); \
166 } while (0)
167 #define phy_writel_relaxed(phy, val, _reg) \
168 do { \
169 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \
170 dev_vdbg(&phy->vchan->vc.chan.dev->device, \
171 "%s(): writel_relaxed(0x%08x, %s)\n", \
172 __func__, (u32)(val), #_reg); \
173 } while (0)
174
175 static unsigned int pxad_drcmr(unsigned int line)
176 {
177 if (line < 64)
178 return 0x100 + line * 4;
179 return 0x1000 + line * 4;
180 }
181
182 /*
183 * Debug fs
184 */
185 #ifdef CONFIG_DEBUG_FS
186 #include <linux/debugfs.h>
187 #include <linux/uaccess.h>
188 #include <linux/seq_file.h>
189
190 static int dbg_show_requester_chan(struct seq_file *s, void *p)
191 {
192 struct pxad_phy *phy = s->private;
193 int i;
194 u32 drcmr;
195
196 seq_printf(s, "DMA channel %d requester :\n", phy->idx);
197 for (i = 0; i < 70; i++) {
198 drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
199 if ((drcmr & DRCMR_CHLNUM) == phy->idx)
200 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
201 !!(drcmr & DRCMR_MAPVLD));
202 }
203 return 0;
204 }
205
206 static inline int dbg_burst_from_dcmd(u32 dcmd)
207 {
208 int burst = (dcmd >> 16) & 0x3;
209
210 return burst ? 4 << burst : 0;
211 }
212
213 static int is_phys_valid(unsigned long addr)
214 {
215 return pfn_valid(__phys_to_pfn(addr));
216 }
217
218 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
219 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")
220
221 static int dbg_show_descriptors(struct seq_file *s, void *p)
222 {
223 struct pxad_phy *phy = s->private;
224 int i, max_show = 20, burst, width;
225 u32 dcmd;
226 unsigned long phys_desc, ddadr;
227 struct pxad_desc_hw *desc;
228
229 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);
230
231 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
232 seq_printf(s, "[%03d] First descriptor unknown\n", 0);
233 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
234 desc = phys_to_virt(phys_desc);
235 dcmd = desc->dcmd;
236 burst = dbg_burst_from_dcmd(dcmd);
237 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
238
239 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
240 i, phys_desc, desc);
241 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
242 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
243 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
244 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
245 dcmd,
246 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
247 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
248 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
249 PXA_DCMD_STR(ENDIAN), burst, width,
250 dcmd & PXA_DCMD_LENGTH);
251 phys_desc = desc->ddadr;
252 }
253 if (i == max_show)
254 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
255 i, phys_desc);
256 else
257 seq_printf(s, "[%03d] Desc at %08lx is %s\n",
258 i, phys_desc, phys_desc == DDADR_STOP ?
259 "DDADR_STOP" : "invalid");
260
261 return 0;
262 }
263
264 static int dbg_show_chan_state(struct seq_file *s, void *p)
265 {
266 struct pxad_phy *phy = s->private;
267 u32 dcsr, dcmd;
268 int burst, width;
269 static const char * const str_prio[] = {
270 "high", "normal", "low", "invalid"
271 };
272
273 dcsr = _phy_readl_relaxed(phy, DCSR);
274 dcmd = _phy_readl_relaxed(phy, DCMD);
275 burst = dbg_burst_from_dcmd(dcmd);
276 width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
277
278 seq_printf(s, "DMA channel %d\n", phy->idx);
279 seq_printf(s, "\tPriority : %s\n",
280 str_prio[(phy->idx & 0xf) / 4]);
281 seq_printf(s, "\tUnaligned transfer bit: %s\n",
282 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
283 "yes" : "no");
284 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
285 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
286 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
287 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
288 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
289 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
290 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
291 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
292 PXA_DCSR_STR(BUSERR));
293
294 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
295 dcmd,
296 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
297 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
298 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
299 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
300 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
301 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
302 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));
303
304 return 0;
305 }
306
307 static int dbg_show_state(struct seq_file *s, void *p)
308 {
309 struct pxad_device *pdev = s->private;
310
311 /* basic device status */
312 seq_puts(s, "DMA engine status\n");
313 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);
314
315 return 0;
316 }
317
318 #define DBGFS_FUNC_DECL(name) \
319 static int dbg_open_##name(struct inode *inode, struct file *file) \
320 { \
321 return single_open(file, dbg_show_##name, inode->i_private); \
322 } \
323 static const struct file_operations dbg_fops_##name = { \
324 .open = dbg_open_##name, \
325 .llseek = seq_lseek, \
326 .read = seq_read, \
327 .release = single_release, \
328 }
329
330 DBGFS_FUNC_DECL(state);
331 DBGFS_FUNC_DECL(chan_state);
332 DBGFS_FUNC_DECL(descriptors);
333 DBGFS_FUNC_DECL(requester_chan);
334
335 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,
336 int ch, struct dentry *chandir)
337 {
338 char chan_name[11];
339 struct dentry *chan, *chan_state = NULL, *chan_descr = NULL;
340 struct dentry *chan_reqs = NULL;
341 void *dt;
342
343 scnprintf(chan_name, sizeof(chan_name), "%d", ch);
344 chan = debugfs_create_dir(chan_name, chandir);
345 dt = (void *)&pdev->phys[ch];
346
347 if (chan)
348 chan_state = debugfs_create_file("state", 0400, chan, dt,
349 &dbg_fops_chan_state);
350 if (chan_state)
351 chan_descr = debugfs_create_file("descriptors", 0400, chan, dt,
352 &dbg_fops_descriptors);
353 if (chan_descr)
354 chan_reqs = debugfs_create_file("requesters", 0400, chan, dt,
355 &dbg_fops_requester_chan);
356 if (!chan_reqs)
357 goto err_state;
358
359 return chan;
360
361 err_state:
362 debugfs_remove_recursive(chan);
363 return NULL;
364 }
365
366 static void pxad_init_debugfs(struct pxad_device *pdev)
367 {
368 int i;
369 struct dentry *chandir;
370
371 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
372 if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root)
373 goto err_root;
374
375 pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root,
376 pdev, &dbg_fops_state);
377 if (!pdev->dbgfs_state)
378 goto err_state;
379
380 pdev->dbgfs_chan =
381 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state),
382 GFP_KERNEL);
383 if (!pdev->dbgfs_chan)
384 goto err_alloc;
385
386 chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
387 if (!chandir)
388 goto err_chandir;
389
390 for (i = 0; i < pdev->nr_chans; i++) {
391 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
392 if (!pdev->dbgfs_chan[i])
393 goto err_chans;
394 }
395
396 return;
397 err_chans:
398 err_chandir:
399 kfree(pdev->dbgfs_chan);
400 err_alloc:
401 err_state:
402 debugfs_remove_recursive(pdev->dbgfs_root);
403 err_root:
404 pr_err("pxad: debugfs is not available\n");
405 }
406
407 static void pxad_cleanup_debugfs(struct pxad_device *pdev)
408 {
409 debugfs_remove_recursive(pdev->dbgfs_root);
410 }
411 #else
412 static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
413 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
414 #endif
415
416 /*
417 * In the transition phase where legacy pxa handling is done at the same time as
418 * mmp_dma, the DMA physical channel split between the 2 DMA providers is done
419 * through legacy_reserved. Legacy code reserves DMA channels by settings
420 * corresponding bits in legacy_reserved.
421 */
422 static u32 legacy_reserved;
423 static u32 legacy_unavailable;
424
425 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)
426 {
427 int prio, i;
428 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);
429 struct pxad_phy *phy, *found = NULL;
430 unsigned long flags;
431
432 /*
433 * dma channel priorities
434 * ch 0 - 3, 16 - 19 <--> (0)
435 * ch 4 - 7, 20 - 23 <--> (1)
436 * ch 8 - 11, 24 - 27 <--> (2)
437 * ch 12 - 15, 28 - 31 <--> (3)
438 */
439
440 spin_lock_irqsave(&pdev->phy_lock, flags);
441 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {
442 for (i = 0; i < pdev->nr_chans; i++) {
443 if (prio != (i & 0xf) >> 2)
444 continue;
445 if ((i < 32) && (legacy_reserved & BIT(i)))
446 continue;
447 phy = &pdev->phys[i];
448 if (!phy->vchan) {
449 phy->vchan = pchan;
450 found = phy;
451 if (i < 32)
452 legacy_unavailable |= BIT(i);
453 goto out_unlock;
454 }
455 }
456 }
457
458 out_unlock:
459 spin_unlock_irqrestore(&pdev->phy_lock, flags);
460 dev_dbg(&pchan->vc.chan.dev->device,
461 "%s(): phy=%p(%d)\n", __func__, found,
462 found ? found->idx : -1);
463
464 return found;
465 }
466
467 static void pxad_free_phy(struct pxad_chan *chan)
468 {
469 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
470 unsigned long flags;
471 u32 reg;
472 int i;
473
474 dev_dbg(&chan->vc.chan.dev->device,
475 "%s(): freeing\n", __func__);
476 if (!chan->phy)
477 return;
478
479 /* clear the channel mapping in DRCMR */
480 if (chan->drcmr <= pdev->nr_requestors) {
481 reg = pxad_drcmr(chan->drcmr);
482 writel_relaxed(0, chan->phy->base + reg);
483 }
484
485 spin_lock_irqsave(&pdev->phy_lock, flags);
486 for (i = 0; i < 32; i++)
487 if (chan->phy == &pdev->phys[i])
488 legacy_unavailable &= ~BIT(i);
489 chan->phy->vchan = NULL;
490 chan->phy = NULL;
491 spin_unlock_irqrestore(&pdev->phy_lock, flags);
492 }
493
494 static bool is_chan_running(struct pxad_chan *chan)
495 {
496 u32 dcsr;
497 struct pxad_phy *phy = chan->phy;
498
499 if (!phy)
500 return false;
501 dcsr = phy_readl_relaxed(phy, DCSR);
502 return dcsr & PXA_DCSR_RUN;
503 }
504
505 static bool is_running_chan_misaligned(struct pxad_chan *chan)
506 {
507 u32 dalgn;
508
509 BUG_ON(!chan->phy);
510 dalgn = phy_readl_relaxed(chan->phy, DALGN);
511 return dalgn & (BIT(chan->phy->idx));
512 }
513
514 static void phy_enable(struct pxad_phy *phy, bool misaligned)
515 {
516 struct pxad_device *pdev;
517 u32 reg, dalgn;
518
519 if (!phy->vchan)
520 return;
521
522 dev_dbg(&phy->vchan->vc.chan.dev->device,
523 "%s(); phy=%p(%d) misaligned=%d\n", __func__,
524 phy, phy->idx, misaligned);
525
526 pdev = to_pxad_dev(phy->vchan->vc.chan.device);
527 if (phy->vchan->drcmr <= pdev->nr_requestors) {
528 reg = pxad_drcmr(phy->vchan->drcmr);
529 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
530 }
531
532 dalgn = phy_readl_relaxed(phy, DALGN);
533 if (misaligned)
534 dalgn |= BIT(phy->idx);
535 else
536 dalgn &= ~BIT(phy->idx);
537 phy_writel_relaxed(phy, dalgn, DALGN);
538
539 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |
540 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);
541 }
542
543 static void phy_disable(struct pxad_phy *phy)
544 {
545 u32 dcsr;
546
547 if (!phy)
548 return;
549
550 dcsr = phy_readl_relaxed(phy, DCSR);
551 dev_dbg(&phy->vchan->vc.chan.dev->device,
552 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx);
553 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);
554 }
555
556 static void pxad_launch_chan(struct pxad_chan *chan,
557 struct pxad_desc_sw *desc)
558 {
559 dev_dbg(&chan->vc.chan.dev->device,
560 "%s(): desc=%p\n", __func__, desc);
561 if (!chan->phy) {
562 chan->phy = lookup_phy(chan);
563 if (!chan->phy) {
564 dev_dbg(&chan->vc.chan.dev->device,
565 "%s(): no free dma channel\n", __func__);
566 return;
567 }
568 }
569 chan->bus_error = 0;
570
571 /*
572 * Program the descriptor's address into the DMA controller,
573 * then start the DMA transaction
574 */
575 phy_writel(chan->phy, desc->first, DDADR);
576 phy_enable(chan->phy, chan->misaligned);
577 wake_up(&chan->wq_state);
578 }
579
580 static void set_updater_desc(struct pxad_desc_sw *sw_desc,
581 unsigned long flags)
582 {
583 struct pxad_desc_hw *updater =
584 sw_desc->hw_desc[sw_desc->nb_desc - 1];
585 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;
586
587 updater->ddadr = DDADR_STOP;
588 updater->dsadr = dma;
589 updater->dtadr = dma + 8;
590 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |
591 (PXA_DCMD_LENGTH & sizeof(u32));
592 if (flags & DMA_PREP_INTERRUPT)
593 updater->dcmd |= PXA_DCMD_ENDIRQEN;
594 if (sw_desc->cyclic)
595 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;
596 }
597
598 static bool is_desc_completed(struct virt_dma_desc *vd)
599 {
600 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
601 struct pxad_desc_hw *updater =
602 sw_desc->hw_desc[sw_desc->nb_desc - 1];
603
604 return updater->dtadr != (updater->dsadr + 8);
605 }
606
607 static void pxad_desc_chain(struct virt_dma_desc *vd1,
608 struct virt_dma_desc *vd2)
609 {
610 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);
611 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);
612 dma_addr_t dma_to_chain;
613
614 dma_to_chain = desc2->first;
615 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;
616 }
617
618 static bool pxad_try_hotchain(struct virt_dma_chan *vc,
619 struct virt_dma_desc *vd)
620 {
621 struct virt_dma_desc *vd_last_issued = NULL;
622 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
623
624 /*
625 * Attempt to hot chain the tx if the phy is still running. This is
626 * considered successful only if either the channel is still running
627 * after the chaining, or if the chained transfer is completed after
628 * having been hot chained.
629 * A change of alignment is not allowed, and forbids hotchaining.
630 */
631 if (is_chan_running(chan)) {
632 BUG_ON(list_empty(&vc->desc_issued));
633
634 if (!is_running_chan_misaligned(chan) &&
635 to_pxad_sw_desc(vd)->misaligned)
636 return false;
637
638 vd_last_issued = list_entry(vc->desc_issued.prev,
639 struct virt_dma_desc, node);
640 pxad_desc_chain(vd_last_issued, vd);
641 if (is_chan_running(chan) || is_desc_completed(vd))
642 return true;
643 }
644
645 return false;
646 }
647
648 static unsigned int clear_chan_irq(struct pxad_phy *phy)
649 {
650 u32 dcsr;
651 u32 dint = readl(phy->base + DINT);
652
653 if (!(dint & BIT(phy->idx)))
654 return PXA_DCSR_RUN;
655
656 /* clear irq */
657 dcsr = phy_readl_relaxed(phy, DCSR);
658 phy_writel(phy, dcsr, DCSR);
659 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))
660 dev_warn(&phy->vchan->vc.chan.dev->device,
661 "%s(chan=%p): PXA_DCSR_BUSERR\n",
662 __func__, &phy->vchan);
663
664 return dcsr & ~PXA_DCSR_RUN;
665 }
666
667 static irqreturn_t pxad_chan_handler(int irq, void *dev_id)
668 {
669 struct pxad_phy *phy = dev_id;
670 struct pxad_chan *chan = phy->vchan;
671 struct virt_dma_desc *vd, *tmp;
672 unsigned int dcsr;
673 unsigned long flags;
674 bool vd_completed;
675 dma_cookie_t last_started = 0;
676
677 BUG_ON(!chan);
678
679 dcsr = clear_chan_irq(phy);
680 if (dcsr & PXA_DCSR_RUN)
681 return IRQ_NONE;
682
683 spin_lock_irqsave(&chan->vc.lock, flags);
684 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {
685 vd_completed = is_desc_completed(vd);
686 dev_dbg(&chan->vc.chan.dev->device,
687 "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n",
688 __func__, vd, vd->tx.cookie, vd_completed,
689 dcsr);
690 last_started = vd->tx.cookie;
691 if (to_pxad_sw_desc(vd)->cyclic) {
692 vchan_cyclic_callback(vd);
693 break;
694 }
695 if (vd_completed) {
696 list_del(&vd->node);
697 vchan_cookie_complete(vd);
698 } else {
699 break;
700 }
701 }
702
703 if (dcsr & PXA_DCSR_BUSERR) {
704 chan->bus_error = last_started;
705 phy_disable(phy);
706 }
707
708 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) {
709 dev_dbg(&chan->vc.chan.dev->device,
710 "%s(): channel stopped, submitted_empty=%d issued_empty=%d",
711 __func__,
712 list_empty(&chan->vc.desc_submitted),
713 list_empty(&chan->vc.desc_issued));
714 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);
715
716 if (list_empty(&chan->vc.desc_issued)) {
717 chan->misaligned =
718 !list_empty(&chan->vc.desc_submitted);
719 } else {
720 vd = list_first_entry(&chan->vc.desc_issued,
721 struct virt_dma_desc, node);
722 pxad_launch_chan(chan, to_pxad_sw_desc(vd));
723 }
724 }
725 spin_unlock_irqrestore(&chan->vc.lock, flags);
726 wake_up(&chan->wq_state);
727
728 return IRQ_HANDLED;
729 }
730
731 static irqreturn_t pxad_int_handler(int irq, void *dev_id)
732 {
733 struct pxad_device *pdev = dev_id;
734 struct pxad_phy *phy;
735 u32 dint = readl(pdev->base + DINT);
736 int i, ret = IRQ_NONE;
737
738 while (dint) {
739 i = __ffs(dint);
740 dint &= (dint - 1);
741 phy = &pdev->phys[i];
742 if ((i < 32) && (legacy_reserved & BIT(i)))
743 continue;
744 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)
745 ret = IRQ_HANDLED;
746 }
747
748 return ret;
749 }
750
751 static int pxad_alloc_chan_resources(struct dma_chan *dchan)
752 {
753 struct pxad_chan *chan = to_pxad_chan(dchan);
754 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
755
756 if (chan->desc_pool)
757 return 1;
758
759 chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
760 pdev->slave.dev,
761 sizeof(struct pxad_desc_hw),
762 __alignof__(struct pxad_desc_hw),
763 0);
764 if (!chan->desc_pool) {
765 dev_err(&chan->vc.chan.dev->device,
766 "%s(): unable to allocate descriptor pool\n",
767 __func__);
768 return -ENOMEM;
769 }
770
771 return 1;
772 }
773
774 static void pxad_free_chan_resources(struct dma_chan *dchan)
775 {
776 struct pxad_chan *chan = to_pxad_chan(dchan);
777
778 vchan_free_chan_resources(&chan->vc);
779 dma_pool_destroy(chan->desc_pool);
780 chan->desc_pool = NULL;
781
782 }
783
784 static void pxad_free_desc(struct virt_dma_desc *vd)
785 {
786 int i;
787 dma_addr_t dma;
788 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
789
790 BUG_ON(sw_desc->nb_desc == 0);
791 for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
792 if (i > 0)
793 dma = sw_desc->hw_desc[i - 1]->ddadr;
794 else
795 dma = sw_desc->first;
796 dma_pool_free(sw_desc->desc_pool,
797 sw_desc->hw_desc[i], dma);
798 }
799 sw_desc->nb_desc = 0;
800 kfree(sw_desc);
801 }
802
803 static struct pxad_desc_sw *
804 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)
805 {
806 struct pxad_desc_sw *sw_desc;
807 dma_addr_t dma;
808 int i;
809
810 sw_desc = kzalloc(sizeof(*sw_desc) +
811 nb_hw_desc * sizeof(struct pxad_desc_hw *),
812 GFP_NOWAIT);
813 if (!sw_desc)
814 return NULL;
815 sw_desc->desc_pool = chan->desc_pool;
816
817 for (i = 0; i < nb_hw_desc; i++) {
818 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,
819 GFP_NOWAIT, &dma);
820 if (!sw_desc->hw_desc[i]) {
821 dev_err(&chan->vc.chan.dev->device,
822 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",
823 __func__, i, sw_desc->desc_pool);
824 goto err;
825 }
826
827 if (i == 0)
828 sw_desc->first = dma;
829 else
830 sw_desc->hw_desc[i - 1]->ddadr = dma;
831 sw_desc->nb_desc++;
832 }
833
834 return sw_desc;
835 err:
836 pxad_free_desc(&sw_desc->vd);
837 return NULL;
838 }
839
840 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)
841 {
842 struct virt_dma_chan *vc = to_virt_chan(tx->chan);
843 struct pxad_chan *chan = to_pxad_chan(&vc->chan);
844 struct virt_dma_desc *vd_chained = NULL,
845 *vd = container_of(tx, struct virt_dma_desc, tx);
846 dma_cookie_t cookie;
847 unsigned long flags;
848
849 set_updater_desc(to_pxad_sw_desc(vd), tx->flags);
850
851 spin_lock_irqsave(&vc->lock, flags);
852 cookie = dma_cookie_assign(tx);
853
854 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {
855 list_move_tail(&vd->node, &vc->desc_issued);
856 dev_dbg(&chan->vc.chan.dev->device,
857 "%s(): txd %p[%x]: submitted (hot linked)\n",
858 __func__, vd, cookie);
859 goto out;
860 }
861
862 /*
863 * Fallback to placing the tx in the submitted queue
864 */
865 if (!list_empty(&vc->desc_submitted)) {
866 vd_chained = list_entry(vc->desc_submitted.prev,
867 struct virt_dma_desc, node);
868 /*
869 * Only chain the descriptors if no new misalignment is
870 * introduced. If a new misalignment is chained, let the channel
871 * stop, and be relaunched in misalign mode from the irq
872 * handler.
873 */
874 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)
875 pxad_desc_chain(vd_chained, vd);
876 else
877 vd_chained = NULL;
878 }
879 dev_dbg(&chan->vc.chan.dev->device,
880 "%s(): txd %p[%x]: submitted (%s linked)\n",
881 __func__, vd, cookie, vd_chained ? "cold" : "not");
882 list_move_tail(&vd->node, &vc->desc_submitted);
883 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;
884
885 out:
886 spin_unlock_irqrestore(&vc->lock, flags);
887 return cookie;
888 }
889
890 static void pxad_issue_pending(struct dma_chan *dchan)
891 {
892 struct pxad_chan *chan = to_pxad_chan(dchan);
893 struct virt_dma_desc *vd_first;
894 unsigned long flags;
895
896 spin_lock_irqsave(&chan->vc.lock, flags);
897 if (list_empty(&chan->vc.desc_submitted))
898 goto out;
899
900 vd_first = list_first_entry(&chan->vc.desc_submitted,
901 struct virt_dma_desc, node);
902 dev_dbg(&chan->vc.chan.dev->device,
903 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);
904
905 vchan_issue_pending(&chan->vc);
906 if (!pxad_try_hotchain(&chan->vc, vd_first))
907 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));
908 out:
909 spin_unlock_irqrestore(&chan->vc.lock, flags);
910 }
911
912 static inline struct dma_async_tx_descriptor *
913 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,
914 unsigned long tx_flags)
915 {
916 struct dma_async_tx_descriptor *tx;
917 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);
918
919 INIT_LIST_HEAD(&vd->node);
920 tx = vchan_tx_prep(vc, vd, tx_flags);
921 tx->tx_submit = pxad_tx_submit;
922 dev_dbg(&chan->vc.chan.dev->device,
923 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,
924 vc, vd, vd->tx.cookie,
925 tx_flags);
926
927 return tx;
928 }
929
930 static void pxad_get_config(struct pxad_chan *chan,
931 enum dma_transfer_direction dir,
932 u32 *dcmd, u32 *dev_src, u32 *dev_dst)
933 {
934 u32 maxburst = 0, dev_addr = 0;
935 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
936 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
937
938 *dcmd = 0;
939 if (dir == DMA_DEV_TO_MEM) {
940 maxburst = chan->cfg.src_maxburst;
941 width = chan->cfg.src_addr_width;
942 dev_addr = chan->cfg.src_addr;
943 *dev_src = dev_addr;
944 *dcmd |= PXA_DCMD_INCTRGADDR;
945 if (chan->drcmr <= pdev->nr_requestors)
946 *dcmd |= PXA_DCMD_FLOWSRC;
947 }
948 if (dir == DMA_MEM_TO_DEV) {
949 maxburst = chan->cfg.dst_maxburst;
950 width = chan->cfg.dst_addr_width;
951 dev_addr = chan->cfg.dst_addr;
952 *dev_dst = dev_addr;
953 *dcmd |= PXA_DCMD_INCSRCADDR;
954 if (chan->drcmr <= pdev->nr_requestors)
955 *dcmd |= PXA_DCMD_FLOWTRG;
956 }
957 if (dir == DMA_MEM_TO_MEM)
958 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
959 PXA_DCMD_INCSRCADDR;
960
961 dev_dbg(&chan->vc.chan.dev->device,
962 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n",
963 __func__, dev_addr, maxburst, width, dir);
964
965 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
966 *dcmd |= PXA_DCMD_WIDTH1;
967 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
968 *dcmd |= PXA_DCMD_WIDTH2;
969 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
970 *dcmd |= PXA_DCMD_WIDTH4;
971
972 if (maxburst == 8)
973 *dcmd |= PXA_DCMD_BURST8;
974 else if (maxburst == 16)
975 *dcmd |= PXA_DCMD_BURST16;
976 else if (maxburst == 32)
977 *dcmd |= PXA_DCMD_BURST32;
978
979 /* FIXME: drivers should be ported over to use the filter
980 * function. Once that's done, the following two lines can
981 * be removed.
982 */
983 if (chan->cfg.slave_id)
984 chan->drcmr = chan->cfg.slave_id;
985 }
986
987 static struct dma_async_tx_descriptor *
988 pxad_prep_memcpy(struct dma_chan *dchan,
989 dma_addr_t dma_dst, dma_addr_t dma_src,
990 size_t len, unsigned long flags)
991 {
992 struct pxad_chan *chan = to_pxad_chan(dchan);
993 struct pxad_desc_sw *sw_desc;
994 struct pxad_desc_hw *hw_desc;
995 u32 dcmd;
996 unsigned int i, nb_desc = 0;
997 size_t copy;
998
999 if (!dchan || !len)
1000 return NULL;
1001
1002 dev_dbg(&chan->vc.chan.dev->device,
1003 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",
1004 __func__, (unsigned long)dma_dst, (unsigned long)dma_src,
1005 len, flags);
1006 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);
1007
1008 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);
1009 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1010 if (!sw_desc)
1011 return NULL;
1012 sw_desc->len = len;
1013
1014 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||
1015 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))
1016 sw_desc->misaligned = true;
1017
1018 i = 0;
1019 do {
1020 hw_desc = sw_desc->hw_desc[i++];
1021 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
1022 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);
1023 hw_desc->dsadr = dma_src;
1024 hw_desc->dtadr = dma_dst;
1025 len -= copy;
1026 dma_src += copy;
1027 dma_dst += copy;
1028 } while (len);
1029 set_updater_desc(sw_desc, flags);
1030
1031 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1032 }
1033
1034 static struct dma_async_tx_descriptor *
1035 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
1036 unsigned int sg_len, enum dma_transfer_direction dir,
1037 unsigned long flags, void *context)
1038 {
1039 struct pxad_chan *chan = to_pxad_chan(dchan);
1040 struct pxad_desc_sw *sw_desc;
1041 size_t len, avail;
1042 struct scatterlist *sg;
1043 dma_addr_t dma;
1044 u32 dcmd, dsadr = 0, dtadr = 0;
1045 unsigned int nb_desc = 0, i, j = 0;
1046
1047 if ((sgl == NULL) || (sg_len == 0))
1048 return NULL;
1049
1050 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1051 dev_dbg(&chan->vc.chan.dev->device,
1052 "%s(): dir=%d flags=%lx\n", __func__, dir, flags);
1053
1054 for_each_sg(sgl, sg, sg_len, i)
1055 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);
1056 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1057 if (!sw_desc)
1058 return NULL;
1059
1060 for_each_sg(sgl, sg, sg_len, i) {
1061 dma = sg_dma_address(sg);
1062 avail = sg_dma_len(sg);
1063 sw_desc->len += avail;
1064
1065 do {
1066 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
1067 if (dma & 0x7)
1068 sw_desc->misaligned = true;
1069
1070 sw_desc->hw_desc[j]->dcmd =
1071 dcmd | (PXA_DCMD_LENGTH & len);
1072 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;
1073 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;
1074
1075 dma += len;
1076 avail -= len;
1077 } while (avail);
1078 }
1079 set_updater_desc(sw_desc, flags);
1080
1081 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1082 }
1083
1084 static struct dma_async_tx_descriptor *
1085 pxad_prep_dma_cyclic(struct dma_chan *dchan,
1086 dma_addr_t buf_addr, size_t len, size_t period_len,
1087 enum dma_transfer_direction dir, unsigned long flags)
1088 {
1089 struct pxad_chan *chan = to_pxad_chan(dchan);
1090 struct pxad_desc_sw *sw_desc;
1091 struct pxad_desc_hw **phw_desc;
1092 dma_addr_t dma;
1093 u32 dcmd, dsadr = 0, dtadr = 0;
1094 unsigned int nb_desc = 0;
1095
1096 if (!dchan || !len || !period_len)
1097 return NULL;
1098 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {
1099 dev_err(&chan->vc.chan.dev->device,
1100 "Unsupported direction for cyclic DMA\n");
1101 return NULL;
1102 }
1103 /* the buffer length must be a multiple of period_len */
1104 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||
1105 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))
1106 return NULL;
1107
1108 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1109 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len);
1110 dev_dbg(&chan->vc.chan.dev->device,
1111 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",
1112 __func__, (unsigned long)buf_addr, len, period_len, dir, flags);
1113
1114 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);
1115 nb_desc *= DIV_ROUND_UP(len, period_len);
1116 sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1117 if (!sw_desc)
1118 return NULL;
1119 sw_desc->cyclic = true;
1120 sw_desc->len = len;
1121
1122 phw_desc = sw_desc->hw_desc;
1123 dma = buf_addr;
1124 do {
1125 phw_desc[0]->dsadr = dsadr ? dsadr : dma;
1126 phw_desc[0]->dtadr = dtadr ? dtadr : dma;
1127 phw_desc[0]->dcmd = dcmd;
1128 phw_desc++;
1129 dma += period_len;
1130 len -= period_len;
1131 } while (len);
1132 set_updater_desc(sw_desc, flags);
1133
1134 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1135 }
1136
1137 static int pxad_config(struct dma_chan *dchan,
1138 struct dma_slave_config *cfg)
1139 {
1140 struct pxad_chan *chan = to_pxad_chan(dchan);
1141
1142 if (!dchan)
1143 return -EINVAL;
1144
1145 chan->cfg = *cfg;
1146 return 0;
1147 }
1148
1149 static int pxad_terminate_all(struct dma_chan *dchan)
1150 {
1151 struct pxad_chan *chan = to_pxad_chan(dchan);
1152 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
1153 struct virt_dma_desc *vd = NULL;
1154 unsigned long flags;
1155 struct pxad_phy *phy;
1156 LIST_HEAD(head);
1157
1158 dev_dbg(&chan->vc.chan.dev->device,
1159 "%s(): vchan %p: terminate all\n", __func__, &chan->vc);
1160
1161 spin_lock_irqsave(&chan->vc.lock, flags);
1162 vchan_get_all_descriptors(&chan->vc, &head);
1163
1164 list_for_each_entry(vd, &head, node) {
1165 dev_dbg(&chan->vc.chan.dev->device,
1166 "%s(): cancelling txd %p[%x] (completed=%d)", __func__,
1167 vd, vd->tx.cookie, is_desc_completed(vd));
1168 }
1169
1170 phy = chan->phy;
1171 if (phy) {
1172 phy_disable(chan->phy);
1173 pxad_free_phy(chan);
1174 chan->phy = NULL;
1175 spin_lock(&pdev->phy_lock);
1176 phy->vchan = NULL;
1177 spin_unlock(&pdev->phy_lock);
1178 }
1179 spin_unlock_irqrestore(&chan->vc.lock, flags);
1180 vchan_dma_desc_free_list(&chan->vc, &head);
1181
1182 return 0;
1183 }
1184
1185 static unsigned int pxad_residue(struct pxad_chan *chan,
1186 dma_cookie_t cookie)
1187 {
1188 struct virt_dma_desc *vd = NULL;
1189 struct pxad_desc_sw *sw_desc = NULL;
1190 struct pxad_desc_hw *hw_desc = NULL;
1191 u32 curr, start, len, end, residue = 0;
1192 unsigned long flags;
1193 bool passed = false;
1194 int i;
1195
1196 /*
1197 * If the channel does not have a phy pointer anymore, it has already
1198 * been completed. Therefore, its residue is 0.
1199 */
1200 if (!chan->phy)
1201 return 0;
1202
1203 spin_lock_irqsave(&chan->vc.lock, flags);
1204
1205 vd = vchan_find_desc(&chan->vc, cookie);
1206 if (!vd)
1207 goto out;
1208
1209 sw_desc = to_pxad_sw_desc(vd);
1210 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1211 curr = phy_readl_relaxed(chan->phy, DSADR);
1212 else
1213 curr = phy_readl_relaxed(chan->phy, DTADR);
1214
1215 /*
1216 * curr has to be actually read before checking descriptor
1217 * completion, so that a curr inside a status updater
1218 * descriptor implies the following test returns true, and
1219 * preventing reordering of curr load and the test.
1220 */
1221 rmb();
1222 if (is_desc_completed(vd))
1223 goto out;
1224
1225 for (i = 0; i < sw_desc->nb_desc - 1; i++) {
1226 hw_desc = sw_desc->hw_desc[i];
1227 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1228 start = hw_desc->dsadr;
1229 else
1230 start = hw_desc->dtadr;
1231 len = hw_desc->dcmd & PXA_DCMD_LENGTH;
1232 end = start + len;
1233
1234 /*
1235 * 'passed' will be latched once we found the descriptor
1236 * which lies inside the boundaries of the curr
1237 * pointer. All descriptors that occur in the list
1238 * _after_ we found that partially handled descriptor
1239 * are still to be processed and are hence added to the
1240 * residual bytes counter.
1241 */
1242
1243 if (passed) {
1244 residue += len;
1245 } else if (curr >= start && curr <= end) {
1246 residue += end - curr;
1247 passed = true;
1248 }
1249 }
1250 if (!passed)
1251 residue = sw_desc->len;
1252
1253 out:
1254 spin_unlock_irqrestore(&chan->vc.lock, flags);
1255 dev_dbg(&chan->vc.chan.dev->device,
1256 "%s(): txd %p[%x] sw_desc=%p: %d\n",
1257 __func__, vd, cookie, sw_desc, residue);
1258 return residue;
1259 }
1260
1261 static enum dma_status pxad_tx_status(struct dma_chan *dchan,
1262 dma_cookie_t cookie,
1263 struct dma_tx_state *txstate)
1264 {
1265 struct pxad_chan *chan = to_pxad_chan(dchan);
1266 enum dma_status ret;
1267
1268 if (cookie == chan->bus_error)
1269 return DMA_ERROR;
1270
1271 ret = dma_cookie_status(dchan, cookie, txstate);
1272 if (likely(txstate && (ret != DMA_ERROR)))
1273 dma_set_residue(txstate, pxad_residue(chan, cookie));
1274
1275 return ret;
1276 }
1277
1278 static void pxad_synchronize(struct dma_chan *dchan)
1279 {
1280 struct pxad_chan *chan = to_pxad_chan(dchan);
1281
1282 wait_event(chan->wq_state, !is_chan_running(chan));
1283 vchan_synchronize(&chan->vc);
1284 }
1285
1286 static void pxad_free_channels(struct dma_device *dmadev)
1287 {
1288 struct pxad_chan *c, *cn;
1289
1290 list_for_each_entry_safe(c, cn, &dmadev->channels,
1291 vc.chan.device_node) {
1292 list_del(&c->vc.chan.device_node);
1293 tasklet_kill(&c->vc.task);
1294 }
1295 }
1296
1297 static int pxad_remove(struct platform_device *op)
1298 {
1299 struct pxad_device *pdev = platform_get_drvdata(op);
1300
1301 pxad_cleanup_debugfs(pdev);
1302 pxad_free_channels(&pdev->slave);
1303 dma_async_device_unregister(&pdev->slave);
1304 return 0;
1305 }
1306
1307 static int pxad_init_phys(struct platform_device *op,
1308 struct pxad_device *pdev,
1309 unsigned int nb_phy_chans)
1310 {
1311 int irq0, irq, nr_irq = 0, i, ret;
1312 struct pxad_phy *phy;
1313
1314 irq0 = platform_get_irq(op, 0);
1315 if (irq0 < 0)
1316 return irq0;
1317
1318 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,
1319 sizeof(pdev->phys[0]), GFP_KERNEL);
1320 if (!pdev->phys)
1321 return -ENOMEM;
1322
1323 for (i = 0; i < nb_phy_chans; i++)
1324 if (platform_get_irq(op, i) > 0)
1325 nr_irq++;
1326
1327 for (i = 0; i < nb_phy_chans; i++) {
1328 phy = &pdev->phys[i];
1329 phy->base = pdev->base;
1330 phy->idx = i;
1331 irq = platform_get_irq(op, i);
1332 if ((nr_irq > 1) && (irq > 0))
1333 ret = devm_request_irq(&op->dev, irq,
1334 pxad_chan_handler,
1335 IRQF_SHARED, "pxa-dma", phy);
1336 if ((nr_irq == 1) && (i == 0))
1337 ret = devm_request_irq(&op->dev, irq0,
1338 pxad_int_handler,
1339 IRQF_SHARED, "pxa-dma", pdev);
1340 if (ret) {
1341 dev_err(pdev->slave.dev,
1342 "%s(): can't request irq %d:%d\n", __func__,
1343 irq, ret);
1344 return ret;
1345 }
1346 }
1347
1348 return 0;
1349 }
1350
1351 static const struct of_device_id pxad_dt_ids[] = {
1352 { .compatible = "marvell,pdma-1.0", },
1353 {}
1354 };
1355 MODULE_DEVICE_TABLE(of, pxad_dt_ids);
1356
1357 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,
1358 struct of_dma *ofdma)
1359 {
1360 struct pxad_device *d = ofdma->of_dma_data;
1361 struct dma_chan *chan;
1362
1363 chan = dma_get_any_slave_channel(&d->slave);
1364 if (!chan)
1365 return NULL;
1366
1367 to_pxad_chan(chan)->drcmr = dma_spec->args[0];
1368 to_pxad_chan(chan)->prio = dma_spec->args[1];
1369
1370 return chan;
1371 }
1372
1373 static int pxad_init_dmadev(struct platform_device *op,
1374 struct pxad_device *pdev,
1375 unsigned int nr_phy_chans,
1376 unsigned int nr_requestors)
1377 {
1378 int ret;
1379 unsigned int i;
1380 struct pxad_chan *c;
1381
1382 pdev->nr_chans = nr_phy_chans;
1383 pdev->nr_requestors = nr_requestors;
1384 INIT_LIST_HEAD(&pdev->slave.channels);
1385 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;
1386 pdev->slave.device_free_chan_resources = pxad_free_chan_resources;
1387 pdev->slave.device_tx_status = pxad_tx_status;
1388 pdev->slave.device_issue_pending = pxad_issue_pending;
1389 pdev->slave.device_config = pxad_config;
1390 pdev->slave.device_synchronize = pxad_synchronize;
1391 pdev->slave.device_terminate_all = pxad_terminate_all;
1392
1393 if (op->dev.coherent_dma_mask)
1394 dma_set_mask(&op->dev, op->dev.coherent_dma_mask);
1395 else
1396 dma_set_mask(&op->dev, DMA_BIT_MASK(32));
1397
1398 ret = pxad_init_phys(op, pdev, nr_phy_chans);
1399 if (ret)
1400 return ret;
1401
1402 for (i = 0; i < nr_phy_chans; i++) {
1403 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);
1404 if (!c)
1405 return -ENOMEM;
1406 c->vc.desc_free = pxad_free_desc;
1407 vchan_init(&c->vc, &pdev->slave);
1408 init_waitqueue_head(&c->wq_state);
1409 }
1410
1411 return dma_async_device_register(&pdev->slave);
1412 }
1413
1414 static int pxad_probe(struct platform_device *op)
1415 {
1416 struct pxad_device *pdev;
1417 const struct of_device_id *of_id;
1418 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1419 struct resource *iores;
1420 int ret, dma_channels = 0, nb_requestors = 0;
1421 const enum dma_slave_buswidth widths =
1422 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES |
1423 DMA_SLAVE_BUSWIDTH_4_BYTES;
1424
1425 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1426 if (!pdev)
1427 return -ENOMEM;
1428
1429 spin_lock_init(&pdev->phy_lock);
1430
1431 iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1432 pdev->base = devm_ioremap_resource(&op->dev, iores);
1433 if (IS_ERR(pdev->base))
1434 return PTR_ERR(pdev->base);
1435
1436 of_id = of_match_device(pxad_dt_ids, &op->dev);
1437 if (of_id) {
1438 of_property_read_u32(op->dev.of_node, "#dma-channels",
1439 &dma_channels);
1440 ret = of_property_read_u32(op->dev.of_node, "#dma-requests",
1441 &nb_requestors);
1442 if (ret) {
1443 dev_warn(pdev->slave.dev,
1444 "#dma-requests set to default 32 as missing in OF: %d",
1445 ret);
1446 nb_requestors = 32;
1447 };
1448 } else if (pdata && pdata->dma_channels) {
1449 dma_channels = pdata->dma_channels;
1450 nb_requestors = pdata->nb_requestors;
1451 } else {
1452 dma_channels = 32; /* default 32 channel */
1453 }
1454
1455 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);
1456 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);
1457 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);
1458 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);
1459 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;
1460 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;
1461 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;
1462
1463 pdev->slave.copy_align = PDMA_ALIGNMENT;
1464 pdev->slave.src_addr_widths = widths;
1465 pdev->slave.dst_addr_widths = widths;
1466 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1467 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1468 pdev->slave.descriptor_reuse = true;
1469
1470 pdev->slave.dev = &op->dev;
1471 ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors);
1472 if (ret) {
1473 dev_err(pdev->slave.dev, "unable to register\n");
1474 return ret;
1475 }
1476
1477 if (op->dev.of_node) {
1478 /* Device-tree DMA controller registration */
1479 ret = of_dma_controller_register(op->dev.of_node,
1480 pxad_dma_xlate, pdev);
1481 if (ret < 0) {
1482 dev_err(pdev->slave.dev,
1483 "of_dma_controller_register failed\n");
1484 return ret;
1485 }
1486 }
1487
1488 platform_set_drvdata(op, pdev);
1489 pxad_init_debugfs(pdev);
1490 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",
1491 dma_channels, nb_requestors);
1492 return 0;
1493 }
1494
1495 static const struct platform_device_id pxad_id_table[] = {
1496 { "pxa-dma", },
1497 { },
1498 };
1499
1500 static struct platform_driver pxad_driver = {
1501 .driver = {
1502 .name = "pxa-dma",
1503 .of_match_table = pxad_dt_ids,
1504 },
1505 .id_table = pxad_id_table,
1506 .probe = pxad_probe,
1507 .remove = pxad_remove,
1508 };
1509
1510 bool pxad_filter_fn(struct dma_chan *chan, void *param)
1511 {
1512 struct pxad_chan *c = to_pxad_chan(chan);
1513 struct pxad_param *p = param;
1514
1515 if (chan->device->dev->driver != &pxad_driver.driver)
1516 return false;
1517
1518 c->drcmr = p->drcmr;
1519 c->prio = p->prio;
1520
1521 return true;
1522 }
1523 EXPORT_SYMBOL_GPL(pxad_filter_fn);
1524
1525 int pxad_toggle_reserved_channel(int legacy_channel)
1526 {
1527 if (legacy_unavailable & (BIT(legacy_channel)))
1528 return -EBUSY;
1529 legacy_reserved ^= BIT(legacy_channel);
1530 return 0;
1531 }
1532 EXPORT_SYMBOL_GPL(pxad_toggle_reserved_channel);
1533
1534 module_platform_driver(pxad_driver);
1535
1536 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");
1537 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
1538 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support