drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/err.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/irqdomain.h>
  29 #include <linux/of.h>
  30 #include <linux/of_address.h>
  31 #include <linux/of_device.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/slab.h>
  34 #include <linux/gpio/driver.h>
  35 #include <linux/module.h>
  36
  37 #define MXS_SET         0x4
  38 #define MXS_CLR         0x8
  39
  40 #define PINCTRL_DOUT(p)         ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
  41 #define PINCTRL_DIN(p)          ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
  42 #define PINCTRL_DOE(p)          ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
  43 #define PINCTRL_PIN2IRQ(p)      ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
  44 #define PINCTRL_IRQEN(p)        ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
  45 #define PINCTRL_IRQLEV(p)       ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
  46 #define PINCTRL_IRQPOL(p)       ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
  47 #define PINCTRL_IRQSTAT(p)      ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
  48
  49 #define GPIO_INT_FALL_EDGE      0x0
  50 #define GPIO_INT_LOW_LEV        0x1
  51 #define GPIO_INT_RISE_EDGE      0x2
  52 #define GPIO_INT_HIGH_LEV       0x3
  53 #define GPIO_INT_LEV_MASK       (1 << 0)
  54 #define GPIO_INT_POL_MASK       (1 << 1)
  55
  56 enum mxs_gpio_id {
  57         IMX23_GPIO,
  58         IMX28_GPIO,
  59 };
  60
  61 struct mxs_gpio_port {
  62         void __iomem *base;
  63         int id;
  64         int irq;
  65         struct irq_domain *domain;
  66         struct gpio_chip gc;
  67         enum mxs_gpio_id devid;
  68         u32 both_edges;
  69 };
  70
  71 static inline int is_imx23_gpio(struct mxs_gpio_port *port)
  72 {
  73         return port->devid == IMX23_GPIO;
  74 }
  75
  76 static inline int is_imx28_gpio(struct mxs_gpio_port *port)
  77 {
  78         return port->devid == IMX28_GPIO;
  79 }
  80
  81 /* Note: This driver assumes 32 GPIOs are handled in one register */
  82
  83 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  84 {
  85         u32 val;
  86         u32 pin_mask = 1 << d->hwirq;
  87         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  88         struct mxs_gpio_port *port = gc->private;
  89         void __iomem *pin_addr;
  90         int edge;
  91
  92         port->both_edges &= ~pin_mask;
  93         switch (type) {
  94         case IRQ_TYPE_EDGE_BOTH:
  95                 val = port->gc.get(&port->gc, d->hwirq);
  96                 if (val)
  97                         edge = GPIO_INT_FALL_EDGE;
  98                 else
  99                         edge = GPIO_INT_RISE_EDGE;
 100                 port->both_edges |= pin_mask;
 101                 break;
 102         case IRQ_TYPE_EDGE_RISING:
 103                 edge = GPIO_INT_RISE_EDGE;
 104                 break;
 105         case IRQ_TYPE_EDGE_FALLING:
 106                 edge = GPIO_INT_FALL_EDGE;
 107                 break;
 108         case IRQ_TYPE_LEVEL_LOW:
 109                 edge = GPIO_INT_LOW_LEV;
 110                 break;
 111         case IRQ_TYPE_LEVEL_HIGH:
 112                 edge = GPIO_INT_HIGH_LEV;
 113                 break;
 114         default:
 115                 return -EINVAL;
 116         }
 117
 118         /* set level or edge */
 119         pin_addr = port->base + PINCTRL_IRQLEV(port);
 120         if (edge & GPIO_INT_LEV_MASK)
 121                 writel(pin_mask, pin_addr + MXS_SET);
 122         else
 123                 writel(pin_mask, pin_addr + MXS_CLR);
 124
 125         /* set polarity */
 126         pin_addr = port->base + PINCTRL_IRQPOL(port);
 127         if (edge & GPIO_INT_POL_MASK)
 128                 writel(pin_mask, pin_addr + MXS_SET);
 129         else
 130                 writel(pin_mask, pin_addr + MXS_CLR);
 131
 132         writel(pin_mask,
 133                port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 134
 135         return 0;
 136 }
 137
 138 static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
 139 {
 140         u32 bit, val, edge;
 141         void __iomem *pin_addr;
 142
 143         bit = 1 << gpio;
 144
 145         pin_addr = port->base + PINCTRL_IRQPOL(port);
 146         val = readl(pin_addr);
 147         edge = val & bit;
 148
 149         if (edge)
 150                 writel(bit, pin_addr + MXS_CLR);
 151         else
 152                 writel(bit, pin_addr + MXS_SET);
 153 }
 154
 155 /* MXS has one interrupt *per* gpio port */
 156 static void mxs_gpio_irq_handler(struct irq_desc *desc)
 157 {
 158         u32 irq_stat;
 159         struct mxs_gpio_port *port = irq_desc_get_handler_data(desc);
 160
 161         desc->irq_data.chip->irq_ack(&desc->irq_data);
 162
 163         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port)) &
 164                         readl(port->base + PINCTRL_IRQEN(port));
 165
 166         while (irq_stat != 0) {
 167                 int irqoffset = fls(irq_stat) - 1;
 168                 if (port->both_edges & (1 << irqoffset))
 169                         mxs_flip_edge(port, irqoffset);
 170
 171                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 172                 irq_stat &= ~(1 << irqoffset);
 173         }
 174 }
 175
 176 /*
 177  * Set interrupt number "irq" in the GPIO as a wake-up source.
 178  * While system is running, all registered GPIO interrupts need to have
 179  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 180  * need to have wake-up enabled.
 181  * @param  irq          interrupt source number
 182  * @param  enable       enable as wake-up if equal to non-zero
 183  * @return       This function returns 0 on success.
 184  */
 185 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 186 {
 187         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 188         struct mxs_gpio_port *port = gc->private;
 189
 190         if (enable)
 191                 enable_irq_wake(port->irq);
 192         else
 193                 disable_irq_wake(port->irq);
 194
 195         return 0;
 196 }
 197
 198 static int __init mxs_gpio_init_gc(struct mxs_gpio_port *port, int irq_base)
 199 {
 200         struct irq_chip_generic *gc;
 201         struct irq_chip_type *ct;
 202
 203         gc = irq_alloc_generic_chip("gpio-mxs", 1, irq_base,
 204                                     port->base, handle_level_irq);
 205         if (!gc)
 206                 return -ENOMEM;
 207
 208         gc->private = port;
 209
 210         ct = gc->chip_types;
 211         ct->chip.irq_ack = irq_gc_ack_set_bit;
 212         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 213         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 214         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 215         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 216         ct->regs.ack = PINCTRL_IRQSTAT(port) + MXS_CLR;
 217         ct->regs.mask = PINCTRL_IRQEN(port);
 218
 219         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 220                                IRQ_NOREQUEST, 0);
 221
 222         return 0;
 223 }
 224
 225 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 226 {
 227         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 228
 229         return irq_find_mapping(port->domain, offset);
 230 }
 231
 232 static int mxs_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
 233 {
 234         struct mxs_gpio_port *port = gpiochip_get_data(gc);
 235         u32 mask = 1 << offset;
 236         u32 dir;
 237
 238         dir = readl(port->base + PINCTRL_DOE(port));
 239         return !(dir & mask);
 240 }
 241
 242 static const struct platform_device_id mxs_gpio_ids[] = {
 243         {
 244                 .name = "imx23-gpio",
 245                 .driver_data = IMX23_GPIO,
 246         }, {
 247                 .name = "imx28-gpio",
 248                 .driver_data = IMX28_GPIO,
 249         }, {
 250                 /* sentinel */
 251         }
 252 };
 253 MODULE_DEVICE_TABLE(platform, mxs_gpio_ids);
 254
 255 static const struct of_device_id mxs_gpio_dt_ids[] = {
 256         { .compatible = "fsl,imx23-gpio", .data = (void *) IMX23_GPIO, },
 257         { .compatible = "fsl,imx28-gpio", .data = (void *) IMX28_GPIO, },
 258         { /* sentinel */ }
 259 };
 260 MODULE_DEVICE_TABLE(of, mxs_gpio_dt_ids);
 261
 262 static int mxs_gpio_probe(struct platform_device *pdev)
 263 {
 264         const struct of_device_id *of_id =
 265                         of_match_device(mxs_gpio_dt_ids, &pdev->dev);
 266         struct device_node *np = pdev->dev.of_node;
 267         struct device_node *parent;
 268         static void __iomem *base;
 269         struct mxs_gpio_port *port;
 270         int irq_base;
 271         int err;
 272
 273         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 274         if (!port)
 275                 return -ENOMEM;
 276
 277         port->id = of_alias_get_id(np, "gpio");
 278         if (port->id < 0)
 279                 return port->id;
 280         port->devid = (enum mxs_gpio_id) of_id->data;
 281         port->irq = platform_get_irq(pdev, 0);
 282         if (port->irq < 0)
 283                 return port->irq;
 284
 285         /*
 286          * map memory region only once, as all the gpio ports
 287          * share the same one
 288          */
 289         if (!base) {
 290                 parent = of_get_parent(np);
 291                 base = of_iomap(parent, 0);
 292                 of_node_put(parent);
 293                 if (!base)
 294                         return -EADDRNOTAVAIL;
 295         }
 296         port->base = base;
 297
 298         /*
 299          * select the pin interrupt functionality but initially
 300          * disable the interrupts
 301          */
 302         writel(~0U, port->base + PINCTRL_PIN2IRQ(port));
 303         writel(0, port->base + PINCTRL_IRQEN(port));
 304
 305         /* clear address has to be used to clear IRQSTAT bits */
 306         writel(~0U, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR);
 307
 308         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 309         if (irq_base < 0) {
 310                 err = irq_base;
 311                 goto out_iounmap;
 312         }
 313
 314         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 315                                              &irq_domain_simple_ops, NULL);
 316         if (!port->domain) {
 317                 err = -ENODEV;
 318                 goto out_irqdesc_free;
 319         }
 320
 321         /* gpio-mxs can be a generic irq chip */
 322         err = mxs_gpio_init_gc(port, irq_base);
 323         if (err < 0)
 324                 goto out_irqdomain_remove;
 325
 326         /* setup one handler for each entry */
 327         irq_set_chained_handler_and_data(port->irq, mxs_gpio_irq_handler,
 328                                          port);
 329
 330         err = bgpio_init(&port->gc, &pdev->dev, 4,
 331                          port->base + PINCTRL_DIN(port),
 332                          port->base + PINCTRL_DOUT(port) + MXS_SET,
 333                          port->base + PINCTRL_DOUT(port) + MXS_CLR,
 334                          port->base + PINCTRL_DOE(port), NULL, 0);
 335         if (err)
 336                 goto out_irqdomain_remove;
 337
 338         port->gc.to_irq = mxs_gpio_to_irq;
 339         port->gc.get_direction = mxs_gpio_get_direction;
 340         port->gc.base = port->id * 32;
 341
 342         err = gpiochip_add_data(&port->gc, port);
 343         if (err)
 344                 goto out_irqdomain_remove;
 345
 346         return 0;
 347
 348 out_irqdomain_remove:
 349         irq_domain_remove(port->domain);
 350 out_irqdesc_free:
 351         irq_free_descs(irq_base, 32);
 352 out_iounmap:
 353         iounmap(port->base);
 354         return err;
 355 }
 356
 357 static struct platform_driver mxs_gpio_driver = {
 358         .driver         = {
 359                 .name   = "gpio-mxs",
 360                 .of_match_table = mxs_gpio_dt_ids,
 361         },
 362         .probe          = mxs_gpio_probe,
 363         .id_table       = mxs_gpio_ids,
 364 };
 365
 366 static int __init mxs_gpio_init(void)
 367 {
 368         return platform_driver_register(&mxs_gpio_driver);
 369 }
 370 postcore_initcall(mxs_gpio_init);
 371
 372 MODULE_AUTHOR("Freescale Semiconductor, "
 373               "Daniel Mack <danielncaiaq.de>, "
 374               "Juergen Beisert <kernel@pengutronix.de>");
 375 MODULE_DESCRIPTION("Freescale MXS GPIO");
 376 MODULE_LICENSE("GPL");