drivers/gpio/gpio-wcove.c

   1 /*
   2  * Intel Whiskey Cove PMIC GPIO Driver
   3  *
   4  * This driver is written based on gpio-crystalcove.c
   5  *
   6  * Copyright (C) 2016 Intel Corporation. All rights reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License version
  10  * 2 as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/bitops.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/gpio/driver.h>
  22 #include <linux/mfd/intel_soc_pmic.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/seq_file.h>
  26
  27 /*
  28  * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
  29  * Bank 0: Pin 0 - 6
  30  * Bank 1: Pin 7 - 10
  31  * Bank 2: Pin 11 -12
  32  * Each pin has one output control register and one input control register.
  33  */
  34 #define BANK0_NR_PINS           7
  35 #define BANK1_NR_PINS           4
  36 #define BANK2_NR_PINS           2
  37 #define WCOVE_GPIO_NUM          (BANK0_NR_PINS + BANK1_NR_PINS + BANK2_NR_PINS)
  38 #define WCOVE_VGPIO_NUM         94
  39 /* GPIO output control registers (one per pin): 0x4e44 - 0x4e50 */
  40 #define GPIO_OUT_CTRL_BASE      0x4e44
  41 /* GPIO input control registers (one per pin): 0x4e51 - 0x4e5d */
  42 #define GPIO_IN_CTRL_BASE       0x4e51
  43
  44 /*
  45  * GPIO interrupts are organized in two groups:
  46  * Group 0: Bank 0 pins (Pin 0 - 6)
  47  * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
  48  * Each group has two registers (one bit per pin): status and mask.
  49  */
  50 #define GROUP0_NR_IRQS          7
  51 #define GROUP1_NR_IRQS          6
  52 #define IRQ_MASK_BASE           0x4e19
  53 #define IRQ_STATUS_BASE         0x4e0b
  54 #define GPIO_IRQ0_MASK          GENMASK(6, 0)
  55 #define GPIO_IRQ1_MASK          GENMASK(5, 0)
  56 #define UPDATE_IRQ_TYPE         BIT(0)
  57 #define UPDATE_IRQ_MASK         BIT(1)
  58
  59 #define CTLI_INTCNT_DIS         (0 << 1)
  60 #define CTLI_INTCNT_NE          (1 << 1)
  61 #define CTLI_INTCNT_PE          (2 << 1)
  62 #define CTLI_INTCNT_BE          (3 << 1)
  63
  64 #define CTLO_DIR_IN             (0 << 5)
  65 #define CTLO_DIR_OUT            (1 << 5)
  66
  67 #define CTLO_DRV_MASK           (1 << 4)
  68 #define CTLO_DRV_OD             (0 << 4)
  69 #define CTLO_DRV_CMOS           (1 << 4)
  70
  71 #define CTLO_DRV_REN            (1 << 3)
  72
  73 #define CTLO_RVAL_2KDOWN        (0 << 1)
  74 #define CTLO_RVAL_2KUP          (1 << 1)
  75 #define CTLO_RVAL_50KDOWN       (2 << 1)
  76 #define CTLO_RVAL_50KUP         (3 << 1)
  77
  78 #define CTLO_INPUT_SET  (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  79 #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  80
  81 enum ctrl_register {
  82         CTRL_IN,
  83         CTRL_OUT,
  84 };
  85
  86 /*
  87  * struct wcove_gpio - Whiskey Cove GPIO controller
  88  * @buslock: for bus lock/sync and unlock.
  89  * @chip: the abstract gpio_chip structure.
  90  * @dev: the gpio device
  91  * @regmap: the regmap from the parent device.
  92  * @regmap_irq_chip: the regmap of the gpio irq chip.
  93  * @update: pending IRQ setting update, to be written to the chip upon unlock.
  94  * @intcnt: the Interrupt Detect value to be written.
  95  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  96  */
  97 struct wcove_gpio {
  98         struct mutex buslock;
  99         struct gpio_chip chip;
 100         struct device *dev;
 101         struct regmap *regmap;
 102         struct regmap_irq_chip_data *regmap_irq_chip;
 103         int update;
 104         int intcnt;
 105         bool set_irq_mask;
 106 };
 107
 108 static inline unsigned int to_reg(int gpio, enum ctrl_register reg_type)
 109 {
 110         unsigned int reg;
 111         int bank;
 112
 113         if (gpio < BANK0_NR_PINS)
 114                 bank = 0;
 115         else if (gpio < BANK0_NR_PINS + BANK1_NR_PINS)
 116                 bank = 1;
 117         else
 118                 bank = 2;
 119
 120         if (reg_type == CTRL_IN)
 121                 reg = GPIO_IN_CTRL_BASE + bank;
 122         else
 123                 reg = GPIO_OUT_CTRL_BASE + bank;
 124
 125         return reg;
 126 }
 127
 128 static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio)
 129 {
 130         unsigned int reg, mask;
 131
 132         if (gpio < GROUP0_NR_IRQS) {
 133                 reg = IRQ_MASK_BASE;
 134                 mask = BIT(gpio % GROUP0_NR_IRQS);
 135         } else {
 136                 reg = IRQ_MASK_BASE + 1;
 137                 mask = BIT((gpio - GROUP0_NR_IRQS) % GROUP1_NR_IRQS);
 138         }
 139
 140         if (wg->set_irq_mask)
 141                 regmap_update_bits(wg->regmap, reg, mask, mask);
 142         else
 143                 regmap_update_bits(wg->regmap, reg, mask, 0);
 144 }
 145
 146 static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio)
 147 {
 148         unsigned int reg = to_reg(gpio, CTRL_IN);
 149
 150         regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt);
 151 }
 152
 153 static int wcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
 154 {
 155         struct wcove_gpio *wg = gpiochip_get_data(chip);
 156
 157         return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
 158                             CTLO_INPUT_SET);
 159 }
 160
 161 static int wcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
 162                                     int value)
 163 {
 164         struct wcove_gpio *wg = gpiochip_get_data(chip);
 165
 166         return regmap_write(wg->regmap, to_reg(gpio, CTRL_OUT),
 167                             CTLO_OUTPUT_SET | value);
 168 }
 169
 170 static int wcove_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 171 {
 172         struct wcove_gpio *wg = gpiochip_get_data(chip);
 173         unsigned int val;
 174         int ret;
 175
 176         ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &val);
 177         if (ret)
 178                 return ret;
 179
 180         return !(val & CTLO_DIR_OUT);
 181 }
 182
 183 static int wcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 184 {
 185         struct wcove_gpio *wg = gpiochip_get_data(chip);
 186         unsigned int val;
 187         int ret;
 188
 189         ret = regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &val);
 190         if (ret)
 191                 return ret;
 192
 193         return val & 0x1;
 194 }
 195
 196 static void wcove_gpio_set(struct gpio_chip *chip,
 197                                  unsigned int gpio, int value)
 198 {
 199         struct wcove_gpio *wg = gpiochip_get_data(chip);
 200
 201         if (value)
 202                 regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);
 203         else
 204                 regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);
 205 }
 206
 207 static int wcove_gpio_set_single_ended(struct gpio_chip *chip,
 208                                         unsigned int gpio,
 209                                         enum single_ended_mode mode)
 210 {
 211         struct wcove_gpio *wg = gpiochip_get_data(chip);
 212
 213         switch (mode) {
 214         case LINE_MODE_OPEN_DRAIN:
 215                 return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
 216                                                 CTLO_DRV_MASK, CTLO_DRV_OD);
 217         case LINE_MODE_PUSH_PULL:
 218                 return regmap_update_bits(wg->regmap, to_reg(gpio, CTRL_OUT),
 219                                                 CTLO_DRV_MASK, CTLO_DRV_CMOS);
 220         default:
 221                 break;
 222         }
 223
 224         return -ENOTSUPP;
 225 }
 226
 227 static int wcove_irq_type(struct irq_data *data, unsigned int type)
 228 {
 229         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 230         struct wcove_gpio *wg = gpiochip_get_data(chip);
 231
 232         switch (type) {
 233         case IRQ_TYPE_NONE:
 234                 wg->intcnt = CTLI_INTCNT_DIS;
 235                 break;
 236         case IRQ_TYPE_EDGE_BOTH:
 237                 wg->intcnt = CTLI_INTCNT_BE;
 238                 break;
 239         case IRQ_TYPE_EDGE_RISING:
 240                 wg->intcnt = CTLI_INTCNT_PE;
 241                 break;
 242         case IRQ_TYPE_EDGE_FALLING:
 243                 wg->intcnt = CTLI_INTCNT_NE;
 244                 break;
 245         default:
 246                 return -EINVAL;
 247         }
 248
 249         wg->update |= UPDATE_IRQ_TYPE;
 250
 251         return 0;
 252 }
 253
 254 static void wcove_bus_lock(struct irq_data *data)
 255 {
 256         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 257         struct wcove_gpio *wg = gpiochip_get_data(chip);
 258
 259         mutex_lock(&wg->buslock);
 260 }
 261
 262 static void wcove_bus_sync_unlock(struct irq_data *data)
 263 {
 264         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 265         struct wcove_gpio *wg = gpiochip_get_data(chip);
 266         int gpio = data->hwirq;
 267
 268         if (wg->update & UPDATE_IRQ_TYPE)
 269                 wcove_update_irq_ctrl(wg, gpio);
 270         if (wg->update & UPDATE_IRQ_MASK)
 271                 wcove_update_irq_mask(wg, gpio);
 272         wg->update = 0;
 273
 274         mutex_unlock(&wg->buslock);
 275 }
 276
 277 static void wcove_irq_unmask(struct irq_data *data)
 278 {
 279         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 280         struct wcove_gpio *wg = gpiochip_get_data(chip);
 281
 282         wg->set_irq_mask = false;
 283         wg->update |= UPDATE_IRQ_MASK;
 284 }
 285
 286 static void wcove_irq_mask(struct irq_data *data)
 287 {
 288         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 289         struct wcove_gpio *wg = gpiochip_get_data(chip);
 290
 291         wg->set_irq_mask = true;
 292         wg->update |= UPDATE_IRQ_MASK;
 293 }
 294
 295 static struct irq_chip wcove_irqchip = {
 296         .name                   = "Whiskey Cove",
 297         .irq_mask               = wcove_irq_mask,
 298         .irq_unmask             = wcove_irq_unmask,
 299         .irq_set_type           = wcove_irq_type,
 300         .irq_bus_lock           = wcove_bus_lock,
 301         .irq_bus_sync_unlock    = wcove_bus_sync_unlock,
 302 };
 303
 304 static irqreturn_t wcove_gpio_irq_handler(int irq, void *data)
 305 {
 306         struct wcove_gpio *wg = (struct wcove_gpio *)data;
 307         unsigned int pending, virq, gpio, mask, offset;
 308         u8 p[2];
 309
 310         if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
 311                 dev_err(wg->dev, "Failed to read irq status register\n");
 312                 return IRQ_NONE;
 313         }
 314
 315         pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
 316         if (!pending)
 317                 return IRQ_NONE;
 318
 319         /* Iterate until no interrupt is pending */
 320         while (pending) {
 321                 /* One iteration is for all pending bits */
 322                 for_each_set_bit(gpio, (const unsigned long *)&pending,
 323                                                  WCOVE_GPIO_NUM) {
 324                         offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
 325                         mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
 326                                                                 BIT(gpio);
 327                         virq = irq_find_mapping(wg->chip.irqdomain, gpio);
 328                         handle_nested_irq(virq);
 329                         regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
 330                                                                 mask, mask);
 331                 }
 332
 333                 /* Next iteration */
 334                 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
 335                         dev_err(wg->dev, "Failed to read irq status\n");
 336                         break;
 337                 }
 338
 339                 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
 340         }
 341
 342         return IRQ_HANDLED;
 343 }
 344
 345 static void wcove_gpio_dbg_show(struct seq_file *s,
 346                                       struct gpio_chip *chip)
 347 {
 348         unsigned int ctlo, ctli, irq_mask, irq_status;
 349         struct wcove_gpio *wg = gpiochip_get_data(chip);
 350         int gpio, offset, group, ret = 0;
 351
 352         for (gpio = 0; gpio < WCOVE_GPIO_NUM; gpio++) {
 353                 group = gpio < GROUP0_NR_IRQS ? 0 : 1;
 354                 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
 355                 ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli);
 356                 ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group,
 357                                                         &irq_mask);
 358                 ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group,
 359                                                         &irq_status);
 360                 if (ret) {
 361                         pr_err("Failed to read registers: ctrl out/in or irq status/mask\n");
 362                         break;
 363                 }
 364
 365                 offset = gpio % 8;
 366                 seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s\n",
 367                            gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
 368                            ctli & 0x1 ? "hi" : "lo",
 369                            ctli & CTLI_INTCNT_NE ? "fall" : "    ",
 370                            ctli & CTLI_INTCNT_PE ? "rise" : "    ",
 371                            ctlo,
 372                            irq_mask & BIT(offset) ? "mask  " : "unmask",
 373                            irq_status & BIT(offset) ? "pending" : "       ");
 374         }
 375 }
 376
 377 static int wcove_gpio_probe(struct platform_device *pdev)
 378 {
 379         struct intel_soc_pmic *pmic;
 380         struct wcove_gpio *wg;
 381         int virq, ret, irq;
 382         struct device *dev;
 383
 384         /*
 385          * This gpio platform device is created by a mfd device (see
 386          * drivers/mfd/intel_soc_pmic_bxtwc.c for details). Information
 387          * shared by all sub-devices created by the mfd device, the regmap
 388          * pointer for instance, is stored as driver data of the mfd device
 389          * driver.
 390          */
 391         pmic = dev_get_drvdata(pdev->dev.parent);
 392         if (!pmic)
 393                 return -ENODEV;
 394
 395         irq = platform_get_irq(pdev, 0);
 396         if (irq < 0)
 397                 return irq;
 398
 399         dev = &pdev->dev;
 400
 401         wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL);
 402         if (!wg)
 403                 return -ENOMEM;
 404
 405         wg->regmap_irq_chip = pmic->irq_chip_data_level2;
 406
 407         platform_set_drvdata(pdev, wg);
 408
 409         mutex_init(&wg->buslock);
 410         wg->chip.label = KBUILD_MODNAME;
 411         wg->chip.direction_input = wcove_gpio_dir_in;
 412         wg->chip.direction_output = wcove_gpio_dir_out;
 413         wg->chip.get_direction = wcove_gpio_get_direction;
 414         wg->chip.get = wcove_gpio_get;
 415         wg->chip.set = wcove_gpio_set;
 416         wg->chip.set_single_ended = wcove_gpio_set_single_ended,
 417         wg->chip.base = -1;
 418         wg->chip.ngpio = WCOVE_VGPIO_NUM;
 419         wg->chip.can_sleep = true;
 420         wg->chip.parent = pdev->dev.parent;
 421         wg->chip.dbg_show = wcove_gpio_dbg_show;
 422         wg->dev = dev;
 423         wg->regmap = pmic->regmap;
 424
 425         ret = devm_gpiochip_add_data(dev, &wg->chip, wg);
 426         if (ret) {
 427                 dev_err(dev, "Failed to add gpiochip: %d\n", ret);
 428                 return ret;
 429         }
 430
 431         ret = gpiochip_irqchip_add(&wg->chip, &wcove_irqchip, 0,
 432                              handle_simple_irq, IRQ_TYPE_NONE);
 433         if (ret) {
 434                 dev_err(dev, "Failed to add irqchip: %d\n", ret);
 435                 return ret;
 436         }
 437
 438         virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq);
 439         if (virq < 0) {
 440                 dev_err(dev, "Failed to get virq by irq %d\n", irq);
 441                 return virq;
 442         }
 443
 444         ret = devm_request_threaded_irq(dev, virq, NULL,
 445                 wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg);
 446         if (ret) {
 447                 dev_err(dev, "Failed to request irq %d\n", virq);
 448                 return ret;
 449         }
 450
 451         return 0;
 452 }
 453
 454 /*
 455  * Whiskey Cove PMIC itself is a analog device(but with digital control
 456  * interface) providing power management support for other devices in
 457  * the accompanied SoC, so we have no .pm for Whiskey Cove GPIO driver.
 458  */
 459 static struct platform_driver wcove_gpio_driver = {
 460         .driver = {
 461                 .name = "bxt_wcove_gpio",
 462         },
 463         .probe = wcove_gpio_probe,
 464 };
 465
 466 module_platform_driver(wcove_gpio_driver);
 467
 468 MODULE_AUTHOR("Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>");
 469 MODULE_AUTHOR("Bin Gao <bin.gao@intel.com>");
 470 MODULE_DESCRIPTION("Intel Whiskey Cove GPIO Driver");
 471 MODULE_LICENSE("GPL v2");
 472 MODULE_ALIAS("platform:bxt_wcove_gpio");