drivers/misc/cxl/cxl.h

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _CXL_H_
  11 #define _CXL_H_
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/semaphore.h>
  15 #include <linux/device.h>
  16 #include <linux/types.h>
  17 #include <linux/cdev.h>
  18 #include <linux/pid.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <linux/fs.h>
  22 #include <asm/cputable.h>
  23 #include <asm/mmu.h>
  24 #include <asm/reg.h>
  25 #include <misc/cxl-base.h>
  26
  27 #include <misc/cxl.h>
  28 #include <uapi/misc/cxl.h>
  29
  30 extern uint cxl_verbose;
  31
  32 #define CXL_TIMEOUT 5
  33
  34 /*
  35  * Bump version each time a user API change is made, whether it is
  36  * backwards compatible ot not.
  37  */
  38 #define CXL_API_VERSION 3
  39 #define CXL_API_VERSION_COMPATIBLE 1
  40
  41 /*
  42  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  43  *
  44  * At the end of the day, I'm not married to using typedef here, but it might
  45  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  46  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  47  *
  48  * I'm quite happy if these are changed back to #defines before upstreaming, it
  49  * should be little more than a regexp search+replace operation in this file.
  50  */
  51 typedef struct {
  52         const int x;
  53 } cxl_p1_reg_t;
  54 typedef struct {
  55         const int x;
  56 } cxl_p1n_reg_t;
  57 typedef struct {
  58         const int x;
  59 } cxl_p2n_reg_t;
  60 #define cxl_reg_off(reg) \
  61         (reg.x)
  62
  63 /* Memory maps. Ref CXL Appendix A */
  64
  65 /* PSL Privilege 1 Memory Map */
  66 /* Configuration and Control area */
  67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  69 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  70 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  72 /* Downloading */
  73 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  74 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  75
  76 /* PSL Lookaside Buffer Management Area */
  77 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  78 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  79 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  80 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  81 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  82 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  83
  84 /* 0x00C0:7EFF Implementation dependent area */
  85 /* PSL registers */
  86 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  87 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  88 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  89 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  95 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  96 /* XSL registers (Mellanox CX4) */
  97 static const cxl_p1_reg_t CXL_XSL_Timebase  = {0x0100};
  98 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
  99 static const cxl_p1_reg_t CXL_XSL_FEC       = {0x0158};
 100 static const cxl_p1_reg_t CXL_XSL_DSNCTL    = {0x0168};
 101 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
 102 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
 103
 104 /* PSL Slice Privilege 1 Memory Map */
 105 /* Configuration Area */
 106 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 107 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 108 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 109 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 110 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 111 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 112 /* Memory Management and Lookaside Buffer Management */
 113 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 114 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 115 /* Pointer Area */
 116 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 117 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 118 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 119 /* Control Area */
 120 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 121 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 122 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 123 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 124 /* 0xC0:FF Implementation Dependent Area */
 125 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 126 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 127 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 128 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 129 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 130 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 131
 132 /* PSL Slice Privilege 2 Memory Map */
 133 /* Configuration and Control Area */
 134 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 135 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 136 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 137 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 138 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 139 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 140 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 141 /* Segment Lookaside Buffer Management */
 142 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 143 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 144 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 145 /* Interrupt Registers */
 146 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 147 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 148 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 149 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 150 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 151 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 152 /* AFU Registers */
 153 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 154 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 155 /* Work Element Descriptor */
 156 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 157 /* 0x0C0:FFF Implementation Dependent Area */
 158
 159 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 160 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 161 #define CXL_PSL_SPAP_Size_Shift 4
 162 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 163
 164 /****** CXL_PSL_Control ****************************************************/
 165 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
 166 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
 167 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
 168 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
 169
 170 /****** CXL_PSL_DLCNTL *****************************************************/
 171 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 172 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 173 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 174 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 175 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 176 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 177
 178 /****** CXL_PSL_SR_An ******************************************************/
 179 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 180 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 181 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 182 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 183 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 184 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 185 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 186 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 187 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 188 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 189 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 190
 191 /****** CXL_PSL_ID_An ****************************************************/
 192 #define CXL_PSL_ID_An_F (1ull << (63-31))
 193 #define CXL_PSL_ID_An_L (1ull << (63-30))
 194
 195 /****** CXL_PSL_SERR_An ****************************************************/
 196 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
 197 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
 198 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
 199 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
 200 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
 201 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
 202 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
 203 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
 204 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
 205 #define CXL_PSL_SERR_An_AE      (1ull << (63-30))
 206
 207 /****** CXL_PSL_SCNTL_An ****************************************************/
 208 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 209 /* Programming Modes: */
 210 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 211 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 212 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 213 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 214 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 215 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 216 /* Purge Status (ro) */
 217 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 218 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 219 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 220 /* Purge */
 221 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 222 /* Suspend Status (ro) */
 223 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 224 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 225 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 226 /* Suspend Control */
 227 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 228
 229 /* AFU Slice Enable Status (ro) */
 230 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 231 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 232 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 233 /* AFU Slice Enable */
 234 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 235 /* AFU Slice Reset status (ro) */
 236 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 237 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 238 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 239 /* AFU Slice Reset */
 240 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 241
 242 /****** CXL_SSTP0/1_An ******************************************************/
 243 /* These top bits are for the segment that CONTAINS the segment table */
 244 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 245 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 246 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 247 #define CXL_SSTP0_An_N              (1ull << (63-4))
 248 #define CXL_SSTP0_An_L              (1ull << (63-5))
 249 #define CXL_SSTP0_An_C              (1ull << (63-6))
 250 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 251 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 252 /* And finally, the virtual address & size of the segment table: */
 253 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 254 #define CXL_SSTP0_An_SegTableSize_MASK \
 255         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 256 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 257 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 258 #define CXL_SSTP1_An_V              (1ull << (63-63))
 259
 260 /****** CXL_PSL_SLBIE_[An] **************************************************/
 261 /* write: */
 262 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 263 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 264 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 265 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 266 /* read: */
 267 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 268 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 269
 270 /****** Common to all CXL_TLBIA/SLBIA_[An] **********************************/
 271 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 272
 273 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers **********************/
 274 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 275 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 276 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 277
 278 /****** CXL_PSL_AFUSEL ******************************************************/
 279 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 280
 281 /****** CXL_PSL_DSISR_An ****************************************************/
 282 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 283 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 284 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 285 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 286 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 287 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 288 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 289 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 290 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 291 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 292 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 293 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 294 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 295 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 296 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 297
 298 /****** CXL_PSL_TFC_An ******************************************************/
 299 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 300 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 301 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 302 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 303
 304 /* cxl_process_element->software_status */
 305 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 306 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 307 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 308 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 309
 310 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 311  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 312  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 313  * of the hang pulse frequency.
 314  */
 315 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 316
 317 /* SPA->sw_command_status */
 318 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 319 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 320 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 321 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 322 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 323 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 324 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 325 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 326 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 327 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 328 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 329 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 330 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 331 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 332 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 333 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 334
 335 #define CXL_MAX_SLICES 4
 336 #define MAX_AFU_MMIO_REGS 3
 337
 338 #define CXL_MODE_TIME_SLICED 0x4
 339 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 340
 341 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 342 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 343 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 344
 345 enum cxl_context_status {
 346         CLOSED,
 347         OPENED,
 348         STARTED
 349 };
 350
 351 enum prefault_modes {
 352         CXL_PREFAULT_NONE,
 353         CXL_PREFAULT_WED,
 354         CXL_PREFAULT_ALL,
 355 };
 356
 357 enum cxl_attrs {
 358         CXL_ADAPTER_ATTRS,
 359         CXL_AFU_MASTER_ATTRS,
 360         CXL_AFU_ATTRS,
 361 };
 362
 363 struct cxl_sste {
 364         __be64 esid_data;
 365         __be64 vsid_data;
 366 };
 367
 368 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 369 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 370
 371 struct cxl_afu_native {
 372         void __iomem *p1n_mmio;
 373         void __iomem *afu_desc_mmio;
 374         irq_hw_number_t psl_hwirq;
 375         unsigned int psl_virq;
 376         struct mutex spa_mutex;
 377         /*
 378          * Only the first part of the SPA is used for the process element
 379          * linked list. The only other part that software needs to worry about
 380          * is sw_command_status, which we store a separate pointer to.
 381          * Everything else in the SPA is only used by hardware
 382          */
 383         struct cxl_process_element *spa;
 384         __be64 *sw_command_status;
 385         unsigned int spa_size;
 386         int spa_order;
 387         int spa_max_procs;
 388         u64 pp_offset;
 389 };
 390
 391 struct cxl_afu_guest {
 392         struct cxl_afu *parent;
 393         u64 handle;
 394         phys_addr_t p2n_phys;
 395         u64 p2n_size;
 396         int max_ints;
 397         bool handle_err;
 398         struct delayed_work work_err;
 399         int previous_state;
 400 };
 401
 402 struct cxl_afu {
 403         struct cxl_afu_native *native;
 404         struct cxl_afu_guest *guest;
 405         irq_hw_number_t serr_hwirq;
 406         unsigned int serr_virq;
 407         char *psl_irq_name;
 408         char *err_irq_name;
 409         void __iomem *p2n_mmio;
 410         phys_addr_t psn_phys;
 411         u64 pp_size;
 412
 413         struct cxl *adapter;
 414         struct device dev;
 415         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 416         struct device *chardev_s, *chardev_m, *chardev_d;
 417         struct idr contexts_idr;
 418         struct dentry *debugfs;
 419         struct mutex contexts_lock;
 420         spinlock_t afu_cntl_lock;
 421
 422         /* -1: AFU deconfigured/locked, >= 0: number of readers */
 423         atomic_t configured_state;
 424
 425         /* AFU error buffer fields and bin attribute for sysfs */
 426         u64 eb_len, eb_offset;
 427         struct bin_attribute attr_eb;
 428
 429         /* pointer to the vphb */
 430         struct pci_controller *phb;
 431
 432         int pp_irqs;
 433         int irqs_max;
 434         int num_procs;
 435         int max_procs_virtualised;
 436         int slice;
 437         int modes_supported;
 438         int current_mode;
 439         int crs_num;
 440         u64 crs_len;
 441         u64 crs_offset;
 442         struct list_head crs;
 443         enum prefault_modes prefault_mode;
 444         bool psa;
 445         bool pp_psa;
 446         bool enabled;
 447 };
 448
 449
 450 struct cxl_irq_name {
 451         struct list_head list;
 452         char *name;
 453 };
 454
 455 struct irq_avail {
 456         irq_hw_number_t offset;
 457         irq_hw_number_t range;
 458         unsigned long   *bitmap;
 459 };
 460
 461 /*
 462  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 463  * of these per AFU.  If in AFU directed there can be lots of these.
 464  */
 465 struct cxl_context {
 466         struct cxl_afu *afu;
 467
 468         /* Problem state MMIO */
 469         phys_addr_t psn_phys;
 470         u64 psn_size;
 471
 472         /* Used to unmap any mmaps when force detaching */
 473         struct address_space *mapping;
 474         struct mutex mapping_lock;
 475         struct page *ff_page;
 476         bool mmio_err_ff;
 477         bool kernelapi;
 478
 479         spinlock_t sste_lock; /* Protects segment table entries */
 480         struct cxl_sste *sstp;
 481         u64 sstp0, sstp1;
 482         unsigned int sst_size, sst_lru;
 483
 484         wait_queue_head_t wq;
 485         /* pid of the group leader associated with the pid */
 486         struct pid *glpid;
 487         /* use mm context associated with this pid for ds faults */
 488         struct pid *pid;
 489         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 490         /* Only used in PR mode */
 491         u64 process_token;
 492
 493         /* driver private data */
 494         void *priv;
 495
 496         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 497         struct cxl_irq_ranges irqs;
 498         struct list_head irq_names;
 499         u64 fault_addr;
 500         u64 fault_dsisr;
 501         u64 afu_err;
 502
 503         /*
 504          * This status and it's lock pretects start and detach context
 505          * from racing.  It also prevents detach from racing with
 506          * itself
 507          */
 508         enum cxl_context_status status;
 509         struct mutex status_mutex;
 510
 511
 512         /* XXX: Is it possible to need multiple work items at once? */
 513         struct work_struct fault_work;
 514         u64 dsisr;
 515         u64 dar;
 516
 517         struct cxl_process_element *elem;
 518
 519         /*
 520          * pe is the process element handle, assigned by this driver when the
 521          * context is initialized.
 522          *
 523          * external_pe is the PE shown outside of cxl.
 524          * On bare-metal, pe=external_pe, because we decide what the handle is.
 525          * In a guest, we only find out about the pe used by pHyp when the
 526          * context is attached, and that's the value we want to report outside
 527          * of cxl.
 528          */
 529         int pe;
 530         int external_pe;
 531
 532         u32 irq_count;
 533         bool pe_inserted;
 534         bool master;
 535         bool kernel;
 536         bool real_mode;
 537         bool pending_irq;
 538         bool pending_fault;
 539         bool pending_afu_err;
 540
 541         /* Used by AFU drivers for driver specific event delivery */
 542         struct cxl_afu_driver_ops *afu_driver_ops;
 543         atomic_t afu_driver_events;
 544
 545         struct rcu_head rcu;
 546
 547         /*
 548          * Only used when more interrupts are allocated via
 549          * pci_enable_msix_range than are supported in the default context, to
 550          * use additional contexts to overcome the limitation. i.e. Mellanox
 551          * CX4 only:
 552          */
 553         struct list_head extra_irq_contexts;
 554 };
 555
 556 struct cxl_service_layer_ops {
 557         int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
 558         int (*afu_regs_init)(struct cxl_afu *afu);
 559         int (*register_serr_irq)(struct cxl_afu *afu);
 560         void (*release_serr_irq)(struct cxl_afu *afu);
 561         void (*debugfs_add_adapter_sl_regs)(struct cxl *adapter, struct dentry *dir);
 562         void (*debugfs_add_afu_sl_regs)(struct cxl_afu *afu, struct dentry *dir);
 563         void (*psl_irq_dump_registers)(struct cxl_context *ctx);
 564         void (*err_irq_dump_registers)(struct cxl *adapter);
 565         void (*debugfs_stop_trace)(struct cxl *adapter);
 566         void (*write_timebase_ctrl)(struct cxl *adapter);
 567         u64 (*timebase_read)(struct cxl *adapter);
 568         int capi_mode;
 569         bool needs_reset_before_disable;
 570 };
 571
 572 struct cxl_native {
 573         u64 afu_desc_off;
 574         u64 afu_desc_size;
 575         void __iomem *p1_mmio;
 576         void __iomem *p2_mmio;
 577         irq_hw_number_t err_hwirq;
 578         unsigned int err_virq;
 579         u64 ps_off;
 580         const struct cxl_service_layer_ops *sl_ops;
 581 };
 582
 583 struct cxl_guest {
 584         struct platform_device *pdev;
 585         int irq_nranges;
 586         struct cdev cdev;
 587         irq_hw_number_t irq_base_offset;
 588         struct irq_avail *irq_avail;
 589         spinlock_t irq_alloc_lock;
 590         u64 handle;
 591         char *status;
 592         u16 vendor;
 593         u16 device;
 594         u16 subsystem_vendor;
 595         u16 subsystem;
 596 };
 597
 598 struct cxl {
 599         struct cxl_native *native;
 600         struct cxl_guest *guest;
 601         spinlock_t afu_list_lock;
 602         struct cxl_afu *afu[CXL_MAX_SLICES];
 603         struct device dev;
 604         struct dentry *trace;
 605         struct dentry *psl_err_chk;
 606         struct dentry *debugfs;
 607         char *irq_name;
 608         struct bin_attribute cxl_attr;
 609         int adapter_num;
 610         int user_irqs;
 611         int min_pe;
 612         u64 ps_size;
 613         u16 psl_rev;
 614         u16 base_image;
 615         u8 vsec_status;
 616         u8 caia_major;
 617         u8 caia_minor;
 618         u8 slices;
 619         bool user_image_loaded;
 620         bool perst_loads_image;
 621         bool perst_select_user;
 622         bool perst_same_image;
 623         bool psl_timebase_synced;
 624
 625         /*
 626          * number of contexts mapped on to this card. Possible values are:
 627          * >0: Number of contexts mapped and new one can be mapped.
 628          *  0: No active contexts and new ones can be mapped.
 629          * -1: No contexts mapped and new ones cannot be mapped.
 630          */
 631         atomic_t contexts_num;
 632 };
 633
 634 int cxl_pci_alloc_one_irq(struct cxl *adapter);
 635 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 636 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 637 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 638 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 639 int cxl_update_image_control(struct cxl *adapter);
 640 int cxl_pci_reset(struct cxl *adapter);
 641 void cxl_pci_release_afu(struct device *dev);
 642 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 643
 644 /* common == phyp + powernv */
 645 struct cxl_process_element_common {
 646         __be32 tid;
 647         __be32 pid;
 648         __be64 csrp;
 649         __be64 aurp0;
 650         __be64 aurp1;
 651         __be64 sstp0;
 652         __be64 sstp1;
 653         __be64 amr;
 654         u8     reserved3[4];
 655         __be64 wed;
 656 } __packed;
 657
 658 /* just powernv */
 659 struct cxl_process_element {
 660         __be64 sr;
 661         __be64 SPOffset;
 662         __be64 sdr;
 663         __be64 haurp;
 664         __be32 ctxtime;
 665         __be16 ivte_offsets[4];
 666         __be16 ivte_ranges[4];
 667         __be32 lpid;
 668         struct cxl_process_element_common common;
 669         __be32 software_state;
 670 } __packed;
 671
 672 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 673 {
 674         struct pci_dev *pdev;
 675
 676         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 677                 pdev = to_pci_dev(cxl->dev.parent);
 678                 return !pci_channel_offline(pdev);
 679         }
 680         return true;
 681 }
 682
 683 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 684 {
 685         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 686         return cxl->native->p1_mmio + cxl_reg_off(reg);
 687 }
 688
 689 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 690 {
 691         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 692                 out_be64(_cxl_p1_addr(cxl, reg), val);
 693 }
 694
 695 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 696 {
 697         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 698                 return in_be64(_cxl_p1_addr(cxl, reg));
 699         else
 700                 return ~0ULL;
 701 }
 702
 703 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 704 {
 705         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 706         return afu->native->p1n_mmio + cxl_reg_off(reg);
 707 }
 708
 709 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 710 {
 711         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 712                 out_be64(_cxl_p1n_addr(afu, reg), val);
 713 }
 714
 715 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 716 {
 717         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 718                 return in_be64(_cxl_p1n_addr(afu, reg));
 719         else
 720                 return ~0ULL;
 721 }
 722
 723 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 724 {
 725         return afu->p2n_mmio + cxl_reg_off(reg);
 726 }
 727
 728 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 729 {
 730         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 731                 out_be64(_cxl_p2n_addr(afu, reg), val);
 732 }
 733
 734 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 735 {
 736         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 737                 return in_be64(_cxl_p2n_addr(afu, reg));
 738         else
 739                 return ~0ULL;
 740 }
 741
 742 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 743                                 loff_t off, size_t count);
 744
 745 /* Internal functions wrapped in cxl_base to allow PHB to call them */
 746 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
 747 void _cxl_pci_disable_device(struct pci_dev *dev);
 748 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 749 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 750 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
 751
 752 struct cxl_calls {
 753         void (*cxl_slbia)(struct mm_struct *mm);
 754         bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
 755         void (*cxl_pci_disable_device)(struct pci_dev *dev);
 756         int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
 757         int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
 758         void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
 759
 760         struct module *owner;
 761 };
 762 int register_cxl_calls(struct cxl_calls *calls);
 763 void unregister_cxl_calls(struct cxl_calls *calls);
 764 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 765
 766 void cxl_remove_adapter_nr(struct cxl *adapter);
 767
 768 int cxl_alloc_spa(struct cxl_afu *afu);
 769 void cxl_release_spa(struct cxl_afu *afu);
 770
 771 dev_t cxl_get_dev(void);
 772 int cxl_file_init(void);
 773 void cxl_file_exit(void);
 774 int cxl_register_adapter(struct cxl *adapter);
 775 int cxl_register_afu(struct cxl_afu *afu);
 776 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 777 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 778 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 779 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 780
 781 void cxl_context_detach_all(struct cxl_afu *afu);
 782 void cxl_context_free(struct cxl_context *ctx);
 783 void cxl_context_detach(struct cxl_context *ctx);
 784
 785 int cxl_sysfs_adapter_add(struct cxl *adapter);
 786 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 787 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 788 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 789 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 790 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 791
 792 struct cxl *cxl_alloc_adapter(void);
 793 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 794 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 795
 796 int cxl_native_register_psl_irq(struct cxl_afu *afu);
 797 void cxl_native_release_psl_irq(struct cxl_afu *afu);
 798 int cxl_native_register_psl_err_irq(struct cxl *adapter);
 799 void cxl_native_release_psl_err_irq(struct cxl *adapter);
 800 int cxl_native_register_serr_irq(struct cxl_afu *afu);
 801 void cxl_native_release_serr_irq(struct cxl_afu *afu);
 802 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 803 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 804 void afu_irq_name_free(struct cxl_context *ctx);
 805
 806 int cxl_debugfs_init(void);
 807 void cxl_debugfs_exit(void);
 808 int cxl_debugfs_adapter_add(struct cxl *adapter);
 809 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 810 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 811 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 812
 813 void cxl_handle_fault(struct work_struct *work);
 814 void cxl_prefault(struct cxl_context *ctx, u64 wed);
 815
 816 struct cxl *get_cxl_adapter(int num);
 817 int cxl_alloc_sst(struct cxl_context *ctx);
 818 void cxl_dump_debug_buffer(void *addr, size_t size);
 819
 820 void init_cxl_native(void);
 821
 822 struct cxl_context *cxl_context_alloc(void);
 823 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master,
 824                      struct address_space *mapping);
 825 void cxl_context_free(struct cxl_context *ctx);
 826 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
 827 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 828                          irq_handler_t handler, void *cookie, const char *name);
 829 void cxl_unmap_irq(unsigned int virq, void *cookie);
 830 int __detach_context(struct cxl_context *ctx);
 831
 832 /*
 833  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
 834  * in PAPR.
 835  * A word about endianness: a pointer to this structure is passed when
 836  * calling the hcall. However, it is not a block of memory filled up by
 837  * the hypervisor. The return values are found in registers, and copied
 838  * one by one when returning from the hcall. See the end of the call to
 839  * plpar_hcall9() in hvCall.S
 840  * As a consequence:
 841  * - we don't need to do any endianness conversion
 842  * - the pid and tid are an exception. They are 32-bit values returned in
 843  *   the same 64-bit register. So we do need to worry about byte ordering.
 844  */
 845 struct cxl_irq_info {
 846         u64 dsisr;
 847         u64 dar;
 848         u64 dsr;
 849 #ifndef CONFIG_CPU_LITTLE_ENDIAN
 850         u32 pid;
 851         u32 tid;
 852 #else
 853         u32 tid;
 854         u32 pid;
 855 #endif
 856         u64 afu_err;
 857         u64 errstat;
 858         u64 proc_handle;
 859         u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
 860 };
 861
 862 void cxl_assign_psn_space(struct cxl_context *ctx);
 863 irqreturn_t cxl_irq(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 864 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
 865                         void *cookie, irq_hw_number_t *dest_hwirq,
 866                         unsigned int *dest_virq, const char *name);
 867
 868 int cxl_check_error(struct cxl_afu *afu);
 869 int cxl_afu_slbia(struct cxl_afu *afu);
 870 int cxl_tlb_slb_invalidate(struct cxl *adapter);
 871 int cxl_data_cache_flush(struct cxl *adapter);
 872 int cxl_afu_disable(struct cxl_afu *afu);
 873 int cxl_psl_purge(struct cxl_afu *afu);
 874
 875 void cxl_debugfs_add_adapter_psl_regs(struct cxl *adapter, struct dentry *dir);
 876 void cxl_debugfs_add_adapter_xsl_regs(struct cxl *adapter, struct dentry *dir);
 877 void cxl_debugfs_add_afu_psl_regs(struct cxl_afu *afu, struct dentry *dir);
 878 void cxl_native_psl_irq_dump_regs(struct cxl_context *ctx);
 879 void cxl_native_err_irq_dump_regs(struct cxl *adapter);
 880 void cxl_stop_trace(struct cxl *cxl);
 881 int cxl_pci_vphb_add(struct cxl_afu *afu);
 882 void cxl_pci_vphb_remove(struct cxl_afu *afu);
 883
 884 extern struct pci_driver cxl_pci_driver;
 885 extern struct platform_driver cxl_of_driver;
 886 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
 887
 888 int afu_open(struct inode *inode, struct file *file);
 889 int afu_release(struct inode *inode, struct file *file);
 890 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
 891 int afu_mmap(struct file *file, struct vm_area_struct *vm);
 892 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
 893 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
 894 extern const struct file_operations afu_fops;
 895
 896 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
 897 void cxl_guest_remove_adapter(struct cxl *adapter);
 898 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
 899 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
 900 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 901 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
 902 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
 903 void cxl_guest_remove_afu(struct cxl_afu *afu);
 904 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
 905 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
 906 int cxl_guest_add_chardev(struct cxl *adapter);
 907 void cxl_guest_remove_chardev(struct cxl *adapter);
 908 void cxl_guest_reload_module(struct cxl *adapter);
 909 int cxl_of_probe(struct platform_device *pdev);
 910
 911 struct cxl_backend_ops {
 912         struct module *module;
 913         int (*adapter_reset)(struct cxl *adapter);
 914         int (*alloc_one_irq)(struct cxl *adapter);
 915         void (*release_one_irq)(struct cxl *adapter, int hwirq);
 916         int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
 917                                 struct cxl *adapter, unsigned int num);
 918         void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
 919                                 struct cxl *adapter);
 920         int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
 921                         unsigned int virq);
 922         irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
 923                                         u64 dsisr, u64 errstat);
 924         irqreturn_t (*psl_interrupt)(int irq, void *data);
 925         int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
 926         void (*irq_wait)(struct cxl_context *ctx);
 927         int (*attach_process)(struct cxl_context *ctx, bool kernel,
 928                         u64 wed, u64 amr);
 929         int (*detach_process)(struct cxl_context *ctx);
 930         void (*update_ivtes)(struct cxl_context *ctx);
 931         bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
 932         bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
 933         void (*release_afu)(struct device *dev);
 934         ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
 935                                 loff_t off, size_t count);
 936         int (*afu_check_and_enable)(struct cxl_afu *afu);
 937         int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
 938         int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
 939         int (*afu_reset)(struct cxl_afu *afu);
 940         int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
 941         int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
 942         int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
 943         int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
 944         int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
 945         int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
 946         int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
 947         ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
 948 };
 949 extern const struct cxl_backend_ops cxl_native_ops;
 950 extern const struct cxl_backend_ops cxl_guest_ops;
 951 extern const struct cxl_backend_ops *cxl_ops;
 952
 953 /* check if the given pci_dev is on the the cxl vphb bus */
 954 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
 955
 956 /* decode AFU error bits in the PSL register PSL_SERR_An */
 957 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
 958
 959 /*
 960  * Increments the number of attached contexts on an adapter.
 961  * In case an adapter_context_lock is taken the return -EBUSY.
 962  */
 963 int cxl_adapter_context_get(struct cxl *adapter);
 964
 965 /* Decrements the number of attached contexts on an adapter */
 966 void cxl_adapter_context_put(struct cxl *adapter);
 967
 968 /* If no active contexts then prevents contexts from being attached */
 969 int cxl_adapter_context_lock(struct cxl *adapter);
 970
 971 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
 972 void cxl_adapter_context_unlock(struct cxl *adapter);
 973
 974 #endif