drivers/pci/access.c

   1 #include <linux/delay.h>
   2 #include <linux/pci.h>
   3 #include <linux/module.h>
   4 #include <linux/sched.h>
   5 #include <linux/slab.h>
   6 #include <linux/ioport.h>
   7 #include <linux/wait.h>
   8
   9 #include "pci.h"
  10
  11 /*
  12  * This interrupt-safe spinlock protects all accesses to PCI
  13  * configuration space.
  14  */
  15
  16 DEFINE_RAW_SPINLOCK(pci_lock);
  17
  18 /*
  19  *  Wrappers for all PCI configuration access functions.  They just check
  20  *  alignment, do locking and call the low-level functions pointed to
  21  *  by pci_dev->ops.
  22  */
  23
  24 #define PCI_byte_BAD 0
  25 #define PCI_word_BAD (pos & 1)
  26 #define PCI_dword_BAD (pos & 3)
  27
  28 #define PCI_OP_READ(size, type, len) \
  29 int pci_bus_read_config_##size \
  30         (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
  31 {                                                                       \
  32         int res;                                                        \
  33         unsigned long flags;                                            \
  34         u32 data = 0;                                                   \
  35         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
  36         raw_spin_lock_irqsave(&pci_lock, flags);                        \
  37         res = bus->ops->read(bus, devfn, pos, len, &data);              \
  38         *value = (type)data;                                            \
  39         raw_spin_unlock_irqrestore(&pci_lock, flags);           \
  40         return res;                                                     \
  41 }
  42
  43 #define PCI_OP_WRITE(size, type, len) \
  44 int pci_bus_write_config_##size \
  45         (struct pci_bus *bus, unsigned int devfn, int pos, type value)  \
  46 {                                                                       \
  47         int res;                                                        \
  48         unsigned long flags;                                            \
  49         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
  50         raw_spin_lock_irqsave(&pci_lock, flags);                        \
  51         res = bus->ops->write(bus, devfn, pos, len, value);             \
  52         raw_spin_unlock_irqrestore(&pci_lock, flags);           \
  53         return res;                                                     \
  54 }
  55
  56 PCI_OP_READ(byte, u8, 1)
  57 PCI_OP_READ(word, u16, 2)
  58 PCI_OP_READ(dword, u32, 4)
  59 PCI_OP_WRITE(byte, u8, 1)
  60 PCI_OP_WRITE(word, u16, 2)
  61 PCI_OP_WRITE(dword, u32, 4)
  62
  63 EXPORT_SYMBOL(pci_bus_read_config_byte);
  64 EXPORT_SYMBOL(pci_bus_read_config_word);
  65 EXPORT_SYMBOL(pci_bus_read_config_dword);
  66 EXPORT_SYMBOL(pci_bus_write_config_byte);
  67 EXPORT_SYMBOL(pci_bus_write_config_word);
  68 EXPORT_SYMBOL(pci_bus_write_config_dword);
  69
  70 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
  71                             int where, int size, u32 *val)
  72 {
  73         void __iomem *addr;
  74
  75         addr = bus->ops->map_bus(bus, devfn, where);
  76         if (!addr) {
  77                 *val = ~0;
  78                 return PCIBIOS_DEVICE_NOT_FOUND;
  79         }
  80
  81         if (size == 1)
  82                 *val = readb(addr);
  83         else if (size == 2)
  84                 *val = readw(addr);
  85         else
  86                 *val = readl(addr);
  87
  88         return PCIBIOS_SUCCESSFUL;
  89 }
  90 EXPORT_SYMBOL_GPL(pci_generic_config_read);
  91
  92 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
  93                              int where, int size, u32 val)
  94 {
  95         void __iomem *addr;
  96
  97         addr = bus->ops->map_bus(bus, devfn, where);
  98         if (!addr)
  99                 return PCIBIOS_DEVICE_NOT_FOUND;
 100
 101         if (size == 1)
 102                 writeb(val, addr);
 103         else if (size == 2)
 104                 writew(val, addr);
 105         else
 106                 writel(val, addr);
 107
 108         return PCIBIOS_SUCCESSFUL;
 109 }
 110 EXPORT_SYMBOL_GPL(pci_generic_config_write);
 111
 112 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
 113                               int where, int size, u32 *val)
 114 {
 115         void __iomem *addr;
 116
 117         addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
 118         if (!addr) {
 119                 *val = ~0;
 120                 return PCIBIOS_DEVICE_NOT_FOUND;
 121         }
 122
 123         *val = readl(addr);
 124
 125         if (size <= 2)
 126                 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
 127
 128         return PCIBIOS_SUCCESSFUL;
 129 }
 130 EXPORT_SYMBOL_GPL(pci_generic_config_read32);
 131
 132 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
 133                                int where, int size, u32 val)
 134 {
 135         void __iomem *addr;
 136         u32 mask, tmp;
 137
 138         addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
 139         if (!addr)
 140                 return PCIBIOS_DEVICE_NOT_FOUND;
 141
 142         if (size == 4) {
 143                 writel(val, addr);
 144                 return PCIBIOS_SUCCESSFUL;
 145         } else {
 146                 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
 147         }
 148
 149         tmp = readl(addr) & mask;
 150         tmp |= val << ((where & 0x3) * 8);
 151         writel(tmp, addr);
 152
 153         return PCIBIOS_SUCCESSFUL;
 154 }
 155 EXPORT_SYMBOL_GPL(pci_generic_config_write32);
 156
 157 /**
 158  * pci_bus_set_ops - Set raw operations of pci bus
 159  * @bus:        pci bus struct
 160  * @ops:        new raw operations
 161  *
 162  * Return previous raw operations
 163  */
 164 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
 165 {
 166         struct pci_ops *old_ops;
 167         unsigned long flags;
 168
 169         raw_spin_lock_irqsave(&pci_lock, flags);
 170         old_ops = bus->ops;
 171         bus->ops = ops;
 172         raw_spin_unlock_irqrestore(&pci_lock, flags);
 173         return old_ops;
 174 }
 175 EXPORT_SYMBOL(pci_bus_set_ops);
 176
 177 /*
 178  * The following routines are to prevent the user from accessing PCI config
 179  * space when it's unsafe to do so.  Some devices require this during BIST and
 180  * we're required to prevent it during D-state transitions.
 181  *
 182  * We have a bit per device to indicate it's blocked and a global wait queue
 183  * for callers to sleep on until devices are unblocked.
 184  */
 185 static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
 186
 187 static noinline void pci_wait_cfg(struct pci_dev *dev)
 188         __must_hold(&pci_lock)
 189 {
 190         do {
 191                 raw_spin_unlock_irq(&pci_lock);
 192                 wait_event(pci_cfg_wait, !dev->block_cfg_access);
 193                 raw_spin_lock_irq(&pci_lock);
 194         } while (dev->block_cfg_access);
 195 }
 196
 197 /* Returns 0 on success, negative values indicate error. */
 198 #define PCI_USER_READ_CONFIG(size, type)                                        \
 199 int pci_user_read_config_##size                                         \
 200         (struct pci_dev *dev, int pos, type *val)                       \
 201 {                                                                       \
 202         int ret = PCIBIOS_SUCCESSFUL;                                   \
 203         u32 data = -1;                                                  \
 204         if (PCI_##size##_BAD)                                           \
 205                 return -EINVAL;                                         \
 206         raw_spin_lock_irq(&pci_lock);                           \
 207         if (unlikely(dev->block_cfg_access))                            \
 208                 pci_wait_cfg(dev);                                      \
 209         ret = dev->bus->ops->read(dev->bus, dev->devfn,                 \
 210                                         pos, sizeof(type), &data);      \
 211         raw_spin_unlock_irq(&pci_lock);                         \
 212         *val = (type)data;                                              \
 213         return pcibios_err_to_errno(ret);                               \
 214 }                                                                       \
 215 EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
 216
 217 /* Returns 0 on success, negative values indicate error. */
 218 #define PCI_USER_WRITE_CONFIG(size, type)                               \
 219 int pci_user_write_config_##size                                        \
 220         (struct pci_dev *dev, int pos, type val)                        \
 221 {                                                                       \
 222         int ret = PCIBIOS_SUCCESSFUL;                                   \
 223         if (PCI_##size##_BAD)                                           \
 224                 return -EINVAL;                                         \
 225         raw_spin_lock_irq(&pci_lock);                           \
 226         if (unlikely(dev->block_cfg_access))                            \
 227                 pci_wait_cfg(dev);                                      \
 228         ret = dev->bus->ops->write(dev->bus, dev->devfn,                \
 229                                         pos, sizeof(type), val);        \
 230         raw_spin_unlock_irq(&pci_lock);                         \
 231         return pcibios_err_to_errno(ret);                               \
 232 }                                                                       \
 233 EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
 234
 235 PCI_USER_READ_CONFIG(byte, u8)
 236 PCI_USER_READ_CONFIG(word, u16)
 237 PCI_USER_READ_CONFIG(dword, u32)
 238 PCI_USER_WRITE_CONFIG(byte, u8)
 239 PCI_USER_WRITE_CONFIG(word, u16)
 240 PCI_USER_WRITE_CONFIG(dword, u32)
 241
 242 /* VPD access through PCI 2.2+ VPD capability */
 243
 244 /**
 245  * pci_read_vpd - Read one entry from Vital Product Data
 246  * @dev:        pci device struct
 247  * @pos:        offset in vpd space
 248  * @count:      number of bytes to read
 249  * @buf:        pointer to where to store result
 250  */
 251 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
 252 {
 253         if (!dev->vpd || !dev->vpd->ops)
 254                 return -ENODEV;
 255         return dev->vpd->ops->read(dev, pos, count, buf);
 256 }
 257 EXPORT_SYMBOL(pci_read_vpd);
 258
 259 /**
 260  * pci_write_vpd - Write entry to Vital Product Data
 261  * @dev:        pci device struct
 262  * @pos:        offset in vpd space
 263  * @count:      number of bytes to write
 264  * @buf:        buffer containing write data
 265  */
 266 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
 267 {
 268         if (!dev->vpd || !dev->vpd->ops)
 269                 return -ENODEV;
 270         return dev->vpd->ops->write(dev, pos, count, buf);
 271 }
 272 EXPORT_SYMBOL(pci_write_vpd);
 273
 274 /**
 275  * pci_set_vpd_size - Set size of Vital Product Data space
 276  * @dev:        pci device struct
 277  * @len:        size of vpd space
 278  */
 279 int pci_set_vpd_size(struct pci_dev *dev, size_t len)
 280 {
 281         if (!dev->vpd || !dev->vpd->ops)
 282                 return -ENODEV;
 283         return dev->vpd->ops->set_size(dev, len);
 284 }
 285 EXPORT_SYMBOL(pci_set_vpd_size);
 286
 287 #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
 288
 289 /**
 290  * pci_vpd_size - determine actual size of Vital Product Data
 291  * @dev:        pci device struct
 292  * @old_size:   current assumed size, also maximum allowed size
 293  */
 294 static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
 295 {
 296         size_t off = 0;
 297         unsigned char header[1+2];      /* 1 byte tag, 2 bytes length */
 298
 299         while (off < old_size &&
 300                pci_read_vpd(dev, off, 1, header) == 1) {
 301                 unsigned char tag;
 302
 303                 if (header[0] & PCI_VPD_LRDT) {
 304                         /* Large Resource Data Type Tag */
 305                         tag = pci_vpd_lrdt_tag(header);
 306                         /* Only read length from known tag items */
 307                         if ((tag == PCI_VPD_LTIN_ID_STRING) ||
 308                             (tag == PCI_VPD_LTIN_RO_DATA) ||
 309                             (tag == PCI_VPD_LTIN_RW_DATA)) {
 310                                 if (pci_read_vpd(dev, off+1, 2,
 311                                                  &header[1]) != 2) {
 312                                         dev_warn(&dev->dev,
 313                                                  "invalid large VPD tag %02x size at offset %zu",
 314                                                  tag, off + 1);
 315                                         return 0;
 316                                 }
 317                                 off += PCI_VPD_LRDT_TAG_SIZE +
 318                                         pci_vpd_lrdt_size(header);
 319                         }
 320                 } else {
 321                         /* Short Resource Data Type Tag */
 322                         off += PCI_VPD_SRDT_TAG_SIZE +
 323                                 pci_vpd_srdt_size(header);
 324                         tag = pci_vpd_srdt_tag(header);
 325                 }
 326
 327                 if (tag == PCI_VPD_STIN_END)    /* End tag descriptor */
 328                         return off;
 329
 330                 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
 331                     (tag != PCI_VPD_LTIN_RO_DATA) &&
 332                     (tag != PCI_VPD_LTIN_RW_DATA)) {
 333                         dev_warn(&dev->dev,
 334                                  "invalid %s VPD tag %02x at offset %zu",
 335                                  (header[0] & PCI_VPD_LRDT) ? "large" : "short",
 336                                  tag, off);
 337                         return 0;
 338                 }
 339         }
 340         return 0;
 341 }
 342
 343 /*
 344  * Wait for last operation to complete.
 345  * This code has to spin since there is no other notification from the PCI
 346  * hardware. Since the VPD is often implemented by serial attachment to an
 347  * EEPROM, it may take many milliseconds to complete.
 348  *
 349  * Returns 0 on success, negative values indicate error.
 350  */
 351 static int pci_vpd_wait(struct pci_dev *dev)
 352 {
 353         struct pci_vpd *vpd = dev->vpd;
 354         unsigned long timeout = jiffies + msecs_to_jiffies(50);
 355         unsigned long max_sleep = 16;
 356         u16 status;
 357         int ret;
 358
 359         if (!vpd->busy)
 360                 return 0;
 361
 362         while (time_before(jiffies, timeout)) {
 363                 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 364                                                 &status);
 365                 if (ret < 0)
 366                         return ret;
 367
 368                 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
 369                         vpd->busy = 0;
 370                         return 0;
 371                 }
 372
 373                 if (fatal_signal_pending(current))
 374                         return -EINTR;
 375
 376                 usleep_range(10, max_sleep);
 377                 if (max_sleep < 1024)
 378                         max_sleep *= 2;
 379         }
 380
 381         dev_warn(&dev->dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
 382         return -ETIMEDOUT;
 383 }
 384
 385 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
 386                             void *arg)
 387 {
 388         struct pci_vpd *vpd = dev->vpd;
 389         int ret;
 390         loff_t end = pos + count;
 391         u8 *buf = arg;
 392
 393         if (pos < 0)
 394                 return -EINVAL;
 395
 396         if (!vpd->valid) {
 397                 vpd->valid = 1;
 398                 vpd->len = pci_vpd_size(dev, vpd->len);
 399         }
 400
 401         if (vpd->len == 0)
 402                 return -EIO;
 403
 404         if (pos > vpd->len)
 405                 return 0;
 406
 407         if (end > vpd->len) {
 408                 end = vpd->len;
 409                 count = end - pos;
 410         }
 411
 412         if (mutex_lock_killable(&vpd->lock))
 413                 return -EINTR;
 414
 415         ret = pci_vpd_wait(dev);
 416         if (ret < 0)
 417                 goto out;
 418
 419         while (pos < end) {
 420                 u32 val;
 421                 unsigned int i, skip;
 422
 423                 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 424                                                  pos & ~3);
 425                 if (ret < 0)
 426                         break;
 427                 vpd->busy = 1;
 428                 vpd->flag = PCI_VPD_ADDR_F;
 429                 ret = pci_vpd_wait(dev);
 430                 if (ret < 0)
 431                         break;
 432
 433                 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
 434                 if (ret < 0)
 435                         break;
 436
 437                 skip = pos & 3;
 438                 for (i = 0;  i < sizeof(u32); i++) {
 439                         if (i >= skip) {
 440                                 *buf++ = val;
 441                                 if (++pos == end)
 442                                         break;
 443                         }
 444                         val >>= 8;
 445                 }
 446         }
 447 out:
 448         mutex_unlock(&vpd->lock);
 449         return ret ? ret : count;
 450 }
 451
 452 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
 453                              const void *arg)
 454 {
 455         struct pci_vpd *vpd = dev->vpd;
 456         const u8 *buf = arg;
 457         loff_t end = pos + count;
 458         int ret = 0;
 459
 460         if (pos < 0 || (pos & 3) || (count & 3))
 461                 return -EINVAL;
 462
 463         if (!vpd->valid) {
 464                 vpd->valid = 1;
 465                 vpd->len = pci_vpd_size(dev, vpd->len);
 466         }
 467
 468         if (vpd->len == 0)
 469                 return -EIO;
 470
 471         if (end > vpd->len)
 472                 return -EINVAL;
 473
 474         if (mutex_lock_killable(&vpd->lock))
 475                 return -EINTR;
 476
 477         ret = pci_vpd_wait(dev);
 478         if (ret < 0)
 479                 goto out;
 480
 481         while (pos < end) {
 482                 u32 val;
 483
 484                 val = *buf++;
 485                 val |= *buf++ << 8;
 486                 val |= *buf++ << 16;
 487                 val |= *buf++ << 24;
 488
 489                 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
 490                 if (ret < 0)
 491                         break;
 492                 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
 493                                                  pos | PCI_VPD_ADDR_F);
 494                 if (ret < 0)
 495                         break;
 496
 497                 vpd->busy = 1;
 498                 vpd->flag = 0;
 499                 ret = pci_vpd_wait(dev);
 500                 if (ret < 0)
 501                         break;
 502
 503                 pos += sizeof(u32);
 504         }
 505 out:
 506         mutex_unlock(&vpd->lock);
 507         return ret ? ret : count;
 508 }
 509
 510 static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
 511 {
 512         struct pci_vpd *vpd = dev->vpd;
 513
 514         if (len == 0 || len > PCI_VPD_MAX_SIZE)
 515                 return -EIO;
 516
 517         vpd->valid = 1;
 518         vpd->len = len;
 519
 520         return 0;
 521 }
 522
 523 static const struct pci_vpd_ops pci_vpd_ops = {
 524         .read = pci_vpd_read,
 525         .write = pci_vpd_write,
 526         .set_size = pci_vpd_set_size,
 527 };
 528
 529 static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
 530                                void *arg)
 531 {
 532         struct pci_dev *tdev = pci_get_slot(dev->bus,
 533                                             PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 534         ssize_t ret;
 535
 536         if (!tdev)
 537                 return -ENODEV;
 538
 539         ret = pci_read_vpd(tdev, pos, count, arg);
 540         pci_dev_put(tdev);
 541         return ret;
 542 }
 543
 544 static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
 545                                 const void *arg)
 546 {
 547         struct pci_dev *tdev = pci_get_slot(dev->bus,
 548                                             PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 549         ssize_t ret;
 550
 551         if (!tdev)
 552                 return -ENODEV;
 553
 554         ret = pci_write_vpd(tdev, pos, count, arg);
 555         pci_dev_put(tdev);
 556         return ret;
 557 }
 558
 559 static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
 560 {
 561         struct pci_dev *tdev = pci_get_slot(dev->bus,
 562                                             PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
 563         int ret;
 564
 565         if (!tdev)
 566                 return -ENODEV;
 567
 568         ret = pci_set_vpd_size(tdev, len);
 569         pci_dev_put(tdev);
 570         return ret;
 571 }
 572
 573 static const struct pci_vpd_ops pci_vpd_f0_ops = {
 574         .read = pci_vpd_f0_read,
 575         .write = pci_vpd_f0_write,
 576         .set_size = pci_vpd_f0_set_size,
 577 };
 578
 579 int pci_vpd_init(struct pci_dev *dev)
 580 {
 581         struct pci_vpd *vpd;
 582         u8 cap;
 583
 584         cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
 585         if (!cap)
 586                 return -ENODEV;
 587
 588         vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
 589         if (!vpd)
 590                 return -ENOMEM;
 591
 592         vpd->len = PCI_VPD_MAX_SIZE;
 593         if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
 594                 vpd->ops = &pci_vpd_f0_ops;
 595         else
 596                 vpd->ops = &pci_vpd_ops;
 597         mutex_init(&vpd->lock);
 598         vpd->cap = cap;
 599         vpd->busy = 0;
 600         vpd->valid = 0;
 601         dev->vpd = vpd;
 602         return 0;
 603 }
 604
 605 void pci_vpd_release(struct pci_dev *dev)
 606 {
 607         kfree(dev->vpd);
 608 }
 609
 610 /**
 611  * pci_cfg_access_lock - Lock PCI config reads/writes
 612  * @dev:        pci device struct
 613  *
 614  * When access is locked, any userspace reads or writes to config
 615  * space and concurrent lock requests will sleep until access is
 616  * allowed via pci_cfg_access_unlocked again.
 617  */
 618 void pci_cfg_access_lock(struct pci_dev *dev)
 619 {
 620         might_sleep();
 621
 622         raw_spin_lock_irq(&pci_lock);
 623         if (dev->block_cfg_access)
 624                 pci_wait_cfg(dev);
 625         dev->block_cfg_access = 1;
 626         raw_spin_unlock_irq(&pci_lock);
 627 }
 628 EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
 629
 630 /**
 631  * pci_cfg_access_trylock - try to lock PCI config reads/writes
 632  * @dev:        pci device struct
 633  *
 634  * Same as pci_cfg_access_lock, but will return 0 if access is
 635  * already locked, 1 otherwise. This function can be used from
 636  * atomic contexts.
 637  */
 638 bool pci_cfg_access_trylock(struct pci_dev *dev)
 639 {
 640         unsigned long flags;
 641         bool locked = true;
 642
 643         raw_spin_lock_irqsave(&pci_lock, flags);
 644         if (dev->block_cfg_access)
 645                 locked = false;
 646         else
 647                 dev->block_cfg_access = 1;
 648         raw_spin_unlock_irqrestore(&pci_lock, flags);
 649
 650         return locked;
 651 }
 652 EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
 653
 654 /**
 655  * pci_cfg_access_unlock - Unlock PCI config reads/writes
 656  * @dev:        pci device struct
 657  *
 658  * This function allows PCI config accesses to resume.
 659  */
 660 void pci_cfg_access_unlock(struct pci_dev *dev)
 661 {
 662         unsigned long flags;
 663
 664         raw_spin_lock_irqsave(&pci_lock, flags);
 665
 666         /* This indicates a problem in the caller, but we don't need
 667          * to kill them, unlike a double-block above. */
 668         WARN_ON(!dev->block_cfg_access);
 669
 670         dev->block_cfg_access = 0;
 671         raw_spin_unlock_irqrestore(&pci_lock, flags);
 672
 673         wake_up_all(&pci_cfg_wait);
 674 }
 675 EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
 676
 677 static inline int pcie_cap_version(const struct pci_dev *dev)
 678 {
 679         return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
 680 }
 681
 682 static bool pcie_downstream_port(const struct pci_dev *dev)
 683 {
 684         int type = pci_pcie_type(dev);
 685
 686         return type == PCI_EXP_TYPE_ROOT_PORT ||
 687                type == PCI_EXP_TYPE_DOWNSTREAM;
 688 }
 689
 690 bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
 691 {
 692         int type = pci_pcie_type(dev);
 693
 694         return type == PCI_EXP_TYPE_ENDPOINT ||
 695                type == PCI_EXP_TYPE_LEG_END ||
 696                type == PCI_EXP_TYPE_ROOT_PORT ||
 697                type == PCI_EXP_TYPE_UPSTREAM ||
 698                type == PCI_EXP_TYPE_DOWNSTREAM ||
 699                type == PCI_EXP_TYPE_PCI_BRIDGE ||
 700                type == PCI_EXP_TYPE_PCIE_BRIDGE;
 701 }
 702
 703 static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
 704 {
 705         return pcie_downstream_port(dev) &&
 706                pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
 707 }
 708
 709 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
 710 {
 711         int type = pci_pcie_type(dev);
 712
 713         return type == PCI_EXP_TYPE_ROOT_PORT ||
 714                type == PCI_EXP_TYPE_RC_EC;
 715 }
 716
 717 static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
 718 {
 719         if (!pci_is_pcie(dev))
 720                 return false;
 721
 722         switch (pos) {
 723         case PCI_EXP_FLAGS:
 724                 return true;
 725         case PCI_EXP_DEVCAP:
 726         case PCI_EXP_DEVCTL:
 727         case PCI_EXP_DEVSTA:
 728                 return true;
 729         case PCI_EXP_LNKCAP:
 730         case PCI_EXP_LNKCTL:
 731         case PCI_EXP_LNKSTA:
 732                 return pcie_cap_has_lnkctl(dev);
 733         case PCI_EXP_SLTCAP:
 734         case PCI_EXP_SLTCTL:
 735         case PCI_EXP_SLTSTA:
 736                 return pcie_cap_has_sltctl(dev);
 737         case PCI_EXP_RTCTL:
 738         case PCI_EXP_RTCAP:
 739         case PCI_EXP_RTSTA:
 740                 return pcie_cap_has_rtctl(dev);
 741         case PCI_EXP_DEVCAP2:
 742         case PCI_EXP_DEVCTL2:
 743         case PCI_EXP_LNKCAP2:
 744         case PCI_EXP_LNKCTL2:
 745         case PCI_EXP_LNKSTA2:
 746                 return pcie_cap_version(dev) > 1;
 747         default:
 748                 return false;
 749         }
 750 }
 751
 752 /*
 753  * Note that these accessor functions are only for the "PCI Express
 754  * Capability" (see PCIe spec r3.0, sec 7.8).  They do not apply to the
 755  * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
 756  */
 757 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
 758 {
 759         int ret;
 760
 761         *val = 0;
 762         if (pos & 1)
 763                 return -EINVAL;
 764
 765         if (pcie_capability_reg_implemented(dev, pos)) {
 766                 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
 767                 /*
 768                  * Reset *val to 0 if pci_read_config_word() fails, it may
 769                  * have been written as 0xFFFF if hardware error happens
 770                  * during pci_read_config_word().
 771                  */
 772                 if (ret)
 773                         *val = 0;
 774                 return ret;
 775         }
 776
 777         /*
 778          * For Functions that do not implement the Slot Capabilities,
 779          * Slot Status, and Slot Control registers, these spaces must
 780          * be hardwired to 0b, with the exception of the Presence Detect
 781          * State bit in the Slot Status register of Downstream Ports,
 782          * which must be hardwired to 1b.  (PCIe Base Spec 3.0, sec 7.8)
 783          */
 784         if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
 785             pos == PCI_EXP_SLTSTA)
 786                 *val = PCI_EXP_SLTSTA_PDS;
 787
 788         return 0;
 789 }
 790 EXPORT_SYMBOL(pcie_capability_read_word);
 791
 792 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
 793 {
 794         int ret;
 795
 796         *val = 0;
 797         if (pos & 3)
 798                 return -EINVAL;
 799
 800         if (pcie_capability_reg_implemented(dev, pos)) {
 801                 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
 802                 /*
 803                  * Reset *val to 0 if pci_read_config_dword() fails, it may
 804                  * have been written as 0xFFFFFFFF if hardware error happens
 805                  * during pci_read_config_dword().
 806                  */
 807                 if (ret)
 808                         *val = 0;
 809                 return ret;
 810         }
 811
 812         if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
 813             pos == PCI_EXP_SLTSTA)
 814                 *val = PCI_EXP_SLTSTA_PDS;
 815
 816         return 0;
 817 }
 818 EXPORT_SYMBOL(pcie_capability_read_dword);
 819
 820 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
 821 {
 822         if (pos & 1)
 823                 return -EINVAL;
 824
 825         if (!pcie_capability_reg_implemented(dev, pos))
 826                 return 0;
 827
 828         return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
 829 }
 830 EXPORT_SYMBOL(pcie_capability_write_word);
 831
 832 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
 833 {
 834         if (pos & 3)
 835                 return -EINVAL;
 836
 837         if (!pcie_capability_reg_implemented(dev, pos))
 838                 return 0;
 839
 840         return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
 841 }
 842 EXPORT_SYMBOL(pcie_capability_write_dword);
 843
 844 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
 845                                        u16 clear, u16 set)
 846 {
 847         int ret;
 848         u16 val;
 849
 850         ret = pcie_capability_read_word(dev, pos, &val);
 851         if (!ret) {
 852                 val &= ~clear;
 853                 val |= set;
 854                 ret = pcie_capability_write_word(dev, pos, val);
 855         }
 856
 857         return ret;
 858 }
 859 EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
 860
 861 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
 862                                         u32 clear, u32 set)
 863 {
 864         int ret;
 865         u32 val;
 866
 867         ret = pcie_capability_read_dword(dev, pos, &val);
 868         if (!ret) {
 869                 val &= ~clear;
 870                 val |= set;
 871                 ret = pcie_capability_write_dword(dev, pos, val);
 872         }
 873
 874         return ret;
 875 }
 876 EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);