drivers/pci/host/pci-keystone.c

   1 /*
   2  * PCIe host controller driver for Texas Instruments Keystone SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   5  *              http://www.ti.com
   6  *
   7  * Author: Murali Karicheri <m-karicheri2@ti.com>
   8  * Implementation based on pci-exynos.c and pcie-designware.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/init.h>
  21 #include <linux/msi.h>
  22 #include <linux/of_irq.h>
  23 #include <linux/of.h>
  24 #include <linux/of_pci.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/phy/phy.h>
  27 #include <linux/resource.h>
  28 #include <linux/signal.h>
  29
  30 #include "pcie-designware.h"
  31 #include "pci-keystone.h"
  32
  33 #define DRIVER_NAME     "keystone-pcie"
  34
  35 /* driver specific constants */
  36 #define MAX_MSI_HOST_IRQS               8
  37 #define MAX_LEGACY_HOST_IRQS            4
  38
  39 /* DEV_STAT_CTRL */
  40 #define PCIE_CAP_BASE           0x70
  41
  42 /* PCIE controller device IDs */
  43 #define PCIE_RC_K2HK            0xb008
  44 #define PCIE_RC_K2E             0xb009
  45 #define PCIE_RC_K2L             0xb00a
  46 #define PCIE_RC_K2G             0xb00b
  47
  48 #define to_keystone_pcie(x)     container_of(x, struct keystone_pcie, pp)
  49
  50 static void quirk_limit_mrrs(struct pci_dev *dev)
  51 {
  52         struct pci_bus *bus = dev->bus;
  53         struct pci_dev *bridge = bus->self;
  54         static const struct pci_device_id rc_pci_devids[] = {
  55                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
  56                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  57                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
  58                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  59                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
  60                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  61                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2G),
  62                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  63                 { 0, },
  64         };
  65
  66         if (pci_is_root_bus(bus))
  67                 return;
  68
  69         /* look for the host bridge */
  70         while (!pci_is_root_bus(bus)) {
  71                 bridge = bus->self;
  72                 bus = bus->parent;
  73         }
  74
  75         if (bridge) {
  76                 /*
  77                  * Keystone PCI controller has a h/w limitation of
  78                  * 256 bytes maximum read request size.  It can't handle
  79                  * anything higher than this.  So force this limit on
  80                  * all downstream devices.
  81                  */
  82                 if (pci_match_id(rc_pci_devids, bridge)) {
  83                         if (pcie_get_readrq(dev) > 256) {
  84                                 dev_info(&dev->dev, "limiting MRRS to 256\n");
  85                                 pcie_set_readrq(dev, 256);
  86                         }
  87                 }
  88         }
  89 }
  90 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
  91
  92 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
  93 {
  94         struct pcie_port *pp = &ks_pcie->pp;
  95         struct device *dev = pp->dev;
  96         unsigned int retries;
  97
  98         dw_pcie_setup_rc(pp);
  99
 100         if (dw_pcie_link_up(pp)) {
 101                 dev_err(dev, "Link already up\n");
 102                 return 0;
 103         }
 104
 105         /* check if the link is up or not */
 106         for (retries = 0; retries < 5; retries++) {
 107                 ks_dw_pcie_initiate_link_train(ks_pcie);
 108                 if (!dw_pcie_wait_for_link(pp))
 109                         return 0;
 110         }
 111
 112         dev_err(dev, "phy link never came up\n");
 113         return -ETIMEDOUT;
 114 }
 115
 116 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
 117 {
 118         unsigned int irq = irq_desc_get_irq(desc);
 119         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 120         u32 offset = irq - ks_pcie->msi_host_irqs[0];
 121         struct pcie_port *pp = &ks_pcie->pp;
 122         struct device *dev = pp->dev;
 123         struct irq_chip *chip = irq_desc_get_chip(desc);
 124
 125         dev_dbg(dev, "%s, irq %d\n", __func__, irq);
 126
 127         /*
 128          * The chained irq handler installation would have replaced normal
 129          * interrupt driver handler so we need to take care of mask/unmask and
 130          * ack operation.
 131          */
 132         chained_irq_enter(chip, desc);
 133         ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
 134         chained_irq_exit(chip, desc);
 135 }
 136
 137 /**
 138  * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
 139  * @irq: IRQ line for legacy interrupts
 140  * @desc: Pointer to irq descriptor
 141  *
 142  * Traverse through pending legacy interrupts and invoke handler for each. Also
 143  * takes care of interrupt controller level mask/ack operation.
 144  */
 145 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
 146 {
 147         unsigned int irq = irq_desc_get_irq(desc);
 148         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 149         struct pcie_port *pp = &ks_pcie->pp;
 150         struct device *dev = pp->dev;
 151         u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
 152         struct irq_chip *chip = irq_desc_get_chip(desc);
 153
 154         dev_dbg(dev, ": Handling legacy irq %d\n", irq);
 155
 156         /*
 157          * The chained irq handler installation would have replaced normal
 158          * interrupt driver handler so we need to take care of mask/unmask and
 159          * ack operation.
 160          */
 161         chained_irq_enter(chip, desc);
 162         ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
 163         chained_irq_exit(chip, desc);
 164 }
 165
 166 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
 167                                            char *controller, int *num_irqs)
 168 {
 169         int temp, max_host_irqs, legacy = 1, *host_irqs;
 170         struct device *dev = ks_pcie->pp.dev;
 171         struct device_node *np_pcie = dev->of_node, **np_temp;
 172
 173         if (!strcmp(controller, "msi-interrupt-controller"))
 174                 legacy = 0;
 175
 176         if (legacy) {
 177                 np_temp = &ks_pcie->legacy_intc_np;
 178                 max_host_irqs = MAX_LEGACY_HOST_IRQS;
 179                 host_irqs = &ks_pcie->legacy_host_irqs[0];
 180         } else {
 181                 np_temp = &ks_pcie->msi_intc_np;
 182                 max_host_irqs = MAX_MSI_HOST_IRQS;
 183                 host_irqs =  &ks_pcie->msi_host_irqs[0];
 184         }
 185
 186         /* interrupt controller is in a child node */
 187         *np_temp = of_get_child_by_name(np_pcie, controller);
 188         if (!(*np_temp)) {
 189                 dev_err(dev, "Node for %s is absent\n", controller);
 190                 return -EINVAL;
 191         }
 192
 193         temp = of_irq_count(*np_temp);
 194         if (!temp) {
 195                 dev_err(dev, "No IRQ entries in %s\n", controller);
 196                 of_node_put(*np_temp);
 197                 return -EINVAL;
 198         }
 199
 200         if (temp > max_host_irqs)
 201                 dev_warn(dev, "Too many %s interrupts defined %u\n",
 202                         (legacy ? "legacy" : "MSI"), temp);
 203
 204         /*
 205          * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
 206          * 7 (MSI)
 207          */
 208         for (temp = 0; temp < max_host_irqs; temp++) {
 209                 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
 210                 if (!host_irqs[temp])
 211                         break;
 212         }
 213
 214         of_node_put(*np_temp);
 215
 216         if (temp) {
 217                 *num_irqs = temp;
 218                 return 0;
 219         }
 220
 221         return -EINVAL;
 222 }
 223
 224 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
 225 {
 226         int i;
 227
 228         /* Legacy IRQ */
 229         for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
 230                 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
 231                                                  ks_pcie_legacy_irq_handler,
 232                                                  ks_pcie);
 233         }
 234         ks_dw_pcie_enable_legacy_irqs(ks_pcie);
 235
 236         /* MSI IRQ */
 237         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 238                 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
 239                         irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
 240                                                          ks_pcie_msi_irq_handler,
 241                                                          ks_pcie);
 242                 }
 243         }
 244
 245         if (ks_pcie->error_irq > 0)
 246                 ks_dw_pcie_enable_error_irq(ks_pcie);
 247 }
 248
 249 /*
 250  * When a PCI device does not exist during config cycles, keystone host gets a
 251  * bus error instead of returning 0xffffffff. This handler always returns 0
 252  * for this kind of faults.
 253  */
 254 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
 255                                 struct pt_regs *regs)
 256 {
 257         unsigned long instr = *(unsigned long *) instruction_pointer(regs);
 258
 259         if ((instr & 0x0e100090) == 0x00100090) {
 260                 int reg = (instr >> 12) & 15;
 261
 262                 regs->uregs[reg] = -1;
 263                 regs->ARM_pc += 4;
 264         }
 265
 266         return 0;
 267 }
 268
 269 static void __init ks_pcie_host_init(struct pcie_port *pp)
 270 {
 271         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 272         u32 val;
 273
 274         ks_pcie_establish_link(ks_pcie);
 275         ks_dw_pcie_setup_rc_app_regs(ks_pcie);
 276         ks_pcie_setup_interrupts(ks_pcie);
 277         writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
 278                         pp->dbi_base + PCI_IO_BASE);
 279
 280         /* update the Vendor ID */
 281         writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
 282
 283         /* update the DEV_STAT_CTRL to publish right mrrs */
 284         val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 285         val &= ~PCI_EXP_DEVCTL_READRQ;
 286         /* set the mrrs to 256 bytes */
 287         val |= BIT(12);
 288         writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 289
 290         /*
 291          * PCIe access errors that result into OCP errors are caught by ARM as
 292          * "External aborts"
 293          */
 294         hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
 295                         "Asynchronous external abort");
 296 }
 297
 298 static struct pcie_host_ops keystone_pcie_host_ops = {
 299         .rd_other_conf = ks_dw_pcie_rd_other_conf,
 300         .wr_other_conf = ks_dw_pcie_wr_other_conf,
 301         .link_up = ks_dw_pcie_link_up,
 302         .host_init = ks_pcie_host_init,
 303         .msi_set_irq = ks_dw_pcie_msi_set_irq,
 304         .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
 305         .get_msi_addr = ks_dw_pcie_get_msi_addr,
 306         .msi_host_init = ks_dw_pcie_msi_host_init,
 307         .scan_bus = ks_dw_pcie_v3_65_scan_bus,
 308 };
 309
 310 static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
 311 {
 312         struct keystone_pcie *ks_pcie = priv;
 313
 314         return ks_dw_pcie_handle_error_irq(ks_pcie);
 315 }
 316
 317 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
 318                          struct platform_device *pdev)
 319 {
 320         struct pcie_port *pp = &ks_pcie->pp;
 321         struct device *dev = pp->dev;
 322         int ret;
 323
 324         ret = ks_pcie_get_irq_controller_info(ks_pcie,
 325                                         "legacy-interrupt-controller",
 326                                         &ks_pcie->num_legacy_host_irqs);
 327         if (ret)
 328                 return ret;
 329
 330         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 331                 ret = ks_pcie_get_irq_controller_info(ks_pcie,
 332                                                 "msi-interrupt-controller",
 333                                                 &ks_pcie->num_msi_host_irqs);
 334                 if (ret)
 335                         return ret;
 336         }
 337
 338         /*
 339          * Index 0 is the platform interrupt for error interrupt
 340          * from RC.  This is optional.
 341          */
 342         ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
 343         if (ks_pcie->error_irq <= 0)
 344                 dev_info(dev, "no error IRQ defined\n");
 345         else {
 346                 ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
 347                                   IRQF_SHARED, "pcie-error-irq", ks_pcie);
 348                 if (ret < 0) {
 349                         dev_err(dev, "failed to request error IRQ %d\n",
 350                                 ks_pcie->error_irq);
 351                         return ret;
 352                 }
 353         }
 354
 355         pp->root_bus_nr = -1;
 356         pp->ops = &keystone_pcie_host_ops;
 357         ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
 358         if (ret) {
 359                 dev_err(dev, "failed to initialize host\n");
 360                 return ret;
 361         }
 362
 363         return 0;
 364 }
 365
 366 static const struct of_device_id ks_pcie_of_match[] = {
 367         {
 368                 .type = "pci",
 369                 .compatible = "ti,keystone-pcie",
 370         },
 371         { },
 372 };
 373
 374 static int __exit ks_pcie_remove(struct platform_device *pdev)
 375 {
 376         struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
 377
 378         clk_disable_unprepare(ks_pcie->clk);
 379
 380         return 0;
 381 }
 382
 383 static int __init ks_pcie_probe(struct platform_device *pdev)
 384 {
 385         struct device *dev = &pdev->dev;
 386         struct keystone_pcie *ks_pcie;
 387         struct pcie_port *pp;
 388         struct resource *res;
 389         void __iomem *reg_p;
 390         struct phy *phy;
 391         int ret;
 392
 393         ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
 394         if (!ks_pcie)
 395                 return -ENOMEM;
 396
 397         pp = &ks_pcie->pp;
 398         pp->dev = dev;
 399
 400         /* initialize SerDes Phy if present */
 401         phy = devm_phy_get(dev, "pcie-phy");
 402         if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
 403                 return PTR_ERR(phy);
 404
 405         if (!IS_ERR_OR_NULL(phy)) {
 406                 ret = phy_init(phy);
 407                 if (ret < 0)
 408                         return ret;
 409         }
 410
 411         /* index 2 is to read PCI DEVICE_ID */
 412         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 413         reg_p = devm_ioremap_resource(dev, res);
 414         if (IS_ERR(reg_p))
 415                 return PTR_ERR(reg_p);
 416         ks_pcie->device_id = readl(reg_p) >> 16;
 417         devm_iounmap(dev, reg_p);
 418         devm_release_mem_region(dev, res->start, resource_size(res));
 419
 420         ks_pcie->np = dev->of_node;
 421         platform_set_drvdata(pdev, ks_pcie);
 422         ks_pcie->clk = devm_clk_get(dev, "pcie");
 423         if (IS_ERR(ks_pcie->clk)) {
 424                 dev_err(dev, "Failed to get pcie rc clock\n");
 425                 return PTR_ERR(ks_pcie->clk);
 426         }
 427         ret = clk_prepare_enable(ks_pcie->clk);
 428         if (ret)
 429                 return ret;
 430
 431         ret = ks_add_pcie_port(ks_pcie, pdev);
 432         if (ret < 0)
 433                 goto fail_clk;
 434
 435         return 0;
 436 fail_clk:
 437         clk_disable_unprepare(ks_pcie->clk);
 438
 439         return ret;
 440 }
 441
 442 static struct platform_driver ks_pcie_driver __refdata = {
 443         .probe  = ks_pcie_probe,
 444         .remove = __exit_p(ks_pcie_remove),
 445         .driver = {
 446                 .name   = "keystone-pcie",
 447                 .of_match_table = of_match_ptr(ks_pcie_of_match),
 448         },
 449 };
 450 builtin_platform_driver(ks_pcie_driver);