drivers/phy/phy-qcom-ufs.c

   1 /*
   2  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  */
  14
  15 #include "phy-qcom-ufs-i.h"
  16
  17 #define MAX_PROP_NAME              32
  18 #define VDDA_PHY_MIN_UV            1000000
  19 #define VDDA_PHY_MAX_UV            1000000
  20 #define VDDA_PLL_MIN_UV            1800000
  21 #define VDDA_PLL_MAX_UV            1800000
  22 #define VDDP_REF_CLK_MIN_UV        1200000
  23 #define VDDP_REF_CLK_MAX_UV        1200000
  24
  25 static int __ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
  26                                     const char *, bool);
  27 static int ufs_qcom_phy_init_vreg(struct phy *, struct ufs_qcom_phy_vreg *,
  28                                   const char *);
  29 static int ufs_qcom_phy_base_init(struct platform_device *pdev,
  30                                   struct ufs_qcom_phy *phy_common);
  31
  32 int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  33                            struct ufs_qcom_phy_calibration *tbl_A,
  34                            int tbl_size_A,
  35                            struct ufs_qcom_phy_calibration *tbl_B,
  36                            int tbl_size_B, bool is_rate_B)
  37 {
  38         int i;
  39         int ret = 0;
  40
  41         if (!tbl_A) {
  42                 dev_err(ufs_qcom_phy->dev, "%s: tbl_A is NULL", __func__);
  43                 ret = EINVAL;
  44                 goto out;
  45         }
  46
  47         for (i = 0; i < tbl_size_A; i++)
  48                 writel_relaxed(tbl_A[i].cfg_value,
  49                                ufs_qcom_phy->mmio + tbl_A[i].reg_offset);
  50
  51         /*
  52          * In case we would like to work in rate B, we need
  53          * to override a registers that were configured in rate A table
  54          * with registers of rate B table.
  55          * table.
  56          */
  57         if (is_rate_B) {
  58                 if (!tbl_B) {
  59                         dev_err(ufs_qcom_phy->dev, "%s: tbl_B is NULL",
  60                                 __func__);
  61                         ret = EINVAL;
  62                         goto out;
  63                 }
  64
  65                 for (i = 0; i < tbl_size_B; i++)
  66                         writel_relaxed(tbl_B[i].cfg_value,
  67                                 ufs_qcom_phy->mmio + tbl_B[i].reg_offset);
  68         }
  69
  70         /* flush buffered writes */
  71         mb();
  72
  73 out:
  74         return ret;
  75 }
  76 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate);
  77
  78 struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
  79                                 struct ufs_qcom_phy *common_cfg,
  80                                 const struct phy_ops *ufs_qcom_phy_gen_ops,
  81                                 struct ufs_qcom_phy_specific_ops *phy_spec_ops)
  82 {
  83         int err;
  84         struct device *dev = &pdev->dev;
  85         struct phy *generic_phy = NULL;
  86         struct phy_provider *phy_provider;
  87
  88         err = ufs_qcom_phy_base_init(pdev, common_cfg);
  89         if (err) {
  90                 dev_err(dev, "%s: phy base init failed %d\n", __func__, err);
  91                 goto out;
  92         }
  93
  94         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
  95         if (IS_ERR(phy_provider)) {
  96                 err = PTR_ERR(phy_provider);
  97                 dev_err(dev, "%s: failed to register phy %d\n", __func__, err);
  98                 goto out;
  99         }
 100
 101         generic_phy = devm_phy_create(dev, NULL, ufs_qcom_phy_gen_ops);
 102         if (IS_ERR(generic_phy)) {
 103                 err =  PTR_ERR(generic_phy);
 104                 dev_err(dev, "%s: failed to create phy %d\n", __func__, err);
 105                 generic_phy = NULL;
 106                 goto out;
 107         }
 108
 109         common_cfg->phy_spec_ops = phy_spec_ops;
 110         common_cfg->dev = dev;
 111
 112 out:
 113         return generic_phy;
 114 }
 115 EXPORT_SYMBOL_GPL(ufs_qcom_phy_generic_probe);
 116
 117 /*
 118  * This assumes the embedded phy structure inside generic_phy is of type
 119  * struct ufs_qcom_phy. In order to function properly it's crucial
 120  * to keep the embedded struct "struct ufs_qcom_phy common_cfg"
 121  * as the first inside generic_phy.
 122  */
 123 struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy)
 124 {
 125         return (struct ufs_qcom_phy *)phy_get_drvdata(generic_phy);
 126 }
 127 EXPORT_SYMBOL_GPL(get_ufs_qcom_phy);
 128
 129 static
 130 int ufs_qcom_phy_base_init(struct platform_device *pdev,
 131                            struct ufs_qcom_phy *phy_common)
 132 {
 133         struct device *dev = &pdev->dev;
 134         struct resource *res;
 135         int err = 0;
 136
 137         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_mem");
 138         phy_common->mmio = devm_ioremap_resource(dev, res);
 139         if (IS_ERR((void const *)phy_common->mmio)) {
 140                 err = PTR_ERR((void const *)phy_common->mmio);
 141                 phy_common->mmio = NULL;
 142                 dev_err(dev, "%s: ioremap for phy_mem resource failed %d\n",
 143                         __func__, err);
 144                 return err;
 145         }
 146
 147         /* "dev_ref_clk_ctrl_mem" is optional resource */
 148         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 149                                            "dev_ref_clk_ctrl_mem");
 150         phy_common->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
 151         if (IS_ERR((void const *)phy_common->dev_ref_clk_ctrl_mmio))
 152                 phy_common->dev_ref_clk_ctrl_mmio = NULL;
 153
 154         return 0;
 155 }
 156
 157 static int __ufs_qcom_phy_clk_get(struct phy *phy,
 158                          const char *name, struct clk **clk_out, bool err_print)
 159 {
 160         struct clk *clk;
 161         int err = 0;
 162         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
 163         struct device *dev = ufs_qcom_phy->dev;
 164
 165         clk = devm_clk_get(dev, name);
 166         if (IS_ERR(clk)) {
 167                 err = PTR_ERR(clk);
 168                 if (err_print)
 169                         dev_err(dev, "failed to get %s err %d", name, err);
 170         } else {
 171                 *clk_out = clk;
 172         }
 173
 174         return err;
 175 }
 176
 177 static
 178 int ufs_qcom_phy_clk_get(struct phy *phy,
 179                          const char *name, struct clk **clk_out)
 180 {
 181         return __ufs_qcom_phy_clk_get(phy, name, clk_out, true);
 182 }
 183
 184 int
 185 ufs_qcom_phy_init_clks(struct phy *generic_phy,
 186                        struct ufs_qcom_phy *phy_common)
 187 {
 188         int err;
 189
 190         err = ufs_qcom_phy_clk_get(generic_phy, "tx_iface_clk",
 191                                    &phy_common->tx_iface_clk);
 192         if (err)
 193                 goto out;
 194
 195         err = ufs_qcom_phy_clk_get(generic_phy, "rx_iface_clk",
 196                                    &phy_common->rx_iface_clk);
 197         if (err)
 198                 goto out;
 199
 200         err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk_src",
 201                                    &phy_common->ref_clk_src);
 202         if (err)
 203                 goto out;
 204
 205         /*
 206          * "ref_clk_parent" is optional hence don't abort init if it's not
 207          * found.
 208          */
 209         __ufs_qcom_phy_clk_get(generic_phy, "ref_clk_parent",
 210                                    &phy_common->ref_clk_parent, false);
 211
 212         err = ufs_qcom_phy_clk_get(generic_phy, "ref_clk",
 213                                    &phy_common->ref_clk);
 214
 215 out:
 216         return err;
 217 }
 218 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_clks);
 219
 220 int
 221 ufs_qcom_phy_init_vregulators(struct phy *generic_phy,
 222                               struct ufs_qcom_phy *phy_common)
 223 {
 224         int err;
 225
 226         err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_pll,
 227                 "vdda-pll");
 228         if (err)
 229                 goto out;
 230
 231         err = ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vdda_phy,
 232                 "vdda-phy");
 233
 234         if (err)
 235                 goto out;
 236
 237         /* vddp-ref-clk-* properties are optional */
 238         __ufs_qcom_phy_init_vreg(generic_phy, &phy_common->vddp_ref_clk,
 239                                  "vddp-ref-clk", true);
 240 out:
 241         return err;
 242 }
 243 EXPORT_SYMBOL_GPL(ufs_qcom_phy_init_vregulators);
 244
 245 static int __ufs_qcom_phy_init_vreg(struct phy *phy,
 246                 struct ufs_qcom_phy_vreg *vreg, const char *name, bool optional)
 247 {
 248         int err = 0;
 249         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
 250         struct device *dev = ufs_qcom_phy->dev;
 251
 252         char prop_name[MAX_PROP_NAME];
 253
 254         vreg->name = kstrdup(name, GFP_KERNEL);
 255         if (!vreg->name) {
 256                 err = -ENOMEM;
 257                 goto out;
 258         }
 259
 260         vreg->reg = devm_regulator_get(dev, name);
 261         if (IS_ERR(vreg->reg)) {
 262                 err = PTR_ERR(vreg->reg);
 263                 vreg->reg = NULL;
 264                 if (!optional)
 265                         dev_err(dev, "failed to get %s, %d\n", name, err);
 266                 goto out;
 267         }
 268
 269         if (dev->of_node) {
 270                 snprintf(prop_name, MAX_PROP_NAME, "%s-max-microamp", name);
 271                 err = of_property_read_u32(dev->of_node,
 272                                         prop_name, &vreg->max_uA);
 273                 if (err && err != -EINVAL) {
 274                         dev_err(dev, "%s: failed to read %s\n",
 275                                         __func__, prop_name);
 276                         goto out;
 277                 } else if (err == -EINVAL || !vreg->max_uA) {
 278                         if (regulator_count_voltages(vreg->reg) > 0) {
 279                                 dev_err(dev, "%s: %s is mandatory\n",
 280                                                 __func__, prop_name);
 281                                 goto out;
 282                         }
 283                         err = 0;
 284                 }
 285                 snprintf(prop_name, MAX_PROP_NAME, "%s-always-on", name);
 286                 vreg->is_always_on = of_property_read_bool(dev->of_node,
 287                                                            prop_name);
 288         }
 289
 290         if (!strcmp(name, "vdda-pll")) {
 291                 vreg->max_uV = VDDA_PLL_MAX_UV;
 292                 vreg->min_uV = VDDA_PLL_MIN_UV;
 293         } else if (!strcmp(name, "vdda-phy")) {
 294                 vreg->max_uV = VDDA_PHY_MAX_UV;
 295                 vreg->min_uV = VDDA_PHY_MIN_UV;
 296         } else if (!strcmp(name, "vddp-ref-clk")) {
 297                 vreg->max_uV = VDDP_REF_CLK_MAX_UV;
 298                 vreg->min_uV = VDDP_REF_CLK_MIN_UV;
 299         }
 300
 301 out:
 302         if (err)
 303                 kfree(vreg->name);
 304         return err;
 305 }
 306
 307 static int ufs_qcom_phy_init_vreg(struct phy *phy,
 308                         struct ufs_qcom_phy_vreg *vreg, const char *name)
 309 {
 310         return __ufs_qcom_phy_init_vreg(phy, vreg, name, false);
 311 }
 312
 313 static
 314 int ufs_qcom_phy_cfg_vreg(struct phy *phy,
 315                           struct ufs_qcom_phy_vreg *vreg, bool on)
 316 {
 317         int ret = 0;
 318         struct regulator *reg = vreg->reg;
 319         const char *name = vreg->name;
 320         int min_uV;
 321         int uA_load;
 322         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
 323         struct device *dev = ufs_qcom_phy->dev;
 324
 325         BUG_ON(!vreg);
 326
 327         if (regulator_count_voltages(reg) > 0) {
 328                 min_uV = on ? vreg->min_uV : 0;
 329                 ret = regulator_set_voltage(reg, min_uV, vreg->max_uV);
 330                 if (ret) {
 331                         dev_err(dev, "%s: %s set voltage failed, err=%d\n",
 332                                         __func__, name, ret);
 333                         goto out;
 334                 }
 335                 uA_load = on ? vreg->max_uA : 0;
 336                 ret = regulator_set_load(reg, uA_load);
 337                 if (ret >= 0) {
 338                         /*
 339                          * regulator_set_load() returns new regulator
 340                          * mode upon success.
 341                          */
 342                         ret = 0;
 343                 } else {
 344                         dev_err(dev, "%s: %s set optimum mode(uA_load=%d) failed, err=%d\n",
 345                                         __func__, name, uA_load, ret);
 346                         goto out;
 347                 }
 348         }
 349 out:
 350         return ret;
 351 }
 352
 353 static
 354 int ufs_qcom_phy_enable_vreg(struct phy *phy,
 355                              struct ufs_qcom_phy_vreg *vreg)
 356 {
 357         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
 358         struct device *dev = ufs_qcom_phy->dev;
 359         int ret = 0;
 360
 361         if (!vreg || vreg->enabled)
 362                 goto out;
 363
 364         ret = ufs_qcom_phy_cfg_vreg(phy, vreg, true);
 365         if (ret) {
 366                 dev_err(dev, "%s: ufs_qcom_phy_cfg_vreg() failed, err=%d\n",
 367                         __func__, ret);
 368                 goto out;
 369         }
 370
 371         ret = regulator_enable(vreg->reg);
 372         if (ret) {
 373                 dev_err(dev, "%s: enable failed, err=%d\n",
 374                                 __func__, ret);
 375                 goto out;
 376         }
 377
 378         vreg->enabled = true;
 379 out:
 380         return ret;
 381 }
 382
 383 int ufs_qcom_phy_enable_ref_clk(struct phy *generic_phy)
 384 {
 385         int ret = 0;
 386         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 387
 388         if (phy->is_ref_clk_enabled)
 389                 goto out;
 390
 391         /*
 392          * reference clock is propagated in a daisy-chained manner from
 393          * source to phy, so ungate them at each stage.
 394          */
 395         ret = clk_prepare_enable(phy->ref_clk_src);
 396         if (ret) {
 397                 dev_err(phy->dev, "%s: ref_clk_src enable failed %d\n",
 398                                 __func__, ret);
 399                 goto out;
 400         }
 401
 402         /*
 403          * "ref_clk_parent" is optional clock hence make sure that clk reference
 404          * is available before trying to enable the clock.
 405          */
 406         if (phy->ref_clk_parent) {
 407                 ret = clk_prepare_enable(phy->ref_clk_parent);
 408                 if (ret) {
 409                         dev_err(phy->dev, "%s: ref_clk_parent enable failed %d\n",
 410                                         __func__, ret);
 411                         goto out_disable_src;
 412                 }
 413         }
 414
 415         ret = clk_prepare_enable(phy->ref_clk);
 416         if (ret) {
 417                 dev_err(phy->dev, "%s: ref_clk enable failed %d\n",
 418                                 __func__, ret);
 419                 goto out_disable_parent;
 420         }
 421
 422         phy->is_ref_clk_enabled = true;
 423         goto out;
 424
 425 out_disable_parent:
 426         if (phy->ref_clk_parent)
 427                 clk_disable_unprepare(phy->ref_clk_parent);
 428 out_disable_src:
 429         clk_disable_unprepare(phy->ref_clk_src);
 430 out:
 431         return ret;
 432 }
 433 EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_ref_clk);
 434
 435 static
 436 int ufs_qcom_phy_disable_vreg(struct phy *phy,
 437                               struct ufs_qcom_phy_vreg *vreg)
 438 {
 439         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(phy);
 440         struct device *dev = ufs_qcom_phy->dev;
 441         int ret = 0;
 442
 443         if (!vreg || !vreg->enabled || vreg->is_always_on)
 444                 goto out;
 445
 446         ret = regulator_disable(vreg->reg);
 447
 448         if (!ret) {
 449                 /* ignore errors on applying disable config */
 450                 ufs_qcom_phy_cfg_vreg(phy, vreg, false);
 451                 vreg->enabled = false;
 452         } else {
 453                 dev_err(dev, "%s: %s disable failed, err=%d\n",
 454                                 __func__, vreg->name, ret);
 455         }
 456 out:
 457         return ret;
 458 }
 459
 460 void ufs_qcom_phy_disable_ref_clk(struct phy *generic_phy)
 461 {
 462         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 463
 464         if (phy->is_ref_clk_enabled) {
 465                 clk_disable_unprepare(phy->ref_clk);
 466                 /*
 467                  * "ref_clk_parent" is optional clock hence make sure that clk
 468                  * reference is available before trying to disable the clock.
 469                  */
 470                 if (phy->ref_clk_parent)
 471                         clk_disable_unprepare(phy->ref_clk_parent);
 472                 clk_disable_unprepare(phy->ref_clk_src);
 473                 phy->is_ref_clk_enabled = false;
 474         }
 475 }
 476 EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_ref_clk);
 477
 478 #define UFS_REF_CLK_EN  (1 << 5)
 479
 480 static void ufs_qcom_phy_dev_ref_clk_ctrl(struct phy *generic_phy, bool enable)
 481 {
 482         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 483
 484         if (phy->dev_ref_clk_ctrl_mmio &&
 485             (enable ^ phy->is_dev_ref_clk_enabled)) {
 486                 u32 temp = readl_relaxed(phy->dev_ref_clk_ctrl_mmio);
 487
 488                 if (enable)
 489                         temp |= UFS_REF_CLK_EN;
 490                 else
 491                         temp &= ~UFS_REF_CLK_EN;
 492
 493                 /*
 494                  * If we are here to disable this clock immediately after
 495                  * entering into hibern8, we need to make sure that device
 496                  * ref_clk is active atleast 1us after the hibern8 enter.
 497                  */
 498                 if (!enable)
 499                         udelay(1);
 500
 501                 writel_relaxed(temp, phy->dev_ref_clk_ctrl_mmio);
 502                 /* ensure that ref_clk is enabled/disabled before we return */
 503                 wmb();
 504                 /*
 505                  * If we call hibern8 exit after this, we need to make sure that
 506                  * device ref_clk is stable for atleast 1us before the hibern8
 507                  * exit command.
 508                  */
 509                 if (enable)
 510                         udelay(1);
 511
 512                 phy->is_dev_ref_clk_enabled = enable;
 513         }
 514 }
 515
 516 void ufs_qcom_phy_enable_dev_ref_clk(struct phy *generic_phy)
 517 {
 518         ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, true);
 519 }
 520 EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_dev_ref_clk);
 521
 522 void ufs_qcom_phy_disable_dev_ref_clk(struct phy *generic_phy)
 523 {
 524         ufs_qcom_phy_dev_ref_clk_ctrl(generic_phy, false);
 525 }
 526 EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_dev_ref_clk);
 527
 528 /* Turn ON M-PHY RMMI interface clocks */
 529 int ufs_qcom_phy_enable_iface_clk(struct phy *generic_phy)
 530 {
 531         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 532         int ret = 0;
 533
 534         if (phy->is_iface_clk_enabled)
 535                 goto out;
 536
 537         ret = clk_prepare_enable(phy->tx_iface_clk);
 538         if (ret) {
 539                 dev_err(phy->dev, "%s: tx_iface_clk enable failed %d\n",
 540                                 __func__, ret);
 541                 goto out;
 542         }
 543         ret = clk_prepare_enable(phy->rx_iface_clk);
 544         if (ret) {
 545                 clk_disable_unprepare(phy->tx_iface_clk);
 546                 dev_err(phy->dev, "%s: rx_iface_clk enable failed %d. disabling also tx_iface_clk\n",
 547                                 __func__, ret);
 548                 goto out;
 549         }
 550         phy->is_iface_clk_enabled = true;
 551
 552 out:
 553         return ret;
 554 }
 555 EXPORT_SYMBOL_GPL(ufs_qcom_phy_enable_iface_clk);
 556
 557 /* Turn OFF M-PHY RMMI interface clocks */
 558 void ufs_qcom_phy_disable_iface_clk(struct phy *generic_phy)
 559 {
 560         struct ufs_qcom_phy *phy = get_ufs_qcom_phy(generic_phy);
 561
 562         if (phy->is_iface_clk_enabled) {
 563                 clk_disable_unprepare(phy->tx_iface_clk);
 564                 clk_disable_unprepare(phy->rx_iface_clk);
 565                 phy->is_iface_clk_enabled = false;
 566         }
 567 }
 568 EXPORT_SYMBOL_GPL(ufs_qcom_phy_disable_iface_clk);
 569
 570 int ufs_qcom_phy_start_serdes(struct phy *generic_phy)
 571 {
 572         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 573         int ret = 0;
 574
 575         if (!ufs_qcom_phy->phy_spec_ops->start_serdes) {
 576                 dev_err(ufs_qcom_phy->dev, "%s: start_serdes() callback is not supported\n",
 577                         __func__);
 578                 ret = -ENOTSUPP;
 579         } else {
 580                 ufs_qcom_phy->phy_spec_ops->start_serdes(ufs_qcom_phy);
 581         }
 582
 583         return ret;
 584 }
 585 EXPORT_SYMBOL_GPL(ufs_qcom_phy_start_serdes);
 586
 587 int ufs_qcom_phy_set_tx_lane_enable(struct phy *generic_phy, u32 tx_lanes)
 588 {
 589         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 590         int ret = 0;
 591
 592         if (!ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable) {
 593                 dev_err(ufs_qcom_phy->dev, "%s: set_tx_lane_enable() callback is not supported\n",
 594                         __func__);
 595                 ret = -ENOTSUPP;
 596         } else {
 597                 ufs_qcom_phy->phy_spec_ops->set_tx_lane_enable(ufs_qcom_phy,
 598                                                                tx_lanes);
 599         }
 600
 601         return ret;
 602 }
 603 EXPORT_SYMBOL_GPL(ufs_qcom_phy_set_tx_lane_enable);
 604
 605 void ufs_qcom_phy_save_controller_version(struct phy *generic_phy,
 606                                           u8 major, u16 minor, u16 step)
 607 {
 608         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 609
 610         ufs_qcom_phy->host_ctrl_rev_major = major;
 611         ufs_qcom_phy->host_ctrl_rev_minor = minor;
 612         ufs_qcom_phy->host_ctrl_rev_step = step;
 613 }
 614 EXPORT_SYMBOL_GPL(ufs_qcom_phy_save_controller_version);
 615
 616 int ufs_qcom_phy_calibrate_phy(struct phy *generic_phy, bool is_rate_B)
 617 {
 618         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 619         int ret = 0;
 620
 621         if (!ufs_qcom_phy->phy_spec_ops->calibrate_phy) {
 622                 dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() callback is not supported\n",
 623                         __func__);
 624                 ret = -ENOTSUPP;
 625         } else {
 626                 ret = ufs_qcom_phy->phy_spec_ops->
 627                                 calibrate_phy(ufs_qcom_phy, is_rate_B);
 628                 if (ret)
 629                         dev_err(ufs_qcom_phy->dev, "%s: calibrate_phy() failed %d\n",
 630                                 __func__, ret);
 631         }
 632
 633         return ret;
 634 }
 635 EXPORT_SYMBOL_GPL(ufs_qcom_phy_calibrate_phy);
 636
 637 int ufs_qcom_phy_remove(struct phy *generic_phy,
 638                         struct ufs_qcom_phy *ufs_qcom_phy)
 639 {
 640         phy_power_off(generic_phy);
 641
 642         kfree(ufs_qcom_phy->vdda_pll.name);
 643         kfree(ufs_qcom_phy->vdda_phy.name);
 644
 645         return 0;
 646 }
 647 EXPORT_SYMBOL_GPL(ufs_qcom_phy_remove);
 648
 649 int ufs_qcom_phy_exit(struct phy *generic_phy)
 650 {
 651         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 652
 653         if (ufs_qcom_phy->is_powered_on)
 654                 phy_power_off(generic_phy);
 655
 656         return 0;
 657 }
 658 EXPORT_SYMBOL_GPL(ufs_qcom_phy_exit);
 659
 660 int ufs_qcom_phy_is_pcs_ready(struct phy *generic_phy)
 661 {
 662         struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
 663
 664         if (!ufs_qcom_phy->phy_spec_ops->is_physical_coding_sublayer_ready) {
 665                 dev_err(ufs_qcom_phy->dev, "%s: is_physical_coding_sublayer_ready() callback is not supported\n",
 666                         __func__);
 667                 return -ENOTSUPP;
 668         }
 669
 670         return ufs_qcom_phy->phy_spec_ops->
 671                         is_physical_coding_sublayer_ready(ufs_qcom_phy);
 672 }
 673 EXPORT_SYMBOL_GPL(ufs_qcom_phy_is_pcs_ready);
 674
 675 int ufs_qcom_phy_power_on(struct phy *generic_phy)
 676 {
 677         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 678         struct device *dev = phy_common->dev;
 679         int err;
 680
 681         err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_phy);
 682         if (err) {
 683                 dev_err(dev, "%s enable vdda_phy failed, err=%d\n",
 684                         __func__, err);
 685                 goto out;
 686         }
 687
 688         phy_common->phy_spec_ops->power_control(phy_common, true);
 689
 690         /* vdda_pll also enables ref clock LDOs so enable it first */
 691         err = ufs_qcom_phy_enable_vreg(generic_phy, &phy_common->vdda_pll);
 692         if (err) {
 693                 dev_err(dev, "%s enable vdda_pll failed, err=%d\n",
 694                         __func__, err);
 695                 goto out_disable_phy;
 696         }
 697
 698         err = ufs_qcom_phy_enable_ref_clk(generic_phy);
 699         if (err) {
 700                 dev_err(dev, "%s enable phy ref clock failed, err=%d\n",
 701                         __func__, err);
 702                 goto out_disable_pll;
 703         }
 704
 705         /* enable device PHY ref_clk pad rail */
 706         if (phy_common->vddp_ref_clk.reg) {
 707                 err = ufs_qcom_phy_enable_vreg(generic_phy,
 708                                                &phy_common->vddp_ref_clk);
 709                 if (err) {
 710                         dev_err(dev, "%s enable vddp_ref_clk failed, err=%d\n",
 711                                 __func__, err);
 712                         goto out_disable_ref_clk;
 713                 }
 714         }
 715
 716         phy_common->is_powered_on = true;
 717         goto out;
 718
 719 out_disable_ref_clk:
 720         ufs_qcom_phy_disable_ref_clk(generic_phy);
 721 out_disable_pll:
 722         ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
 723 out_disable_phy:
 724         ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
 725 out:
 726         return err;
 727 }
 728 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_on);
 729
 730 int ufs_qcom_phy_power_off(struct phy *generic_phy)
 731 {
 732         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
 733
 734         phy_common->phy_spec_ops->power_control(phy_common, false);
 735
 736         if (phy_common->vddp_ref_clk.reg)
 737                 ufs_qcom_phy_disable_vreg(generic_phy,
 738                                           &phy_common->vddp_ref_clk);
 739         ufs_qcom_phy_disable_ref_clk(generic_phy);
 740
 741         ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_pll);
 742         ufs_qcom_phy_disable_vreg(generic_phy, &phy_common->vdda_phy);
 743         phy_common->is_powered_on = false;
 744
 745         return 0;
 746 }
 747 EXPORT_SYMBOL_GPL(ufs_qcom_phy_power_off);