arch/arm/mach-omap2/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap2/irq.c
   3  *
   4  * Interrupt handler for OMAP2 boards.
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License. See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <mach/hardware.h>
  18 #include <asm/mach/irq.h>
  19
  20
  21 /* selected INTC register offsets */
  22
  23 #define INTC_REVISION           0x0000
  24 #define INTC_SYSCONFIG          0x0010
  25 #define INTC_SYSSTATUS          0x0014
  26 #define INTC_SIR                0x0040
  27 #define INTC_CONTROL            0x0048
  28 #define INTC_MIR_CLEAR0         0x0088
  29 #define INTC_MIR_SET0           0x008c
  30 #define INTC_PENDING_IRQ0       0x0098
  31 /* Number of IRQ state bits in each MIR register */
  32 #define IRQ_BITS_PER_REG        32
  33
  34 /*
  35  * OMAP2 has a number of different interrupt controllers, each interrupt
  36  * controller is identified as its own "bank". Register definitions are
  37  * fairly consistent for each bank, but not all registers are implemented
  38  * for each bank.. when in doubt, consult the TRM.
  39  */
  40 static struct omap_irq_bank {
  41         void __iomem *base_reg;
  42         unsigned int nr_irqs;
  43 } __attribute__ ((aligned(4))) irq_banks[] = {
  44         {
  45                 /* MPU INTC */
  46                 .base_reg       = 0,
  47                 .nr_irqs        = 96,
  48         },
  49 };
  50
  51 /* INTC bank register get/set */
  52
  53 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
  54 {
  55         __raw_writel(val, bank->base_reg + reg);
  56 }
  57
  58 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
  59 {
  60         return __raw_readl(bank->base_reg + reg);
  61 }
  62
  63 static int previous_irq;
  64
  65 /*
  66  * On 34xx we can get occasional spurious interrupts if the ack from
  67  * an interrupt handler does not get posted before we unmask. Warn about
  68  * the interrupt handlers that need to flush posted writes.
  69  */
  70 static int omap_check_spurious(unsigned int irq)
  71 {
  72         u32 sir, spurious;
  73
  74         sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
  75         spurious = sir >> 7;
  76
  77         if (spurious) {
  78                 printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
  79                                         "posted write for irq %i\n",
  80                                         irq, sir, previous_irq);
  81                 return spurious;
  82         }
  83
  84         return 0;
  85 }
  86
  87 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
  88 static void omap_ack_irq(unsigned int irq)
  89 {
  90         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
  91 }
  92
  93 static void omap_mask_irq(unsigned int irq)
  94 {
  95         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
  96
  97         if (cpu_is_omap34xx()) {
  98                 int spurious = 0;
  99
 100                 /*
 101                  * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
 102                  * it is the highest irq number?
 103                  */
 104                 if (irq == INT_34XX_GPT12_IRQ)
 105                         spurious = omap_check_spurious(irq);
 106
 107                 if (!spurious)
 108                         previous_irq = irq;
 109         }
 110
 111         irq &= (IRQ_BITS_PER_REG - 1);
 112
 113         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
 114 }
 115
 116 static void omap_unmask_irq(unsigned int irq)
 117 {
 118         int offset = irq & (~(IRQ_BITS_PER_REG - 1));
 119
 120         irq &= (IRQ_BITS_PER_REG - 1);
 121
 122         intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
 123 }
 124
 125 static void omap_mask_ack_irq(unsigned int irq)
 126 {
 127         omap_mask_irq(irq);
 128         omap_ack_irq(irq);
 129 }
 130
 131 static struct irq_chip omap_irq_chip = {
 132         .name   = "INTC",
 133         .ack    = omap_mask_ack_irq,
 134         .mask   = omap_mask_irq,
 135         .unmask = omap_unmask_irq,
 136 };
 137
 138 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
 139 {
 140         unsigned long tmp;
 141
 142         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
 143         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
 144                          "(revision %ld.%ld) with %d interrupts\n",
 145                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
 146
 147         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
 148         tmp |= 1 << 1;  /* soft reset */
 149         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
 150
 151         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
 152                 /* Wait for reset to complete */;
 153
 154         /* Enable autoidle */
 155         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
 156 }
 157
 158 int omap_irq_pending(void)
 159 {
 160         int i;
 161
 162         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 163                 struct omap_irq_bank *bank = irq_banks + i;
 164                 int irq;
 165
 166                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
 167                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
 168                                                ((irq >> 5) << 5)))
 169                                 return 1;
 170         }
 171         return 0;
 172 }
 173
 174 void __init omap_init_irq(void)
 175 {
 176         unsigned long nr_of_irqs = 0;
 177         unsigned int nr_banks = 0;
 178         int i;
 179
 180         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 181                 struct omap_irq_bank *bank = irq_banks + i;
 182
 183                 if (cpu_is_omap24xx())
 184                         bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
 185                 else if (cpu_is_omap34xx())
 186                         bank->base_reg = OMAP2_IO_ADDRESS(OMAP34XX_IC_BASE);
 187
 188                 omap_irq_bank_init_one(bank);
 189
 190                 nr_of_irqs += bank->nr_irqs;
 191                 nr_banks++;
 192         }
 193
 194         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
 195                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 196
 197         for (i = 0; i < nr_of_irqs; i++) {
 198                 set_irq_chip(i, &omap_irq_chip);
 199                 set_irq_handler(i, handle_level_irq);
 200                 set_irq_flags(i, IRQF_VALID);
 201         }
 202 }
 203