arch/arm/mach-omap2/sdrc2xxx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/sdrc2xxx.c
   3  *
   4  * SDRAM timing related functions for OMAP2xxx
   5  *
   6  * Copyright (C) 2005, 2008 Texas Instruments Inc.
   7  * Copyright (C) 2005, 2008 Nokia Corporation
   8  *
   9  * Tony Lindgren <tony@atomide.com>
  10  * Paul Walmsley
  11  * Richard Woodruff <r-woodruff2@ti.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/device.h>
  21 #include <linux/list.h>
  22 #include <linux/errno.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/common.h>
  28 #include <mach/clock.h>
  29 #include <mach/sram.h>
  30
  31 #include "prm.h"
  32 #include "clock.h"
  33 #include <mach/sdrc.h>
  34 #include "sdrc.h"
  35
  36 /* Memory timing, DLL mode flags */
  37 #define M_DDR           1
  38 #define M_LOCK_CTRL     (1 << 2)
  39 #define M_UNLOCK        0
  40 #define M_LOCK          1
  41
  42
  43 static struct memory_timings mem_timings;
  44 static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
  45
  46 static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
  47 {
  48         return mem_timings.slow_dll_ctrl;
  49 }
  50
  51 static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
  52 {
  53         return mem_timings.fast_dll_ctrl;
  54 }
  55
  56 static u32 omap2xxx_sdrc_get_type(void)
  57 {
  58         return mem_timings.m_type;
  59 }
  60
  61 /*
  62  * Check the DLL lock state, and return tue if running in unlock mode.
  63  * This is needed to compensate for the shifted DLL value in unlock mode.
  64  */
  65 u32 omap2xxx_sdrc_dll_is_unlocked(void)
  66 {
  67         /* dlla and dllb are a set */
  68         u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
  69
  70         if ((dll_state & (1 << 2)) == (1 << 2))
  71                 return 1;
  72         else
  73                 return 0;
  74 }
  75
  76 /*
  77  * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
  78  * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
  79  * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
  80  *
  81  * Used by the clock framework during CORE DPLL changes
  82  */
  83 u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
  84 {
  85         u32 dll_ctrl, m_type;
  86         u32 prev = curr_perf_level;
  87         unsigned long flags;
  88
  89         if ((curr_perf_level == level) && !force)
  90                 return prev;
  91
  92         if (level == CORE_CLK_SRC_DPLL)
  93                 dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
  94         else if (level == CORE_CLK_SRC_DPLL_X2)
  95                 dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
  96         else
  97                 return prev;
  98
  99         m_type = omap2xxx_sdrc_get_type();
 100
 101         local_irq_save(flags);
 102         if (cpu_is_omap2420())
 103                 __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
 104         else
 105                 __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
 106         omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
 107         curr_perf_level = level;
 108         local_irq_restore(flags);
 109
 110         return prev;
 111 }
 112
 113 /* Used by the clock framework during CORE DPLL changes */
 114 void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
 115 {
 116         unsigned long dll_cnt;
 117         u32 fast_dll = 0;
 118
 119         /* DDR = 1, SDR = 0 */
 120         mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
 121
 122         /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
 123          * In the case of 2422, its ok to use CS1 instead of CS0.
 124          */
 125         if (cpu_is_omap2422())
 126                 mem_timings.base_cs = 1;
 127         else
 128                 mem_timings.base_cs = 0;
 129
 130         if (mem_timings.m_type != M_DDR)
 131                 return;
 132
 133         /* With DDR we need to determine the low frequency DLL value */
 134         if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
 135                 mem_timings.dll_mode = M_UNLOCK;
 136         else
 137                 mem_timings.dll_mode = M_LOCK;
 138
 139         if (mem_timings.base_cs == 0) {
 140                 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
 141                 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
 142         } else {
 143                 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
 144                 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
 145         }
 146         if (force_lock_to_unlock_mode) {
 147                 fast_dll &= ~0xff00;
 148                 fast_dll |= dll_cnt;            /* Current lock mode */
 149         }
 150         /* set fast timings with DLL filter disabled */
 151         mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
 152
 153         /* No disruptions, DDR will be offline & C-ABI not followed */
 154         omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
 155                             mem_timings.fast_dll_ctrl,
 156                             mem_timings.base_cs,
 157                             force_lock_to_unlock_mode);
 158         mem_timings.slow_dll_ctrl &= 0xff00;    /* Keep lock value */
 159
 160         /* Turn status into unlock ctrl */
 161         mem_timings.slow_dll_ctrl |=
 162                 ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
 163
 164         /* 90 degree phase for anything below 133Mhz + disable DLL filter */
 165         mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
 166 }