arch/powerpc/mm/40x_mmu.c

   1 /*
   2  * This file contains the routines for initializing the MMU
   3  * on the 4xx series of chips.
   4  *  -- paulus
   5  *
   6  *  Derived from arch/ppc/mm/init.c:
   7  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   8  *
   9  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  10  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  11  *    Copyright (C) 1996 Paul Mackerras
  12  *
  13  *  Derived from "arch/i386/mm/init.c"
  14  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  15  *
  16  *  This program is free software; you can redistribute it and/or
  17  *  modify it under the terms of the GNU General Public License
  18  *  as published by the Free Software Foundation; either version
  19  *  2 of the License, or (at your option) any later version.
  20  *
  21  */
  22
  23 #include <linux/signal.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/errno.h>
  27 #include <linux/string.h>
  28 #include <linux/types.h>
  29 #include <linux/ptrace.h>
  30 #include <linux/mman.h>
  31 #include <linux/mm.h>
  32 #include <linux/swap.h>
  33 #include <linux/stddef.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/init.h>
  36 #include <linux/delay.h>
  37 #include <linux/highmem.h>
  38
  39 #include <asm/pgalloc.h>
  40 #include <asm/prom.h>
  41 #include <asm/io.h>
  42 #include <asm/mmu_context.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/mmu.h>
  45 #include <asm/uaccess.h>
  46 #include <asm/smp.h>
  47 #include <asm/bootx.h>
  48 #include <asm/machdep.h>
  49 #include <asm/setup.h>
  50 #include "mmu_decl.h"
  51
  52 extern int __map_without_ltlbs;
  53 /*
  54  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
  55  */
  56 void __init MMU_init_hw(void)
  57 {
  58         /*
  59          * The Zone Protection Register (ZPR) defines how protection will
  60          * be applied to every page which is a member of a given zone. At
  61          * present, we utilize only two of the 4xx's zones.
  62          * The zone index bits (of ZSEL) in the PTE are used for software
  63          * indicators, except the LSB.  For user access, zone 1 is used,
  64          * for kernel access, zone 0 is used.  We set all but zone 1
  65          * to zero, allowing only kernel access as indicated in the PTE.
  66          * For zone 1, we set a 01 binary (a value of 10 will not work)
  67          * to allow user access as indicated in the PTE.  This also allows
  68          * kernel access as indicated in the PTE.
  69          */
  70
  71         mtspr(SPRN_ZPR, 0x10000000);
  72
  73         flush_instruction_cache();
  74
  75         /*
  76          * Set up the real-mode cache parameters for the exception vector
  77          * handlers (which are run in real-mode).
  78          */
  79
  80         mtspr(SPRN_DCWR, 0x00000000);   /* All caching is write-back */
  81
  82         /*
  83          * Cache instruction and data space where the exception
  84          * vectors and the kernel live in real-mode.
  85          */
  86
  87         mtspr(SPRN_DCCR, 0xF0000000);   /* 512 MB of data space at 0x0. */
  88         mtspr(SPRN_ICCR, 0xF0000000);   /* 512 MB of instr. space at 0x0. */
  89 }
  90
  91 #define LARGE_PAGE_SIZE_16M     (1<<24)
  92 #define LARGE_PAGE_SIZE_4M      (1<<22)
  93
  94 unsigned long __init mmu_mapin_ram(void)
  95 {
  96         unsigned long v, s, mapped;
  97         phys_addr_t p;
  98
  99         v = KERNELBASE;
 100         p = 0;
 101         s = total_lowmem;
 102
 103         if (__map_without_ltlbs)
 104                 return 0;
 105
 106         while (s >= LARGE_PAGE_SIZE_16M) {
 107                 pmd_t *pmdp;
 108                 unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 109
 110                 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
 111                 pmd_val(*pmdp++) = val;
 112                 pmd_val(*pmdp++) = val;
 113                 pmd_val(*pmdp++) = val;
 114                 pmd_val(*pmdp++) = val;
 115
 116                 v += LARGE_PAGE_SIZE_16M;
 117                 p += LARGE_PAGE_SIZE_16M;
 118                 s -= LARGE_PAGE_SIZE_16M;
 119         }
 120
 121         while (s >= LARGE_PAGE_SIZE_4M) {
 122                 pmd_t *pmdp;
 123                 unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
 124
 125                 pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
 126                 pmd_val(*pmdp) = val;
 127
 128                 v += LARGE_PAGE_SIZE_4M;
 129                 p += LARGE_PAGE_SIZE_4M;
 130                 s -= LARGE_PAGE_SIZE_4M;
 131         }
 132
 133         mapped = total_lowmem - s;
 134
 135         /* If the size of RAM is not an exact power of two, we may not
 136          * have covered RAM in its entirety with 16 and 4 MiB
 137          * pages. Consequently, restrict the top end of RAM currently
 138          * allocable so that calls to the LMB to allocate PTEs for "tail"
 139          * coverage with normal-sized pages (or other reasons) do not
 140          * attempt to allocate outside the allowed range.
 141          */
 142
 143         __initial_memory_limit_addr = memstart_addr + mapped;
 144
 145         return mapped;
 146 }