arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33 #include <linux/of_platform.h>
  34 #include <linux/of_device.h>
  35 #include <linux/phy.h>
  36 #include <linux/lmb.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/atomic.h>
  40 #include <asm/time.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/pci-bridge.h>
  44 #include <asm/irq.h>
  45 #include <mm/mmu_decl.h>
  46 #include <asm/prom.h>
  47 #include <asm/udbg.h>
  48 #include <sysdev/fsl_soc.h>
  49 #include <sysdev/fsl_pci.h>
  50 #include <asm/qe.h>
  51 #include <asm/qe_ic.h>
  52 #include <asm/mpic.h>
  53 #include <asm/swiotlb.h>
  54
  55 #undef DEBUG
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 #define MV88E1111_SCR   0x10
  63 #define MV88E1111_SCR_125CLK    0x0010
  64 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
  65 {
  66         int scr;
  67         int err;
  68
  69         /* Workaround for the 125 CLK Toggle */
  70         scr = phy_read(phydev, MV88E1111_SCR);
  71
  72         if (scr < 0)
  73                 return scr;
  74
  75         err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
  76
  77         if (err)
  78                 return err;
  79
  80         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  81
  82         if (err)
  83                 return err;
  84
  85         scr = phy_read(phydev, MV88E1111_SCR);
  86
  87         if (scr < 0)
  88                 return err;
  89
  90         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
  91
  92         return err;
  93 }
  94
  95 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
  96 {
  97         int temp;
  98         int err;
  99
 100         /* Errata */
 101         err = phy_write(phydev,29, 0x0006);
 102
 103         if (err)
 104                 return err;
 105
 106         temp = phy_read(phydev, 30);
 107
 108         if (temp < 0)
 109                 return temp;
 110
 111         temp = (temp & (~0x8000)) | 0x4000;
 112         err = phy_write(phydev,30, temp);
 113
 114         if (err)
 115                 return err;
 116
 117         err = phy_write(phydev,29, 0x000a);
 118
 119         if (err)
 120                 return err;
 121
 122         temp = phy_read(phydev, 30);
 123
 124         if (temp < 0)
 125                 return temp;
 126
 127         temp = phy_read(phydev, 30);
 128
 129         if (temp < 0)
 130                 return temp;
 131
 132         temp &= ~0x0020;
 133
 134         err = phy_write(phydev,30,temp);
 135
 136         if (err)
 137                 return err;
 138
 139         /* Disable automatic MDI/MDIX selection */
 140         temp = phy_read(phydev, 16);
 141
 142         if (temp < 0)
 143                 return temp;
 144
 145         temp &= ~0x0060;
 146         err = phy_write(phydev,16,temp);
 147
 148         return err;
 149 }
 150
 151 /* ************************************************************************
 152  *
 153  * Setup the architecture
 154  *
 155  */
 156 static void __init mpc85xx_mds_setup_arch(void)
 157 {
 158         struct device_node *np;
 159         static u8 __iomem *bcsr_regs = NULL;
 160 #ifdef CONFIG_PCI
 161         struct pci_controller *hose;
 162 #endif
 163         dma_addr_t max = 0xffffffff;
 164
 165         if (ppc_md.progress)
 166                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
 167
 168         /* Map BCSR area */
 169         np = of_find_node_by_name(NULL, "bcsr");
 170         if (np != NULL) {
 171                 struct resource res;
 172
 173                 of_address_to_resource(np, 0, &res);
 174                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
 175                 of_node_put(np);
 176         }
 177
 178 #ifdef CONFIG_PCI
 179         for_each_node_by_type(np, "pci") {
 180                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 181                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 182                         struct resource rsrc;
 183                         of_address_to_resource(np, 0, &rsrc);
 184                         if ((rsrc.start & 0xfffff) == 0x8000)
 185                                 fsl_add_bridge(np, 1);
 186                         else
 187                                 fsl_add_bridge(np, 0);
 188
 189                         hose = pci_find_hose_for_OF_device(np);
 190                         max = min(max, hose->dma_window_base_cur +
 191                                         hose->dma_window_size);
 192                 }
 193         }
 194 #endif
 195
 196 #ifdef CONFIG_QUICC_ENGINE
 197         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
 198         if (!np) {
 199                 np = of_find_node_by_name(NULL, "qe");
 200                 if (!np)
 201                         return;
 202         }
 203
 204         qe_reset();
 205         of_node_put(np);
 206
 207         np = of_find_node_by_name(NULL, "par_io");
 208         if (np) {
 209                 struct device_node *ucc;
 210
 211                 par_io_init(np);
 212                 of_node_put(np);
 213
 214                 for_each_node_by_name(ucc, "ucc")
 215                         par_io_of_config(ucc);
 216         }
 217
 218         if (bcsr_regs) {
 219                 if (machine_is(mpc8568_mds)) {
 220 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
 221 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
 222 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
 223 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
 224
 225                         /* Turn off UCC1 & UCC2 */
 226                         clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 227                         clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 228
 229                         /* Mode is RGMII, all bits clear */
 230                         clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
 231                                                  BCSR_UCC2_MODE_MSK);
 232
 233                         /* Turn UCC1 & UCC2 on */
 234                         setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
 235                         setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
 236                 } else if (machine_is(mpc8569_mds)) {
 237 #define BCSR7_UCC12_GETHnRST    (0x1 << 2)
 238 #define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
 239                         /*
 240                          * U-Boot mangles interrupt polarity for Marvell PHYs,
 241                          * so reset built-in and UEM Marvell PHYs, this puts
 242                          * the PHYs into their normal state.
 243                          */
 244                         clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 245                         setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 246
 247                         setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
 248                         clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
 249                 }
 250                 iounmap(bcsr_regs);
 251         }
 252 #endif  /* CONFIG_QUICC_ENGINE */
 253
 254 #ifdef CONFIG_SWIOTLB
 255         if (lmb_end_of_DRAM() > max) {
 256                 ppc_swiotlb_enable = 1;
 257                 set_pci_dma_ops(&swiotlb_pci_dma_ops);
 258         }
 259 #endif
 260 }
 261
 262
 263 static int __init board_fixups(void)
 264 {
 265         char phy_id[20];
 266         char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
 267         struct device_node *mdio;
 268         struct resource res;
 269         int i;
 270
 271         for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
 272                 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
 273
 274                 of_address_to_resource(mdio, 0, &res);
 275                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 276                         (unsigned long long)res.start, 1);
 277
 278                 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
 279                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 280
 281                 /* Register a workaround for errata */
 282                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
 283                         (unsigned long long)res.start, 7);
 284                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
 285
 286                 of_node_put(mdio);
 287         }
 288
 289         return 0;
 290 }
 291 machine_arch_initcall(mpc8568_mds, board_fixups);
 292 machine_arch_initcall(mpc8569_mds, board_fixups);
 293
 294 static struct of_device_id mpc85xx_ids[] = {
 295         { .type = "soc", },
 296         { .compatible = "soc", },
 297         { .compatible = "simple-bus", },
 298         { .type = "qe", },
 299         { .compatible = "fsl,qe", },
 300         { .compatible = "gianfar", },
 301         { .compatible = "fsl,rapidio-delta", },
 302         {},
 303 };
 304
 305 static int __init mpc85xx_publish_devices(void)
 306 {
 307         /* Publish the QE devices */
 308         of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
 309
 310         return 0;
 311 }
 312 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
 313 machine_device_initcall(mpc8569_mds, mpc85xx_publish_devices);
 314
 315 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
 316 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
 317
 318 static void __init mpc85xx_mds_pic_init(void)
 319 {
 320         struct mpic *mpic;
 321         struct resource r;
 322         struct device_node *np = NULL;
 323
 324         np = of_find_node_by_type(NULL, "open-pic");
 325         if (!np)
 326                 return;
 327
 328         if (of_address_to_resource(np, 0, &r)) {
 329                 printk(KERN_ERR "Failed to map mpic register space\n");
 330                 of_node_put(np);
 331                 return;
 332         }
 333
 334         mpic = mpic_alloc(np, r.start,
 335                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 336                         0, 256, " OpenPIC  ");
 337         BUG_ON(mpic == NULL);
 338         of_node_put(np);
 339
 340         mpic_init(mpic);
 341
 342 #ifdef CONFIG_QUICC_ENGINE
 343         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 344         if (!np) {
 345                 np = of_find_node_by_type(NULL, "qeic");
 346                 if (!np)
 347                         return;
 348         }
 349         qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
 350         of_node_put(np);
 351 #endif                          /* CONFIG_QUICC_ENGINE */
 352 }
 353
 354 static int __init mpc85xx_mds_probe(void)
 355 {
 356         unsigned long root = of_get_flat_dt_root();
 357
 358         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 359 }
 360
 361 define_machine(mpc8568_mds) {
 362         .name           = "MPC8568 MDS",
 363         .probe          = mpc85xx_mds_probe,
 364         .setup_arch     = mpc85xx_mds_setup_arch,
 365         .init_IRQ       = mpc85xx_mds_pic_init,
 366         .get_irq        = mpic_get_irq,
 367         .restart        = fsl_rstcr_restart,
 368         .calibrate_decr = generic_calibrate_decr,
 369         .progress       = udbg_progress,
 370 #ifdef CONFIG_PCI
 371         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 372 #endif
 373 };
 374
 375 static int __init mpc8569_mds_probe(void)
 376 {
 377         unsigned long root = of_get_flat_dt_root();
 378
 379         return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
 380 }
 381
 382 define_machine(mpc8569_mds) {
 383         .name           = "MPC8569 MDS",
 384         .probe          = mpc8569_mds_probe,
 385         .setup_arch     = mpc85xx_mds_setup_arch,
 386         .init_IRQ       = mpc85xx_mds_pic_init,
 387         .get_irq        = mpic_get_irq,
 388         .restart        = fsl_rstcr_restart,
 389         .calibrate_decr = generic_calibrate_decr,
 390         .progress       = udbg_progress,
 391 #ifdef CONFIG_PCI
 392         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 393 #endif
 394 };