sound/pci/azt3328.h

   1 #ifndef __SOUND_AZT3328_H
   2 #define __SOUND_AZT3328_H
   3
   4 /* "PU" == "power-up value", as tested on PCI168 PCI rev. 10
   5  * "WRITE_ONLY"  == register does not indicate actual bit values */
   6
   7 /*** main I/O area port indices ***/
   8 /* (only 0x70 of 0x80 bytes saved/restored by Windows driver) */
   9 #define AZF_IO_SIZE_CODEC       0x80
  10 #define AZF_IO_SIZE_CODEC_PM    0x70
  11
  12 /* the driver initialisation suggests a layout of 4 main areas:
  13  * from 0x00 (playback), from 0x20 (recording) and from 0x40 (maybe MPU401??).
  14  * And another area from 0x60 to 0x6f (DirectX timer, IRQ management,
  15  * power management etc.???). */
  16
  17 /** playback area **/
  18 #define IDX_IO_PLAY_FLAGS       0x00 /* PU:0x0000 */
  19      /* able to reactivate output after output muting due to 8/16bit
  20       * output change, just like 0x0002.
  21       * 0x0001 is the only bit that's able to start the DMA counter */
  22   #define DMA_RESUME                    0x0001 /* paused if cleared ? */
  23      /* 0x0002 *temporarily* set during DMA stopping. hmm
  24       * both 0x0002 and 0x0004 set in playback setup. */
  25      /* able to reactivate output after output muting due to 8/16bit
  26       * output change, just like 0x0001. */
  27   #define DMA_PLAY_SOMETHING1           0x0002 /* \ alternated (toggled) */
  28      /* 0x0004: NOT able to reactivate output */
  29   #define DMA_PLAY_SOMETHING2           0x0004 /* / bits */
  30   #define SOMETHING_ALMOST_ALWAYS_SET   0x0008 /* ???; can be modified */
  31   #define DMA_EPILOGUE_SOMETHING        0x0010
  32   #define DMA_SOMETHING_ELSE            0x0020 /* ??? */
  33   #define SOMETHING_UNMODIFIABLE        0xffc0 /* unused ? not modifiable */
  34 #define IDX_IO_PLAY_IRQTYPE     0x02 /* PU:0x0001 */
  35   /* write back to flags in case flags are set, in order to ACK IRQ in handler
  36    * (bit 1 of port 0x64 indicates interrupt for one of these three types)
  37    * sometimes in this case it just writes 0xffff to globally ACK all IRQs
  38    * settings written are not reflected when reading back, though.
  39    * seems to be IRQ, too (frequently used: port |= 0x07 !), but who knows ? */
  40   #define IRQ_PLAY_SOMETHING            0x0001 /* something & ACK */
  41   #define IRQ_FINISHED_PLAYBUF_1        0x0002 /* 1st dmabuf finished & ACK */
  42   #define IRQ_FINISHED_PLAYBUF_2        0x0004 /* 2nd dmabuf finished & ACK */
  43   #define IRQMASK_SOME_STATUS_1         0x0008 /* \ related bits */
  44   #define IRQMASK_SOME_STATUS_2         0x0010 /* / (checked together in loop) */
  45   #define IRQMASK_UNMODIFIABLE          0xffe0 /* unused ? not modifiable */
  46 #define IDX_IO_PLAY_DMA_START_1 0x04 /* start address of 1st DMA play area, PU:0x00000000 */
  47 #define IDX_IO_PLAY_DMA_START_2 0x08 /* start address of 2nd DMA play area, PU:0x00000000 */
  48 #define IDX_IO_PLAY_DMA_LEN_1   0x0c /* length of 1st DMA play area, PU:0x0000 */
  49 #define IDX_IO_PLAY_DMA_LEN_2   0x0e /* length of 2nd DMA play area, PU:0x0000 */
  50 #define IDX_IO_PLAY_DMA_CURRPOS 0x10 /* current DMA position, PU:0x00000000 */
  51 #define IDX_IO_PLAY_DMA_CURROFS 0x14 /* offset within current DMA play area, PU:0x0000 */
  52 #define IDX_IO_PLAY_SOUNDFORMAT 0x16 /* PU:0x0010 */
  53   /* all unspecified bits can't be modified */
  54   #define SOUNDFORMAT_FREQUENCY_MASK    0x000f
  55   #define SOUNDFORMAT_XTAL1             0x00
  56   #define SOUNDFORMAT_XTAL2             0x01
  57     /* all _SUSPECTED_ values are not used by Windows drivers, so we don't
  58      * have any hard facts, only rough measurements.
  59      * All we know is that the crystal used on the board has 24.576MHz,
  60      * like many soundcards (which results in the frequencies below when
  61      * using certain divider values selected by the values below) */
  62     #define SOUNDFORMAT_FREQ_SUSPECTED_4000     0x0c | SOUNDFORMAT_XTAL1
  63     #define SOUNDFORMAT_FREQ_SUSPECTED_4800     0x0a | SOUNDFORMAT_XTAL1
  64     #define SOUNDFORMAT_FREQ_5510               0x0c | SOUNDFORMAT_XTAL2
  65     #define SOUNDFORMAT_FREQ_6620               0x0a | SOUNDFORMAT_XTAL2
  66     #define SOUNDFORMAT_FREQ_8000               0x00 | SOUNDFORMAT_XTAL1 /* also 0x0e | SOUNDFORMAT_XTAL1? */
  67     #define SOUNDFORMAT_FREQ_9600               0x08 | SOUNDFORMAT_XTAL1
  68     #define SOUNDFORMAT_FREQ_11025              0x00 | SOUNDFORMAT_XTAL2 /* also 0x0e | SOUNDFORMAT_XTAL2? */
  69     #define SOUNDFORMAT_FREQ_SUSPECTED_13240    0x08 | SOUNDFORMAT_XTAL2 /* seems to be 6620 *2 */
  70     #define SOUNDFORMAT_FREQ_16000              0x02 | SOUNDFORMAT_XTAL1
  71     #define SOUNDFORMAT_FREQ_22050              0x02 | SOUNDFORMAT_XTAL2
  72     #define SOUNDFORMAT_FREQ_32000              0x04 | SOUNDFORMAT_XTAL1
  73     #define SOUNDFORMAT_FREQ_44100              0x04 | SOUNDFORMAT_XTAL2
  74     #define SOUNDFORMAT_FREQ_48000              0x06 | SOUNDFORMAT_XTAL1
  75     #define SOUNDFORMAT_FREQ_SUSPECTED_66200    0x06 | SOUNDFORMAT_XTAL2 /* 66200 (13240 * 5); 64000 may have been nicer :-\ */
  76   #define SOUNDFORMAT_FLAG_16BIT        0x0010
  77   #define SOUNDFORMAT_FLAG_2CHANNELS    0x0020
  78
  79 /* define frequency helpers, for maximum value safety */
  80 enum azf_freq_t {
  81 #define AZF_FREQ(rate) AZF_FREQ_##rate = rate
  82   AZF_FREQ(4000),
  83   AZF_FREQ(4800),
  84   AZF_FREQ(5512),
  85   AZF_FREQ(6620),
  86   AZF_FREQ(8000),
  87   AZF_FREQ(9600),
  88   AZF_FREQ(11025),
  89   AZF_FREQ(13240),
  90   AZF_FREQ(16000),
  91   AZF_FREQ(22050),
  92   AZF_FREQ(32000),
  93   AZF_FREQ(44100),
  94   AZF_FREQ(48000),
  95   AZF_FREQ(66200),
  96 #undef AZF_FREQ
  97 };
  98
  99 /** recording area (see also: playback bit flag definitions) **/
 100 #define IDX_IO_REC_FLAGS        0x20 /* ??, PU:0x0000 */
 101 #define IDX_IO_REC_IRQTYPE      0x22 /* ??, PU:0x0000 */
 102   #define IRQ_REC_SOMETHING             0x0001 /* something & ACK */
 103   #define IRQ_FINISHED_RECBUF_1         0x0002 /* 1st dmabuf finished & ACK */
 104   #define IRQ_FINISHED_RECBUF_2         0x0004 /* 2nd dmabuf finished & ACK */
 105   /* hmm, maybe these are just the corresponding *recording* flags ?
 106    * but OTOH they are most likely at port 0x22 instead */
 107   #define IRQMASK_SOME_STATUS_1         0x0008 /* \ related bits */
 108   #define IRQMASK_SOME_STATUS_2         0x0010 /* / (checked together in loop) */
 109 #define IDX_IO_REC_DMA_START_1  0x24 /* PU:0x00000000 */
 110 #define IDX_IO_REC_DMA_START_2  0x28 /* PU:0x00000000 */
 111 #define IDX_IO_REC_DMA_LEN_1    0x2c /* PU:0x0000 */
 112 #define IDX_IO_REC_DMA_LEN_2    0x2e /* PU:0x0000 */
 113 #define IDX_IO_REC_DMA_CURRPOS  0x30 /* PU:0x00000000 */
 114 #define IDX_IO_REC_DMA_CURROFS  0x34 /* PU:0x00000000 */
 115 #define IDX_IO_REC_SOUNDFORMAT  0x36 /* PU:0x0000 */
 116
 117 /** hmm, what is this I/O area for? MPU401?? or external DAC via I2S?? (after playback, recording, ???, timer) **/
 118 #define IDX_IO_SOMETHING_FLAGS  0x40 /* gets set to 0x34 just like port 0x0 and 0x20 on card init, PU:0x0000 */
 119 /* general */
 120 #define IDX_IO_42H              0x42 /* PU:0x0001 */
 121
 122 /** DirectX timer, main interrupt area (FIXME: and something else?) **/
 123 #define IDX_IO_TIMER_VALUE      0x60 /* found this timer area by pure luck :-) */
 124   /* timer countdown value; triggers IRQ when timer is finished */
 125   #define TIMER_VALUE_MASK              0x000fffffUL
 126   /* activate timer countdown */
 127   #define TIMER_COUNTDOWN_ENABLE        0x01000000UL
 128   /* trigger timer IRQ on zero transition */
 129   #define TIMER_IRQ_ENABLE              0x02000000UL
 130   /* being set in IRQ handler in case port 0x00 (hmm, not port 0x64!?!?)
 131    * had 0x0020 set upon IRQ handler */
 132   #define TIMER_IRQ_ACK                 0x04000000UL
 133 #define IDX_IO_IRQSTATUS        0x64
 134   /* some IRQ bit in here might also be used to signal a power-management timer
 135    * timeout, to request shutdown of the chip (e.g. AD1815JS has such a thing).
 136    * Some OPL3 hardware (e.g. in LM4560) has some special timer hardware which
 137    * can trigger an OPL3 timer IRQ, so maybe there's such a thing as well... */
 138
 139   #define IRQ_PLAYBACK  0x0001
 140   #define IRQ_RECORDING 0x0002
 141   #define IRQ_UNKNOWN1  0x0004 /* most probably I2S port */
 142   #define IRQ_GAMEPORT  0x0008 /* Interrupt of Digital(ly) Enhanced Game Port */
 143   #define IRQ_MPU401    0x0010
 144   #define IRQ_TIMER     0x0020 /* DirectX timer */
 145   #define IRQ_UNKNOWN2  0x0040 /* probably unused, or possibly I2S port? */
 146   #define IRQ_UNKNOWN3  0x0080 /* probably unused, or possibly I2S port? */
 147 #define IDX_IO_66H              0x66    /* writing 0xffff returns 0x0000 */
 148   /* this is set to e.g. 0x3ff or 0x300, and writable;
 149    * maybe some buffer limit, but I couldn't find out more, PU:0x00ff: */
 150 #define IDX_IO_SOME_VALUE       0x68
 151   #define IO_68_RANDOM_TOGGLE1  0x0100  /* toggles randomly */
 152   #define IO_68_RANDOM_TOGGLE2  0x0200  /* toggles randomly */
 153   /* umm, nope, behaviour of these bits changes depending on what we wrote
 154    * to 0x6b!!
 155    * And they change upon playback/stop, too:
 156    * Writing a value to 0x68 will display this exact value during playback,
 157    * too but when stopped it can fall back to a rather different
 158    * seemingly random value). Hmm, possibly this is a register which
 159    * has a remote shadow which needs proper device supply which only exists
 160    * in case playback is active? Or is this driver-induced?
 161    */
 162
 163 /* this WORD can be set to have bits 0x0028 activated (FIXME: correct??);
 164  * actually inhibits PCM playback!!! maybe power management??: */
 165 #define IDX_IO_6AH              0x6A /* WRITE_ONLY! */
 166   /* bit 5: enabling this will activate permanent counting of bytes 2/3
 167    * at gameport I/O (0xb402/3) (equal values each) and cause
 168    * gameport legacy I/O at 0x0200 to be _DISABLED_!
 169    * Is this Digital Enhanced Game Port Enable??? Or maybe it's Testmode
 170    * for Enhanced Digital Gameport (see 4D Wave DX card): */
 171   #define IO_6A_SOMETHING1_GAMEPORT     0x0020
 172   /* bit 8; sure, this _pauses_ playback (later resumes at same spot!),
 173    * but what the heck is this really about??: */
 174   #define IO_6A_PAUSE_PLAYBACK_BIT8     0x0100
 175   /* bit 9; sure, this _pauses_ playback (later resumes at same spot!),
 176    * but what the heck is this really about??: */
 177   #define IO_6A_PAUSE_PLAYBACK_BIT9     0x0200
 178         /* BIT8 and BIT9 are _NOT_ able to affect OPL3 MIDI playback,
 179          * thus it suggests influence on PCM only!!
 180          * However OTOH there seems to be no bit anywhere around here
 181          * which is able to disable OPL3... */
 182   /* bit 10: enabling this actually changes values at legacy gameport
 183    * I/O address (0x200); is this enabling of the Digital Enhanced Game Port???
 184    * Or maybe this simply switches off the NE558 circuit, since enabling this
 185    * still lets us evaluate button states, but not axis states */
 186   #define IO_6A_SOMETHING2_GAMEPORT      0x0400
 187         /* writing 0x0300: causes quite some crackling during
 188          * PC activity such as switching windows (PCI traffic??
 189          * --> FIFO/timing settings???) */
 190         /* writing 0x0100 plus/or 0x0200 inhibits playback */
 191         /* since the Windows .INF file has Flag_Enable_JoyStick and
 192          * Flag_Enable_SB_DOS_Emulation directly together, it stands to reason
 193          * that some other bit in this same register might be responsible
 194          * for SB DOS Emulation activation (note that the file did NOT define
 195          * a switch for OPL3!) */
 196 #define IDX_IO_6CH              0x6C    /* unknown; fully read-writable */
 197 #define IDX_IO_6EH              0x6E
 198         /* writing 0xffff returns 0x83fe (or 0x03fe only).
 199          * writing 0x83 (and only 0x83!!) to 0x6f will cause 0x6c to switch
 200          * from 0000 to ffff. */
 201
 202 /* further I/O indices not saved/restored and not readable after writing,
 203  * so probably not used */
 204
 205
 206 /*** Gameport area port indices ***/
 207 /* (only 0x06 of 0x08 bytes saved/restored by Windows driver) */
 208 #define AZF_IO_SIZE_GAME                0x08
 209 #define AZF_IO_SIZE_GAME_PM     0x06
 210
 211 enum {
 212         AZF_GAME_LEGACY_IO_PORT = 0x200
 213 };
 214
 215 #define IDX_GAME_LEGACY_COMPATIBLE      0x00
 216         /* in some operation mode, writing anything to this port
 217          * triggers an interrupt:
 218          * yup, that's in case IDX_GAME_01H has one of the
 219          * axis measurement bits enabled
 220          * (and of course one needs to have GAME_HWCFG_IRQ_ENABLE, too) */
 221
 222 #define IDX_GAME_AXES_CONFIG            0x01
 223         /* NOTE: layout of this register awfully similar (read: "identical??")
 224          * to AD1815JS.pdf (p.29) */
 225
 226   /* enables axis 1 (X axis) measurement: */
 227   #define GAME_AXES_ENABLE_1            0x01
 228   /* enables axis 2 (Y axis) measurement: */
 229   #define GAME_AXES_ENABLE_2            0x02
 230   /* enables axis 3 (X axis) measurement: */
 231   #define GAME_AXES_ENABLE_3            0x04
 232   /* enables axis 4 (Y axis) measurement: */
 233   #define GAME_AXES_ENABLE_4            0x08
 234   /* selects the current axis to read the measured value of
 235    * (at IDX_GAME_AXIS_VALUE):
 236    * 00 = axis 1, 01 = axis 2, 10 = axis 3, 11 = axis 4: */
 237   #define GAME_AXES_READ_MASK           0x30
 238   /* enable to have the latch continuously accept ADC values
 239    * (and continuously cause interrupts in case interrupts are enabled);
 240    * AD1815JS.pdf says it's ~16ms interval there: */
 241   #define GAME_AXES_LATCH_ENABLE        0x40
 242   /* joystick data (measured axes) ready for reading: */
 243   #define GAME_AXES_SAMPLING_READY      0x80
 244
 245   /* NOTE: other card specs (SiS960 and others!) state that the
 246    * game position latches should be frozen when reading and be freed
 247    * (== reset?) after reading!!!
 248    * Freezing most likely means disabling 0x40 (GAME_AXES_LATCH_ENABLE),
 249    *  but how to free the value? */
 250   /* An internet search for "gameport latch ADC" should provide some insight
 251    * into how to program such a gameport system. */
 252
 253   /* writing 0xf0 to 01H once reset both counters to 0, in some special mode!?
 254    * yup, in case 6AH 0x20 is not enabled
 255    * (and 0x40 is sufficient, 0xf0 is not needed) */
 256
 257 #define IDX_GAME_AXIS_VALUE     0x02
 258         /* R: value of currently configured axis (word value!);
 259          * W: trigger axis measurement */
 260
 261 #define IDX_GAME_HWCONFIG       0x04
 262         /* note: bits 4 to 7 are never set (== 0) when reading!
 263          * --> reserved bits? */
 264   /* enables IRQ notification upon axes measurement ready: */
 265   #define GAME_HWCFG_IRQ_ENABLE                 0x01
 266   /* these bits choose a different frequency for the
 267    *  internal ADC counter increment.
 268    * hmm, seems to be a combo of bits:
 269    * 00 --> standard frequency
 270    * 10 --> 1/2
 271    * 01 --> 1/20
 272    * 11 --> 1/200: */
 273   #define GAME_HWCFG_ADC_COUNTER_FREQ_MASK      0x06
 274
 275   /* enable gameport legacy I/O address (0x200)
 276    * I was unable to locate any configurability for a different address: */
 277   #define GAME_HWCFG_LEGACY_ADDRESS_ENABLE      0x08
 278
 279 /*** MPU401 ***/
 280 #define AZF_IO_SIZE_MPU         0x04
 281 #define AZF_IO_SIZE_MPU_PM      0x04
 282
 283 /*** OPL3 synth ***/
 284 #define AZF_IO_SIZE_OPL3        0x08
 285 #define AZF_IO_SIZE_OPL3_PM     0x06
 286 /* hmm, given that a standard OPL3 has 4 registers only,
 287  * there might be some enhanced functionality lurking at the end
 288  * (especially since register 0x04 has a "non-empty" value 0xfe) */
 289
 290 /*** mixer I/O area port indices ***/
 291 /* (only 0x22 of 0x40 bytes saved/restored by Windows driver)
 292  * UNFORTUNATELY azf3328 is NOT truly AC97 compliant: see main file intro */
 293 #define AZF_IO_SIZE_MIXER       0x40
 294 #define AZF_IO_SIZE_MIXER_PM    0x22
 295
 296   #define MIXER_VOLUME_RIGHT_MASK       0x001f
 297   #define MIXER_VOLUME_LEFT_MASK        0x1f00
 298   #define MIXER_MUTE_MASK               0x8000
 299 #define IDX_MIXER_RESET         0x00 /* does NOT seem to have AC97 ID bits */
 300 #define IDX_MIXER_PLAY_MASTER   0x02
 301 #define IDX_MIXER_MODEMOUT      0x04
 302 #define IDX_MIXER_BASSTREBLE    0x06
 303   #define MIXER_BASSTREBLE_TREBLE_VOLUME_MASK   0x000e
 304   #define MIXER_BASSTREBLE_BASS_VOLUME_MASK     0x0e00
 305 #define IDX_MIXER_PCBEEP        0x08
 306 #define IDX_MIXER_MODEMIN       0x0a
 307 #define IDX_MIXER_MIC           0x0c
 308   #define MIXER_MIC_MICGAIN_20DB_ENHANCEMENT_MASK       0x0040
 309 #define IDX_MIXER_LINEIN        0x0e
 310 #define IDX_MIXER_CDAUDIO       0x10
 311 #define IDX_MIXER_VIDEO         0x12
 312 #define IDX_MIXER_AUX           0x14
 313 #define IDX_MIXER_WAVEOUT       0x16
 314 #define IDX_MIXER_FMSYNTH       0x18
 315 #define IDX_MIXER_REC_SELECT    0x1a
 316   #define MIXER_REC_SELECT_MIC          0x00
 317   #define MIXER_REC_SELECT_CD           0x01
 318   #define MIXER_REC_SELECT_VIDEO        0x02
 319   #define MIXER_REC_SELECT_AUX          0x03
 320   #define MIXER_REC_SELECT_LINEIN       0x04
 321   #define MIXER_REC_SELECT_MIXSTEREO    0x05
 322   #define MIXER_REC_SELECT_MIXMONO      0x06
 323   #define MIXER_REC_SELECT_MONOIN       0x07
 324 #define IDX_MIXER_REC_VOLUME    0x1c
 325 #define IDX_MIXER_ADVCTL1       0x1e
 326   /* unlisted bits are unmodifiable */
 327   #define MIXER_ADVCTL1_3DWIDTH_MASK    0x000e
 328   #define MIXER_ADVCTL1_HIFI3D_MASK     0x0300 /* yup, this is missing the high bit that official AC97 contains, plus it doesn't have linear bit value range behaviour but instead acts weirdly (possibly we're dealing with two *different* 3D settings here??) */
 329 #define IDX_MIXER_ADVCTL2       0x20 /* subset of AC97_GENERAL_PURPOSE reg! */
 330   /* unlisted bits are unmodifiable */
 331   #define MIXER_ADVCTL2_LPBK            0x0080 /* Loopback mode -- Win driver: "WaveOut3DBypass"? mutes WaveOut at LineOut */
 332   #define MIXER_ADVCTL2_MS              0x0100 /* Mic Select 0=Mic1, 1=Mic2 -- Win driver: "ModemOutSelect"?? */
 333   #define MIXER_ADVCTL2_MIX             0x0200 /* Mono output select 0=Mix, 1=Mic; Win driver: "MonoSelectSource"?? */
 334   #define MIXER_ADVCTL2_3D              0x2000 /* 3D Enhancement 1=on */
 335   #define MIXER_ADVCTL2_POP             0x8000 /* Pcm Out Path, 0=pre 3D, 1=post 3D */
 336
 337 #define IDX_MIXER_SOMETHING30H  0x30 /* used, but unknown??? */
 338
 339 /* driver internal flags */
 340 #define SET_CHAN_LEFT   1
 341 #define SET_CHAN_RIGHT  2
 342
 343 #endif /* __SOUND_AZT3328_H  */