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Linux 2.6.31.8
[linux/fpc-iii.git] / sound / pci / oxygen / oxygen_lib.c
blob9a8936e207448e792218d1c3aee804fb09db30e6
1 /*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
30 #include "oxygen.h"
31 #include "cm9780.h"
32
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL v2");
36
37 #define DRIVER "oxygen"
38
39 static inline int oxygen_uart_input_ready(struct oxygen *chip)
40 {
41 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY);
42 }
43
44 static void oxygen_read_uart(struct oxygen *chip)
45 {
46 if (unlikely(!oxygen_uart_input_ready(chip))) {
47 /* no data, but read it anyway to clear the interrupt */
48 oxygen_read8(chip, OXYGEN_MPU401);
49 return;
50 }
51 do {
52 u8 data = oxygen_read8(chip, OXYGEN_MPU401);
53 if (data == MPU401_ACK)
54 continue;
55 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input))
56 chip->uart_input_count = 0;
57 chip->uart_input[chip->uart_input_count++] = data;
58 } while (oxygen_uart_input_ready(chip));
59 if (chip->model.uart_input)
60 chip->model.uart_input(chip);
61 }
62
63 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
64 {
65 struct oxygen *chip = dev_id;
66 unsigned int status, clear, elapsed_streams, i;
67
68 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
69 if (!status)
70 return IRQ_NONE;
71
72 spin_lock(&chip->reg_lock);
73
74 clear = status & (OXYGEN_CHANNEL_A |
75 OXYGEN_CHANNEL_B |
76 OXYGEN_CHANNEL_C |
77 OXYGEN_CHANNEL_SPDIF |
78 OXYGEN_CHANNEL_MULTICH |
79 OXYGEN_CHANNEL_AC97 |
80 OXYGEN_INT_SPDIF_IN_DETECT |
81 OXYGEN_INT_GPIO |
82 OXYGEN_INT_AC97);
83 if (clear) {
84 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
85 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
86 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
87 chip->interrupt_mask & ~clear);
88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
89 chip->interrupt_mask);
90 }
91
92 elapsed_streams = status & chip->pcm_running;
93
94 spin_unlock(&chip->reg_lock);
95
96 for (i = 0; i < PCM_COUNT; ++i)
97 if ((elapsed_streams & (1 << i)) && chip->streams[i])
98 snd_pcm_period_elapsed(chip->streams[i]);
99
100 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
101 spin_lock(&chip->reg_lock);
102 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
103 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
104 OXYGEN_SPDIF_RATE_INT)) {
105 /* write the interrupt bit(s) to clear */
106 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
107 schedule_work(&chip->spdif_input_bits_work);
108 }
109 spin_unlock(&chip->reg_lock);
110 }
111
112 if (status & OXYGEN_INT_GPIO)
113 schedule_work(&chip->gpio_work);
114
115 if (status & OXYGEN_INT_MIDI) {
116 if (chip->midi)
117 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
118 else
119 oxygen_read_uart(chip);
120 }
121
122 if (status & OXYGEN_INT_AC97)
123 wake_up(&chip->ac97_waitqueue);
124
125 return IRQ_HANDLED;
126 }
127
128 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
129 {
130 struct oxygen *chip = container_of(work, struct oxygen,
131 spdif_input_bits_work);
132 u32 reg;
133
134 /*
135 * This function gets called when there is new activity on the SPDIF
136 * input, or when we lose lock on the input signal, or when the rate
137 * changes.
138 */
139 msleep(1);
140 spin_lock_irq(&chip->reg_lock);
141 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
142 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
143 OXYGEN_SPDIF_LOCK_STATUS))
144 == OXYGEN_SPDIF_SENSE_STATUS) {
145 /*
146 * If we detect activity on the SPDIF input but cannot lock to
147 * a signal, the clock bit is likely to be wrong.
148 */
149 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
150 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
151 spin_unlock_irq(&chip->reg_lock);
152 msleep(1);
153 spin_lock_irq(&chip->reg_lock);
154 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
155 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
156 OXYGEN_SPDIF_LOCK_STATUS))
157 == OXYGEN_SPDIF_SENSE_STATUS) {
158 /* nothing detected with either clock; give up */
159 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
160 == OXYGEN_SPDIF_IN_CLOCK_192) {
161 /*
162 * Reset clock to <= 96 kHz because this is
163 * more likely to be received next time.
164 */
165 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
166 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
167 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
168 }
169 }
170 }
171 spin_unlock_irq(&chip->reg_lock);
172
173 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
174 spin_lock_irq(&chip->reg_lock);
175 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
176 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
177 chip->interrupt_mask);
178 spin_unlock_irq(&chip->reg_lock);
179
180 /*
181 * We don't actually know that any channel status bits have
182 * changed, but let's send a notification just to be sure.
183 */
184 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
185 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
186 }
187 }
188
189 static void oxygen_gpio_changed(struct work_struct *work)
190 {
191 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
192
193 if (chip->model.gpio_changed)
194 chip->model.gpio_changed(chip);
195 }
196
197 #ifdef CONFIG_PROC_FS
198 static void oxygen_proc_read(struct snd_info_entry *entry,
199 struct snd_info_buffer *buffer)
200 {
201 struct oxygen *chip = entry->private_data;
202 int i, j;
203
204 snd_iprintf(buffer, "CMI8788\n\n");
205 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) {
206 snd_iprintf(buffer, "%02x:", i);
207 for (j = 0; j < 0x10; ++j)
208 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
209 snd_iprintf(buffer, "\n");
210 }
211 if (mutex_lock_interruptible(&chip->mutex) < 0)
212 return;
213 if (chip->has_ac97_0) {
214 snd_iprintf(buffer, "\nAC97\n");
215 for (i = 0; i < 0x80; i += 0x10) {
216 snd_iprintf(buffer, "%02x:", i);
217 for (j = 0; j < 0x10; j += 2)
218 snd_iprintf(buffer, " %04x",
219 oxygen_read_ac97(chip, 0, i + j));
220 snd_iprintf(buffer, "\n");
221 }
222 }
223 if (chip->has_ac97_1) {
224 snd_iprintf(buffer, "\nAC97 2\n");
225 for (i = 0; i < 0x80; i += 0x10) {
226 snd_iprintf(buffer, "%02x:", i);
227 for (j = 0; j < 0x10; j += 2)
228 snd_iprintf(buffer, " %04x",
229 oxygen_read_ac97(chip, 1, i + j));
230 snd_iprintf(buffer, "\n");
231 }
232 }
233 mutex_unlock(&chip->mutex);
234 }
235
236 static void oxygen_proc_init(struct oxygen *chip)
237 {
238 struct snd_info_entry *entry;
239
240 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
241 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
242 }
243 #else
244 #define oxygen_proc_init(chip)
245 #endif
246
247 static const struct pci_device_id *
248 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[])
249 {
250 u16 subdevice;
251
252 /*
253 * Make sure the EEPROM pins are available, i.e., not used for SPI.
254 * (This function is called before we initialize or use SPI.)
255 */
256 oxygen_clear_bits8(chip, OXYGEN_FUNCTION,
257 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
258 /*
259 * Read the subsystem device ID directly from the EEPROM, because the
260 * chip didn't if the first EEPROM word was overwritten.
261 */
262 subdevice = oxygen_read_eeprom(chip, 2);
263 /* use default ID if EEPROM is missing */
264 if (subdevice == 0xffff)
265 subdevice = 0x8788;
266 /*
267 * We use only the subsystem device ID for searching because it is
268 * unique even without the subsystem vendor ID, which may have been
269 * overwritten in the EEPROM.
270 */
271 for (; ids->vendor; ++ids)
272 if (ids->subdevice == subdevice &&
273 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA)
274 return ids;
275 return NULL;
276 }
277
278 static void oxygen_restore_eeprom(struct oxygen *chip,
279 const struct pci_device_id *id)
280 {
281 if (oxygen_read_eeprom(chip, 0) != OXYGEN_EEPROM_ID) {
282 /*
283 * This function gets called only when a known card model has
284 * been detected, i.e., we know there is a valid subsystem
285 * product ID at index 2 in the EEPROM. Therefore, we have
286 * been able to deduce the correct subsystem vendor ID, and
287 * this is enough information to restore the original EEPROM
288 * contents.
289 */
290 oxygen_write_eeprom(chip, 1, id->subvendor);
291 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID);
292
293 oxygen_set_bits8(chip, OXYGEN_MISC,
294 OXYGEN_MISC_WRITE_PCI_SUBID);
295 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID,
296 id->subvendor);
297 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID,
298 id->subdevice);
299 oxygen_clear_bits8(chip, OXYGEN_MISC,
300 OXYGEN_MISC_WRITE_PCI_SUBID);
301
302 snd_printk(KERN_INFO "EEPROM ID restored\n");
303 }
304 }
305
306 static void oxygen_init(struct oxygen *chip)
307 {
308 unsigned int i;
309
310 chip->dac_routing = 1;
311 for (i = 0; i < 8; ++i)
312 chip->dac_volume[i] = chip->model.dac_volume_min;
313 chip->dac_mute = 1;
314 chip->spdif_playback_enable = 1;
315 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
316 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
317 chip->spdif_pcm_bits = chip->spdif_bits;
318
319 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
320 chip->revision = 2;
321 else
322 chip->revision = 1;
323
324 if (chip->revision == 1)
325 oxygen_set_bits8(chip, OXYGEN_MISC,
326 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
327
328 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
329 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
330 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
331
332 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
333 OXYGEN_FUNCTION_RESET_CODEC |
334 chip->model.function_flags,
335 OXYGEN_FUNCTION_RESET_CODEC |
336 OXYGEN_FUNCTION_2WIRE_SPI_MASK |
337 OXYGEN_FUNCTION_ENABLE_SPI_4_5);
338 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
339 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
340 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
341 OXYGEN_PLAY_CHANNELS_2 |
342 OXYGEN_DMA_A_BURST_8 |
343 OXYGEN_DMA_MULTICH_BURST_8);
344 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
345 oxygen_write8_masked(chip, OXYGEN_MISC,
346 chip->model.misc_flags,
347 OXYGEN_MISC_WRITE_PCI_SUBID |
348 OXYGEN_MISC_REC_C_FROM_SPDIF |
349 OXYGEN_MISC_REC_B_FROM_AC97 |
350 OXYGEN_MISC_REC_A_FROM_MULTICH |
351 OXYGEN_MISC_MIDI);
352 oxygen_write8(chip, OXYGEN_REC_FORMAT,
353 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
354 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
355 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
356 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
357 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
358 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
359 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
360 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
361 OXYGEN_RATE_48000 | chip->model.dac_i2s_format |
362 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
363 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
364 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
365 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
366 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
367 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
368 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
369 else
370 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
371 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
372 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 |
373 CAPTURE_2_FROM_I2S_2))
374 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
375 OXYGEN_RATE_48000 | chip->model.adc_i2s_format |
376 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 |
377 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
378 else
379 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
380 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
381 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
382 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK);
383 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
384 OXYGEN_SPDIF_OUT_ENABLE |
385 OXYGEN_SPDIF_LOOPBACK);
386 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
387 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
388 OXYGEN_SPDIF_SENSE_MASK |
389 OXYGEN_SPDIF_LOCK_MASK |
390 OXYGEN_SPDIF_RATE_MASK |
391 OXYGEN_SPDIF_LOCK_PAR |
392 OXYGEN_SPDIF_IN_CLOCK_96,
393 OXYGEN_SPDIF_SENSE_MASK |
394 OXYGEN_SPDIF_LOCK_MASK |
395 OXYGEN_SPDIF_RATE_MASK |
396 OXYGEN_SPDIF_SENSE_PAR |
397 OXYGEN_SPDIF_LOCK_PAR |
398 OXYGEN_SPDIF_IN_CLOCK_MASK);
399 else
400 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
401 OXYGEN_SPDIF_SENSE_MASK |
402 OXYGEN_SPDIF_LOCK_MASK |
403 OXYGEN_SPDIF_RATE_MASK);
404 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
405 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS,
406 OXYGEN_2WIRE_LENGTH_8 |
407 OXYGEN_2WIRE_INTERRUPT_MASK |
408 OXYGEN_2WIRE_SPEED_STANDARD);
409 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
410 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
411 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
412 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
413 OXYGEN_PLAY_MULTICH_I2S_DAC |
414 OXYGEN_PLAY_SPDIF_SPDIF |
415 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
416 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
417 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
418 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
419 oxygen_write8(chip, OXYGEN_REC_ROUTING,
420 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
421 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
422 OXYGEN_REC_C_ROUTE_SPDIF);
423 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
424 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
425 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
426 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
427 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
428 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
429
430 if (chip->has_ac97_0 | chip->has_ac97_1)
431 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
432 OXYGEN_AC97_INT_READ_DONE |
433 OXYGEN_AC97_INT_WRITE_DONE);
434 else
435 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0);
436 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
437 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
438 if (!(chip->has_ac97_0 | chip->has_ac97_1))
439 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
440 OXYGEN_AC97_CLOCK_DISABLE);
441 if (!chip->has_ac97_0) {
442 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
443 OXYGEN_AC97_NO_CODEC_0);
444 } else {
445 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
446 msleep(1);
447 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
448 CM9780_GPIO0IO | CM9780_GPIO1IO);
449 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
450 CM9780_BSTSEL | CM9780_STRO_MIC |
451 CM9780_MIX2FR | CM9780_PCBSW);
452 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
453 CM9780_RSOE | CM9780_CBOE |
454 CM9780_SSOE | CM9780_FROE |
455 CM9780_MIC2MIC | CM9780_LI2LI);
456 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
457 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
458 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
459 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
460 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
461 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
462 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
463 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
464 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
465 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
466 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS,
467 CM9780_GPO0);
468 /* power down unused ADCs and DACs */
469 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
470 AC97_PD_PR0 | AC97_PD_PR1);
471 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
472 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
473 }
474 if (chip->has_ac97_1) {
475 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
476 OXYGEN_AC97_CODEC1_SLOT3 |
477 OXYGEN_AC97_CODEC1_SLOT4);
478 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
479 msleep(1);
480 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
481 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
482 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
483 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
484 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
485 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
486 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
487 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
488 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
489 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
490 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
491 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
492 }
493 }
494
495 static void oxygen_card_free(struct snd_card *card)
496 {
497 struct oxygen *chip = card->private_data;
498
499 spin_lock_irq(&chip->reg_lock);
500 chip->interrupt_mask = 0;
501 chip->pcm_running = 0;
502 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
503 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
504 spin_unlock_irq(&chip->reg_lock);
505 if (chip->irq >= 0)
506 free_irq(chip->irq, chip);
507 flush_scheduled_work();
508 chip->model.cleanup(chip);
509 kfree(chip->model_data);
510 mutex_destroy(&chip->mutex);
511 pci_release_regions(chip->pci);
512 pci_disable_device(chip->pci);
513 }
514
515 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
516 struct module *owner,
517 const struct pci_device_id *ids,
518 int (*get_model)(struct oxygen *chip,
519 const struct pci_device_id *id
520 )
521 )
522 {
523 struct snd_card *card;
524 struct oxygen *chip;
525 const struct pci_device_id *pci_id;
526 int err;
527
528 err = snd_card_create(index, id, owner, sizeof(*chip), &card);
529 if (err < 0)
530 return err;
531
532 chip = card->private_data;
533 chip->card = card;
534 chip->pci = pci;
535 chip->irq = -1;
536 spin_lock_init(&chip->reg_lock);
537 mutex_init(&chip->mutex);
538 INIT_WORK(&chip->spdif_input_bits_work,
539 oxygen_spdif_input_bits_changed);
540 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
541 init_waitqueue_head(&chip->ac97_waitqueue);
542
543 err = pci_enable_device(pci);
544 if (err < 0)
545 goto err_card;
546
547 err = pci_request_regions(pci, DRIVER);
548 if (err < 0) {
549 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
550 goto err_pci_enable;
551 }
552
553 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
554 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) {
555 snd_printk(KERN_ERR "invalid PCI I/O range\n");
556 err = -ENXIO;
557 goto err_pci_regions;
558 }
559 chip->addr = pci_resource_start(pci, 0);
560
561 pci_id = oxygen_search_pci_id(chip, ids);
562 if (!pci_id) {
563 err = -ENODEV;
564 goto err_pci_regions;
565 }
566 oxygen_restore_eeprom(chip, pci_id);
567 err = get_model(chip, pci_id);
568 if (err < 0)
569 goto err_pci_regions;
570
571 if (chip->model.model_data_size) {
572 chip->model_data = kzalloc(chip->model.model_data_size,
573 GFP_KERNEL);
574 if (!chip->model_data) {
575 err = -ENOMEM;
576 goto err_pci_regions;
577 }
578 }
579
580 pci_set_master(pci);
581 snd_card_set_dev(card, &pci->dev);
582 card->private_free = oxygen_card_free;
583
584 oxygen_init(chip);
585 chip->model.init(chip);
586
587 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
588 DRIVER, chip);
589 if (err < 0) {
590 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
591 goto err_card;
592 }
593 chip->irq = pci->irq;
594
595 strcpy(card->driver, chip->model.chip);
596 strcpy(card->shortname, chip->model.shortname);
597 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
598 chip->model.longname, chip->revision, chip->addr, chip->irq);
599 strcpy(card->mixername, chip->model.chip);
600 snd_component_add(card, chip->model.chip);
601
602 err = oxygen_pcm_init(chip);
603 if (err < 0)
604 goto err_card;
605
606 err = oxygen_mixer_init(chip);
607 if (err < 0)
608 goto err_card;
609
610 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) {
611 unsigned int info_flags = MPU401_INFO_INTEGRATED;
612 if (chip->model.device_config & MIDI_OUTPUT)
613 info_flags |= MPU401_INFO_OUTPUT;
614 if (chip->model.device_config & MIDI_INPUT)
615 info_flags |= MPU401_INFO_INPUT;
616 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
617 chip->addr + OXYGEN_MPU401,
618 info_flags, 0, 0,
619 &chip->midi);
620 if (err < 0)
621 goto err_card;
622 }
623
624 oxygen_proc_init(chip);
625
626 spin_lock_irq(&chip->reg_lock);
627 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF)
628 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
629 if (chip->has_ac97_0 | chip->has_ac97_1)
630 chip->interrupt_mask |= OXYGEN_INT_AC97;
631 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
632 spin_unlock_irq(&chip->reg_lock);
633
634 err = snd_card_register(card);
635 if (err < 0)
636 goto err_card;
637
638 pci_set_drvdata(pci, card);
639 return 0;
640
641 err_pci_regions:
642 pci_release_regions(pci);
643 err_pci_enable:
644 pci_disable_device(pci);
645 err_card:
646 snd_card_free(card);
647 return err;
648 }
649 EXPORT_SYMBOL(oxygen_pci_probe);
650
651 void oxygen_pci_remove(struct pci_dev *pci)
652 {
653 snd_card_free(pci_get_drvdata(pci));
654 pci_set_drvdata(pci, NULL);
655 }
656 EXPORT_SYMBOL(oxygen_pci_remove);
657
658 #ifdef CONFIG_PM
659 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state)
660 {
661 struct snd_card *card = pci_get_drvdata(pci);
662 struct oxygen *chip = card->private_data;
663 unsigned int i, saved_interrupt_mask;
664
665 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
666
667 for (i = 0; i < PCM_COUNT; ++i)
668 if (chip->streams[i])
669 snd_pcm_suspend(chip->streams[i]);
670
671 if (chip->model.suspend)
672 chip->model.suspend(chip);
673
674 spin_lock_irq(&chip->reg_lock);
675 saved_interrupt_mask = chip->interrupt_mask;
676 chip->interrupt_mask = 0;
677 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
678 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
679 spin_unlock_irq(&chip->reg_lock);
680
681 synchronize_irq(chip->irq);
682 flush_scheduled_work();
683 chip->interrupt_mask = saved_interrupt_mask;
684
685 pci_disable_device(pci);
686 pci_save_state(pci);
687 pci_set_power_state(pci, pci_choose_state(pci, state));
688 return 0;
689 }
690 EXPORT_SYMBOL(oxygen_pci_suspend);
691
692 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = {
693 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff,
694 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000
695 };
696 static const u32 ac97_registers_to_restore[2][0x40 / 32] = {
697 { 0x18284fa2, 0x03060000 },
698 { 0x00007fa6, 0x00200000 }
699 };
700
701 static inline int is_bit_set(const u32 *bitmap, unsigned int bit)
702 {
703 return bitmap[bit / 32] & (1 << (bit & 31));
704 }
705
706 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec)
707 {
708 unsigned int i;
709
710 oxygen_write_ac97(chip, codec, AC97_RESET, 0);
711 msleep(1);
712 for (i = 1; i < 0x40; ++i)
713 if (is_bit_set(ac97_registers_to_restore[codec], i))
714 oxygen_write_ac97(chip, codec, i * 2,
715 chip->saved_ac97_registers[codec][i]);
716 }
717
718 int oxygen_pci_resume(struct pci_dev *pci)
719 {
720 struct snd_card *card = pci_get_drvdata(pci);
721 struct oxygen *chip = card->private_data;
722 unsigned int i;
723
724 pci_set_power_state(pci, PCI_D0);
725 pci_restore_state(pci);
726 if (pci_enable_device(pci) < 0) {
727 snd_printk(KERN_ERR "cannot reenable device");
728 snd_card_disconnect(card);
729 return -EIO;
730 }
731 pci_set_master(pci);
732
733 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
734 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
735 for (i = 0; i < OXYGEN_IO_SIZE; ++i)
736 if (is_bit_set(registers_to_restore, i))
737 oxygen_write8(chip, i, chip->saved_registers._8[i]);
738 if (chip->has_ac97_0)
739 oxygen_restore_ac97(chip, 0);
740 if (chip->has_ac97_1)
741 oxygen_restore_ac97(chip, 1);
742
743 if (chip->model.resume)
744 chip->model.resume(chip);
745
746 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
747
748 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
749 return 0;
750 }
751 EXPORT_SYMBOL(oxygen_pci_resume);
752 #endif /* CONFIG_PM */
Linux with added FPC-III support