sound/pci/oxygen/oxygen_pcm.c

   1 /*
   2  * C-Media CMI8788 driver - PCM code
   3  *
   4  * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
   5  *
   6  *
   7  *  This driver is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License, version 2.
   9  *
  10  *  This driver is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this driver; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #include <linux/pci.h>
  21 #include <sound/control.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include "oxygen.h"
  26
  27 /* most DMA channels have a 16-bit counter for 32-bit words */
  28 #define BUFFER_BYTES_MAX                ((1 << 16) * 4)
  29 /* the multichannel DMA channel has a 24-bit counter */
  30 #define BUFFER_BYTES_MAX_MULTICH        ((1 << 24) * 4)
  31
  32 #define PERIOD_BYTES_MIN                64
  33
  34 #define DEFAULT_BUFFER_BYTES            (BUFFER_BYTES_MAX / 2)
  35 #define DEFAULT_BUFFER_BYTES_MULTICH    (1024 * 1024)
  36
  37 static const struct snd_pcm_hardware oxygen_stereo_hardware = {
  38         .info = SNDRV_PCM_INFO_MMAP |
  39                 SNDRV_PCM_INFO_MMAP_VALID |
  40                 SNDRV_PCM_INFO_INTERLEAVED |
  41                 SNDRV_PCM_INFO_PAUSE |
  42                 SNDRV_PCM_INFO_SYNC_START,
  43         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  44                    SNDRV_PCM_FMTBIT_S32_LE,
  45         .rates = SNDRV_PCM_RATE_32000 |
  46                  SNDRV_PCM_RATE_44100 |
  47                  SNDRV_PCM_RATE_48000 |
  48                  SNDRV_PCM_RATE_64000 |
  49                  SNDRV_PCM_RATE_88200 |
  50                  SNDRV_PCM_RATE_96000 |
  51                  SNDRV_PCM_RATE_176400 |
  52                  SNDRV_PCM_RATE_192000,
  53         .rate_min = 32000,
  54         .rate_max = 192000,
  55         .channels_min = 2,
  56         .channels_max = 2,
  57         .buffer_bytes_max = BUFFER_BYTES_MAX,
  58         .period_bytes_min = PERIOD_BYTES_MIN,
  59         .period_bytes_max = BUFFER_BYTES_MAX / 2,
  60         .periods_min = 2,
  61         .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
  62 };
  63 static const struct snd_pcm_hardware oxygen_multichannel_hardware = {
  64         .info = SNDRV_PCM_INFO_MMAP |
  65                 SNDRV_PCM_INFO_MMAP_VALID |
  66                 SNDRV_PCM_INFO_INTERLEAVED |
  67                 SNDRV_PCM_INFO_PAUSE |
  68                 SNDRV_PCM_INFO_SYNC_START,
  69         .formats = SNDRV_PCM_FMTBIT_S16_LE |
  70                    SNDRV_PCM_FMTBIT_S32_LE,
  71         .rates = SNDRV_PCM_RATE_32000 |
  72                  SNDRV_PCM_RATE_44100 |
  73                  SNDRV_PCM_RATE_48000 |
  74                  SNDRV_PCM_RATE_64000 |
  75                  SNDRV_PCM_RATE_88200 |
  76                  SNDRV_PCM_RATE_96000 |
  77                  SNDRV_PCM_RATE_176400 |
  78                  SNDRV_PCM_RATE_192000,
  79         .rate_min = 32000,
  80         .rate_max = 192000,
  81         .channels_min = 2,
  82         .channels_max = 8,
  83         .buffer_bytes_max = BUFFER_BYTES_MAX_MULTICH,
  84         .period_bytes_min = PERIOD_BYTES_MIN,
  85         .period_bytes_max = BUFFER_BYTES_MAX_MULTICH / 2,
  86         .periods_min = 2,
  87         .periods_max = BUFFER_BYTES_MAX_MULTICH / PERIOD_BYTES_MIN,
  88 };
  89 static const struct snd_pcm_hardware oxygen_ac97_hardware = {
  90         .info = SNDRV_PCM_INFO_MMAP |
  91                 SNDRV_PCM_INFO_MMAP_VALID |
  92                 SNDRV_PCM_INFO_INTERLEAVED |
  93                 SNDRV_PCM_INFO_PAUSE |
  94                 SNDRV_PCM_INFO_SYNC_START,
  95         .formats = SNDRV_PCM_FMTBIT_S16_LE,
  96         .rates = SNDRV_PCM_RATE_48000,
  97         .rate_min = 48000,
  98         .rate_max = 48000,
  99         .channels_min = 2,
 100         .channels_max = 2,
 101         .buffer_bytes_max = BUFFER_BYTES_MAX,
 102         .period_bytes_min = PERIOD_BYTES_MIN,
 103         .period_bytes_max = BUFFER_BYTES_MAX / 2,
 104         .periods_min = 2,
 105         .periods_max = BUFFER_BYTES_MAX / PERIOD_BYTES_MIN,
 106 };
 107
 108 static const struct snd_pcm_hardware *const oxygen_hardware[PCM_COUNT] = {
 109         [PCM_A] = &oxygen_stereo_hardware,
 110         [PCM_B] = &oxygen_stereo_hardware,
 111         [PCM_C] = &oxygen_stereo_hardware,
 112         [PCM_SPDIF] = &oxygen_stereo_hardware,
 113         [PCM_MULTICH] = &oxygen_multichannel_hardware,
 114         [PCM_AC97] = &oxygen_ac97_hardware,
 115 };
 116
 117 static inline unsigned int
 118 oxygen_substream_channel(struct snd_pcm_substream *substream)
 119 {
 120         return (unsigned int)(uintptr_t)substream->runtime->private_data;
 121 }
 122
 123 static int oxygen_open(struct snd_pcm_substream *substream,
 124                        unsigned int channel)
 125 {
 126         struct oxygen *chip = snd_pcm_substream_chip(substream);
 127         struct snd_pcm_runtime *runtime = substream->runtime;
 128         int err;
 129
 130         runtime->private_data = (void *)(uintptr_t)channel;
 131         if (channel == PCM_B && chip->has_ac97_1 &&
 132             (chip->model.device_config & CAPTURE_2_FROM_AC97_1))
 133                 runtime->hw = oxygen_ac97_hardware;
 134         else
 135                 runtime->hw = *oxygen_hardware[channel];
 136         switch (channel) {
 137         case PCM_C:
 138                 runtime->hw.rates &= ~(SNDRV_PCM_RATE_32000 |
 139                                        SNDRV_PCM_RATE_64000);
 140                 runtime->hw.rate_min = 44100;
 141                 break;
 142         case PCM_MULTICH:
 143                 runtime->hw.channels_max = chip->model.dac_channels;
 144                 break;
 145         }
 146         if (chip->model.pcm_hardware_filter)
 147                 chip->model.pcm_hardware_filter(channel, &runtime->hw);
 148         err = snd_pcm_hw_constraint_step(runtime, 0,
 149                                          SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32);
 150         if (err < 0)
 151                 return err;
 152         err = snd_pcm_hw_constraint_step(runtime, 0,
 153                                          SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32);
 154         if (err < 0)
 155                 return err;
 156         if (runtime->hw.formats & SNDRV_PCM_FMTBIT_S32_LE) {
 157                 err = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
 158                 if (err < 0)
 159                         return err;
 160         }
 161         if (runtime->hw.channels_max > 2) {
 162                 err = snd_pcm_hw_constraint_step(runtime, 0,
 163                                                  SNDRV_PCM_HW_PARAM_CHANNELS,
 164                                                  2);
 165                 if (err < 0)
 166                         return err;
 167         }
 168         if (channel == PCM_MULTICH) {
 169                 err = snd_pcm_hw_constraint_minmax
 170                         (runtime, SNDRV_PCM_HW_PARAM_PERIOD_TIME, 0, 8192000);
 171                 if (err < 0)
 172                         return err;
 173         }
 174         snd_pcm_set_sync(substream);
 175         chip->streams[channel] = substream;
 176
 177         mutex_lock(&chip->mutex);
 178         chip->pcm_active |= 1 << channel;
 179         if (channel == PCM_SPDIF) {
 180                 chip->spdif_pcm_bits = chip->spdif_bits;
 181                 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access &=
 182                         ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
 183                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
 184                                SNDRV_CTL_EVENT_MASK_INFO,
 185                                &chip->controls[CONTROL_SPDIF_PCM]->id);
 186         }
 187         mutex_unlock(&chip->mutex);
 188
 189         return 0;
 190 }
 191
 192 static int oxygen_rec_a_open(struct snd_pcm_substream *substream)
 193 {
 194         return oxygen_open(substream, PCM_A);
 195 }
 196
 197 static int oxygen_rec_b_open(struct snd_pcm_substream *substream)
 198 {
 199         return oxygen_open(substream, PCM_B);
 200 }
 201
 202 static int oxygen_rec_c_open(struct snd_pcm_substream *substream)
 203 {
 204         return oxygen_open(substream, PCM_C);
 205 }
 206
 207 static int oxygen_spdif_open(struct snd_pcm_substream *substream)
 208 {
 209         return oxygen_open(substream, PCM_SPDIF);
 210 }
 211
 212 static int oxygen_multich_open(struct snd_pcm_substream *substream)
 213 {
 214         return oxygen_open(substream, PCM_MULTICH);
 215 }
 216
 217 static int oxygen_ac97_open(struct snd_pcm_substream *substream)
 218 {
 219         return oxygen_open(substream, PCM_AC97);
 220 }
 221
 222 static int oxygen_close(struct snd_pcm_substream *substream)
 223 {
 224         struct oxygen *chip = snd_pcm_substream_chip(substream);
 225         unsigned int channel = oxygen_substream_channel(substream);
 226
 227         mutex_lock(&chip->mutex);
 228         chip->pcm_active &= ~(1 << channel);
 229         if (channel == PCM_SPDIF) {
 230                 chip->controls[CONTROL_SPDIF_PCM]->vd[0].access |=
 231                         SNDRV_CTL_ELEM_ACCESS_INACTIVE;
 232                 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
 233                                SNDRV_CTL_EVENT_MASK_INFO,
 234                                &chip->controls[CONTROL_SPDIF_PCM]->id);
 235         }
 236         if (channel == PCM_SPDIF || channel == PCM_MULTICH)
 237                 oxygen_update_spdif_source(chip);
 238         mutex_unlock(&chip->mutex);
 239
 240         chip->streams[channel] = NULL;
 241         return 0;
 242 }
 243
 244 static unsigned int oxygen_format(struct snd_pcm_hw_params *hw_params)
 245 {
 246         if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
 247                 return OXYGEN_FORMAT_24;
 248         else
 249                 return OXYGEN_FORMAT_16;
 250 }
 251
 252 static unsigned int oxygen_rate(struct snd_pcm_hw_params *hw_params)
 253 {
 254         switch (params_rate(hw_params)) {
 255         case 32000:
 256                 return OXYGEN_RATE_32000;
 257         case 44100:
 258                 return OXYGEN_RATE_44100;
 259         default: /* 48000 */
 260                 return OXYGEN_RATE_48000;
 261         case 64000:
 262                 return OXYGEN_RATE_64000;
 263         case 88200:
 264                 return OXYGEN_RATE_88200;
 265         case 96000:
 266                 return OXYGEN_RATE_96000;
 267         case 176400:
 268                 return OXYGEN_RATE_176400;
 269         case 192000:
 270                 return OXYGEN_RATE_192000;
 271         }
 272 }
 273
 274 static unsigned int oxygen_i2s_mclk(struct snd_pcm_hw_params *hw_params)
 275 {
 276         if (params_rate(hw_params) <= 96000)
 277                 return OXYGEN_I2S_MCLK_256;
 278         else
 279                 return OXYGEN_I2S_MCLK_128;
 280 }
 281
 282 static unsigned int oxygen_i2s_bits(struct snd_pcm_hw_params *hw_params)
 283 {
 284         if (params_format(hw_params) == SNDRV_PCM_FORMAT_S32_LE)
 285                 return OXYGEN_I2S_BITS_24;
 286         else
 287                 return OXYGEN_I2S_BITS_16;
 288 }
 289
 290 static unsigned int oxygen_play_channels(struct snd_pcm_hw_params *hw_params)
 291 {
 292         switch (params_channels(hw_params)) {
 293         default: /* 2 */
 294                 return OXYGEN_PLAY_CHANNELS_2;
 295         case 4:
 296                 return OXYGEN_PLAY_CHANNELS_4;
 297         case 6:
 298                 return OXYGEN_PLAY_CHANNELS_6;
 299         case 8:
 300                 return OXYGEN_PLAY_CHANNELS_8;
 301         }
 302 }
 303
 304 static const unsigned int channel_base_registers[PCM_COUNT] = {
 305         [PCM_A] = OXYGEN_DMA_A_ADDRESS,
 306         [PCM_B] = OXYGEN_DMA_B_ADDRESS,
 307         [PCM_C] = OXYGEN_DMA_C_ADDRESS,
 308         [PCM_SPDIF] = OXYGEN_DMA_SPDIF_ADDRESS,
 309         [PCM_MULTICH] = OXYGEN_DMA_MULTICH_ADDRESS,
 310         [PCM_AC97] = OXYGEN_DMA_AC97_ADDRESS,
 311 };
 312
 313 static int oxygen_hw_params(struct snd_pcm_substream *substream,
 314                             struct snd_pcm_hw_params *hw_params)
 315 {
 316         struct oxygen *chip = snd_pcm_substream_chip(substream);
 317         unsigned int channel = oxygen_substream_channel(substream);
 318         int err;
 319
 320         err = snd_pcm_lib_malloc_pages(substream,
 321                                        params_buffer_bytes(hw_params));
 322         if (err < 0)
 323                 return err;
 324
 325         oxygen_write32(chip, channel_base_registers[channel],
 326                        (u32)substream->runtime->dma_addr);
 327         if (channel == PCM_MULTICH) {
 328                 oxygen_write32(chip, OXYGEN_DMA_MULTICH_COUNT,
 329                                params_buffer_bytes(hw_params) / 4 - 1);
 330                 oxygen_write32(chip, OXYGEN_DMA_MULTICH_TCOUNT,
 331                                params_period_bytes(hw_params) / 4 - 1);
 332         } else {
 333                 oxygen_write16(chip, channel_base_registers[channel] + 4,
 334                                params_buffer_bytes(hw_params) / 4 - 1);
 335                 oxygen_write16(chip, channel_base_registers[channel] + 6,
 336                                params_period_bytes(hw_params) / 4 - 1);
 337         }
 338         return 0;
 339 }
 340
 341 static int oxygen_rec_a_hw_params(struct snd_pcm_substream *substream,
 342                                   struct snd_pcm_hw_params *hw_params)
 343 {
 344         struct oxygen *chip = snd_pcm_substream_chip(substream);
 345         int err;
 346
 347         err = oxygen_hw_params(substream, hw_params);
 348         if (err < 0)
 349                 return err;
 350
 351         spin_lock_irq(&chip->reg_lock);
 352         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
 353                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_A_SHIFT,
 354                              OXYGEN_REC_FORMAT_A_MASK);
 355         oxygen_write16_masked(chip, OXYGEN_I2S_A_FORMAT,
 356                               oxygen_rate(hw_params) |
 357                               oxygen_i2s_mclk(hw_params) |
 358                               chip->model.adc_i2s_format |
 359                               oxygen_i2s_bits(hw_params),
 360                               OXYGEN_I2S_RATE_MASK |
 361                               OXYGEN_I2S_FORMAT_MASK |
 362                               OXYGEN_I2S_MCLK_MASK |
 363                               OXYGEN_I2S_BITS_MASK);
 364         spin_unlock_irq(&chip->reg_lock);
 365
 366         mutex_lock(&chip->mutex);
 367         chip->model.set_adc_params(chip, hw_params);
 368         mutex_unlock(&chip->mutex);
 369         return 0;
 370 }
 371
 372 static int oxygen_rec_b_hw_params(struct snd_pcm_substream *substream,
 373                                   struct snd_pcm_hw_params *hw_params)
 374 {
 375         struct oxygen *chip = snd_pcm_substream_chip(substream);
 376         int is_ac97;
 377         int err;
 378
 379         err = oxygen_hw_params(substream, hw_params);
 380         if (err < 0)
 381                 return err;
 382
 383         is_ac97 = chip->has_ac97_1 &&
 384                 (chip->model.device_config & CAPTURE_2_FROM_AC97_1);
 385
 386         spin_lock_irq(&chip->reg_lock);
 387         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
 388                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_B_SHIFT,
 389                              OXYGEN_REC_FORMAT_B_MASK);
 390         if (!is_ac97)
 391                 oxygen_write16_masked(chip, OXYGEN_I2S_B_FORMAT,
 392                                       oxygen_rate(hw_params) |
 393                                       oxygen_i2s_mclk(hw_params) |
 394                                       chip->model.adc_i2s_format |
 395                                       oxygen_i2s_bits(hw_params),
 396                                       OXYGEN_I2S_RATE_MASK |
 397                                       OXYGEN_I2S_FORMAT_MASK |
 398                                       OXYGEN_I2S_MCLK_MASK |
 399                                       OXYGEN_I2S_BITS_MASK);
 400         spin_unlock_irq(&chip->reg_lock);
 401
 402         if (!is_ac97) {
 403                 mutex_lock(&chip->mutex);
 404                 chip->model.set_adc_params(chip, hw_params);
 405                 mutex_unlock(&chip->mutex);
 406         }
 407         return 0;
 408 }
 409
 410 static int oxygen_rec_c_hw_params(struct snd_pcm_substream *substream,
 411                                   struct snd_pcm_hw_params *hw_params)
 412 {
 413         struct oxygen *chip = snd_pcm_substream_chip(substream);
 414         int err;
 415
 416         err = oxygen_hw_params(substream, hw_params);
 417         if (err < 0)
 418                 return err;
 419
 420         spin_lock_irq(&chip->reg_lock);
 421         oxygen_write8_masked(chip, OXYGEN_REC_FORMAT,
 422                              oxygen_format(hw_params) << OXYGEN_REC_FORMAT_C_SHIFT,
 423                              OXYGEN_REC_FORMAT_C_MASK);
 424         spin_unlock_irq(&chip->reg_lock);
 425         return 0;
 426 }
 427
 428 static int oxygen_spdif_hw_params(struct snd_pcm_substream *substream,
 429                                   struct snd_pcm_hw_params *hw_params)
 430 {
 431         struct oxygen *chip = snd_pcm_substream_chip(substream);
 432         int err;
 433
 434         err = oxygen_hw_params(substream, hw_params);
 435         if (err < 0)
 436                 return err;
 437
 438         spin_lock_irq(&chip->reg_lock);
 439         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 440                             OXYGEN_SPDIF_OUT_ENABLE);
 441         oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
 442                              oxygen_format(hw_params) << OXYGEN_SPDIF_FORMAT_SHIFT,
 443                              OXYGEN_SPDIF_FORMAT_MASK);
 444         oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
 445                               oxygen_rate(hw_params) << OXYGEN_SPDIF_OUT_RATE_SHIFT,
 446                               OXYGEN_SPDIF_OUT_RATE_MASK);
 447         oxygen_update_spdif_source(chip);
 448         spin_unlock_irq(&chip->reg_lock);
 449         return 0;
 450 }
 451
 452 static int oxygen_multich_hw_params(struct snd_pcm_substream *substream,
 453                                     struct snd_pcm_hw_params *hw_params)
 454 {
 455         struct oxygen *chip = snd_pcm_substream_chip(substream);
 456         int err;
 457
 458         err = oxygen_hw_params(substream, hw_params);
 459         if (err < 0)
 460                 return err;
 461
 462         spin_lock_irq(&chip->reg_lock);
 463         oxygen_write8_masked(chip, OXYGEN_PLAY_CHANNELS,
 464                              oxygen_play_channels(hw_params),
 465                              OXYGEN_PLAY_CHANNELS_MASK);
 466         oxygen_write8_masked(chip, OXYGEN_PLAY_FORMAT,
 467                              oxygen_format(hw_params) << OXYGEN_MULTICH_FORMAT_SHIFT,
 468                              OXYGEN_MULTICH_FORMAT_MASK);
 469         oxygen_write16_masked(chip, OXYGEN_I2S_MULTICH_FORMAT,
 470                               oxygen_rate(hw_params) |
 471                               chip->model.dac_i2s_format |
 472                               oxygen_i2s_mclk(hw_params) |
 473                               oxygen_i2s_bits(hw_params),
 474                               OXYGEN_I2S_RATE_MASK |
 475                               OXYGEN_I2S_FORMAT_MASK |
 476                               OXYGEN_I2S_MCLK_MASK |
 477                               OXYGEN_I2S_BITS_MASK);
 478         oxygen_update_dac_routing(chip);
 479         oxygen_update_spdif_source(chip);
 480         spin_unlock_irq(&chip->reg_lock);
 481
 482         mutex_lock(&chip->mutex);
 483         chip->model.set_dac_params(chip, hw_params);
 484         mutex_unlock(&chip->mutex);
 485         return 0;
 486 }
 487
 488 static int oxygen_hw_free(struct snd_pcm_substream *substream)
 489 {
 490         struct oxygen *chip = snd_pcm_substream_chip(substream);
 491         unsigned int channel = oxygen_substream_channel(substream);
 492         unsigned int channel_mask = 1 << channel;
 493
 494         spin_lock_irq(&chip->reg_lock);
 495         chip->interrupt_mask &= ~channel_mask;
 496         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 497
 498         oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
 499         oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
 500         spin_unlock_irq(&chip->reg_lock);
 501
 502         return snd_pcm_lib_free_pages(substream);
 503 }
 504
 505 static int oxygen_spdif_hw_free(struct snd_pcm_substream *substream)
 506 {
 507         struct oxygen *chip = snd_pcm_substream_chip(substream);
 508
 509         spin_lock_irq(&chip->reg_lock);
 510         oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL,
 511                             OXYGEN_SPDIF_OUT_ENABLE);
 512         spin_unlock_irq(&chip->reg_lock);
 513         return oxygen_hw_free(substream);
 514 }
 515
 516 static int oxygen_prepare(struct snd_pcm_substream *substream)
 517 {
 518         struct oxygen *chip = snd_pcm_substream_chip(substream);
 519         unsigned int channel = oxygen_substream_channel(substream);
 520         unsigned int channel_mask = 1 << channel;
 521
 522         spin_lock_irq(&chip->reg_lock);
 523         oxygen_set_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
 524         oxygen_clear_bits8(chip, OXYGEN_DMA_FLUSH, channel_mask);
 525
 526         chip->interrupt_mask |= channel_mask;
 527         oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
 528         spin_unlock_irq(&chip->reg_lock);
 529         return 0;
 530 }
 531
 532 static int oxygen_trigger(struct snd_pcm_substream *substream, int cmd)
 533 {
 534         struct oxygen *chip = snd_pcm_substream_chip(substream);
 535         struct snd_pcm_substream *s;
 536         unsigned int mask = 0;
 537         int pausing;
 538
 539         switch (cmd) {
 540         case SNDRV_PCM_TRIGGER_STOP:
 541         case SNDRV_PCM_TRIGGER_START:
 542         case SNDRV_PCM_TRIGGER_SUSPEND:
 543                 pausing = 0;
 544                 break;
 545         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 546         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 547                 pausing = 1;
 548                 break;
 549         default:
 550                 return -EINVAL;
 551         }
 552
 553         snd_pcm_group_for_each_entry(s, substream) {
 554                 if (snd_pcm_substream_chip(s) == chip) {
 555                         mask |= 1 << oxygen_substream_channel(s);
 556                         snd_pcm_trigger_done(s, substream);
 557                 }
 558         }
 559
 560         spin_lock(&chip->reg_lock);
 561         if (!pausing) {
 562                 if (cmd == SNDRV_PCM_TRIGGER_START)
 563                         chip->pcm_running |= mask;
 564                 else
 565                         chip->pcm_running &= ~mask;
 566                 oxygen_write8(chip, OXYGEN_DMA_STATUS, chip->pcm_running);
 567         } else {
 568                 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
 569                         oxygen_set_bits8(chip, OXYGEN_DMA_PAUSE, mask);
 570                 else
 571                         oxygen_clear_bits8(chip, OXYGEN_DMA_PAUSE, mask);
 572         }
 573         spin_unlock(&chip->reg_lock);
 574         return 0;
 575 }
 576
 577 static snd_pcm_uframes_t oxygen_pointer(struct snd_pcm_substream *substream)
 578 {
 579         struct oxygen *chip = snd_pcm_substream_chip(substream);
 580         struct snd_pcm_runtime *runtime = substream->runtime;
 581         unsigned int channel = oxygen_substream_channel(substream);
 582         u32 curr_addr;
 583
 584         /* no spinlock, this read should be atomic */
 585         curr_addr = oxygen_read32(chip, channel_base_registers[channel]);
 586         return bytes_to_frames(runtime, curr_addr - (u32)runtime->dma_addr);
 587 }
 588
 589 static struct snd_pcm_ops oxygen_rec_a_ops = {
 590         .open      = oxygen_rec_a_open,
 591         .close     = oxygen_close,
 592         .ioctl     = snd_pcm_lib_ioctl,
 593         .hw_params = oxygen_rec_a_hw_params,
 594         .hw_free   = oxygen_hw_free,
 595         .prepare   = oxygen_prepare,
 596         .trigger   = oxygen_trigger,
 597         .pointer   = oxygen_pointer,
 598 };
 599
 600 static struct snd_pcm_ops oxygen_rec_b_ops = {
 601         .open      = oxygen_rec_b_open,
 602         .close     = oxygen_close,
 603         .ioctl     = snd_pcm_lib_ioctl,
 604         .hw_params = oxygen_rec_b_hw_params,
 605         .hw_free   = oxygen_hw_free,
 606         .prepare   = oxygen_prepare,
 607         .trigger   = oxygen_trigger,
 608         .pointer   = oxygen_pointer,
 609 };
 610
 611 static struct snd_pcm_ops oxygen_rec_c_ops = {
 612         .open      = oxygen_rec_c_open,
 613         .close     = oxygen_close,
 614         .ioctl     = snd_pcm_lib_ioctl,
 615         .hw_params = oxygen_rec_c_hw_params,
 616         .hw_free   = oxygen_hw_free,
 617         .prepare   = oxygen_prepare,
 618         .trigger   = oxygen_trigger,
 619         .pointer   = oxygen_pointer,
 620 };
 621
 622 static struct snd_pcm_ops oxygen_spdif_ops = {
 623         .open      = oxygen_spdif_open,
 624         .close     = oxygen_close,
 625         .ioctl     = snd_pcm_lib_ioctl,
 626         .hw_params = oxygen_spdif_hw_params,
 627         .hw_free   = oxygen_spdif_hw_free,
 628         .prepare   = oxygen_prepare,
 629         .trigger   = oxygen_trigger,
 630         .pointer   = oxygen_pointer,
 631 };
 632
 633 static struct snd_pcm_ops oxygen_multich_ops = {
 634         .open      = oxygen_multich_open,
 635         .close     = oxygen_close,
 636         .ioctl     = snd_pcm_lib_ioctl,
 637         .hw_params = oxygen_multich_hw_params,
 638         .hw_free   = oxygen_hw_free,
 639         .prepare   = oxygen_prepare,
 640         .trigger   = oxygen_trigger,
 641         .pointer   = oxygen_pointer,
 642 };
 643
 644 static struct snd_pcm_ops oxygen_ac97_ops = {
 645         .open      = oxygen_ac97_open,
 646         .close     = oxygen_close,
 647         .ioctl     = snd_pcm_lib_ioctl,
 648         .hw_params = oxygen_hw_params,
 649         .hw_free   = oxygen_hw_free,
 650         .prepare   = oxygen_prepare,
 651         .trigger   = oxygen_trigger,
 652         .pointer   = oxygen_pointer,
 653 };
 654
 655 static void oxygen_pcm_free(struct snd_pcm *pcm)
 656 {
 657         snd_pcm_lib_preallocate_free_for_all(pcm);
 658 }
 659
 660 int oxygen_pcm_init(struct oxygen *chip)
 661 {
 662         struct snd_pcm *pcm;
 663         int outs, ins;
 664         int err;
 665
 666         outs = !!(chip->model.device_config & PLAYBACK_0_TO_I2S);
 667         ins = !!(chip->model.device_config & (CAPTURE_0_FROM_I2S_1 |
 668                                               CAPTURE_0_FROM_I2S_2));
 669         if (outs | ins) {
 670                 err = snd_pcm_new(chip->card, "Multichannel",
 671                                   0, outs, ins, &pcm);
 672                 if (err < 0)
 673                         return err;
 674                 if (outs)
 675                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 676                                         &oxygen_multich_ops);
 677                 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1)
 678                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 679                                         &oxygen_rec_a_ops);
 680                 else if (chip->model.device_config & CAPTURE_0_FROM_I2S_2)
 681                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 682                                         &oxygen_rec_b_ops);
 683                 pcm->private_data = chip;
 684                 pcm->private_free = oxygen_pcm_free;
 685                 strcpy(pcm->name, "Multichannel");
 686                 if (outs)
 687                         snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream,
 688                                                       SNDRV_DMA_TYPE_DEV,
 689                                                       snd_dma_pci_data(chip->pci),
 690                                                       DEFAULT_BUFFER_BYTES_MULTICH,
 691                                                       BUFFER_BYTES_MAX_MULTICH);
 692                 if (ins)
 693                         snd_pcm_lib_preallocate_pages(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream,
 694                                                       SNDRV_DMA_TYPE_DEV,
 695                                                       snd_dma_pci_data(chip->pci),
 696                                                       DEFAULT_BUFFER_BYTES,
 697                                                       BUFFER_BYTES_MAX);
 698         }
 699
 700         outs = !!(chip->model.device_config & PLAYBACK_1_TO_SPDIF);
 701         ins = !!(chip->model.device_config & CAPTURE_1_FROM_SPDIF);
 702         if (outs | ins) {
 703                 err = snd_pcm_new(chip->card, "Digital", 1, outs, ins, &pcm);
 704                 if (err < 0)
 705                         return err;
 706                 if (outs)
 707                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 708                                         &oxygen_spdif_ops);
 709                 if (ins)
 710                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 711                                         &oxygen_rec_c_ops);
 712                 pcm->private_data = chip;
 713                 pcm->private_free = oxygen_pcm_free;
 714                 strcpy(pcm->name, "Digital");
 715                 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 716                                                       snd_dma_pci_data(chip->pci),
 717                                                       DEFAULT_BUFFER_BYTES,
 718                                                       BUFFER_BYTES_MAX);
 719         }
 720
 721         if (chip->has_ac97_1) {
 722                 outs = !!(chip->model.device_config & PLAYBACK_2_TO_AC97_1);
 723                 ins = !!(chip->model.device_config & CAPTURE_2_FROM_AC97_1);
 724         } else {
 725                 outs = 0;
 726                 ins = !!(chip->model.device_config & CAPTURE_2_FROM_I2S_2);
 727         }
 728         if (outs | ins) {
 729                 err = snd_pcm_new(chip->card, outs ? "AC97" : "Analog2",
 730                                   2, outs, ins, &pcm);
 731                 if (err < 0)
 732                         return err;
 733                 if (outs) {
 734                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
 735                                         &oxygen_ac97_ops);
 736                         oxygen_write8_masked(chip, OXYGEN_REC_ROUTING,
 737                                              OXYGEN_REC_B_ROUTE_AC97_1,
 738                                              OXYGEN_REC_B_ROUTE_MASK);
 739                 }
 740                 if (ins)
 741                         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
 742                                         &oxygen_rec_b_ops);
 743                 pcm->private_data = chip;
 744                 pcm->private_free = oxygen_pcm_free;
 745                 strcpy(pcm->name, outs ? "Front Panel" : "Analog 2");
 746                 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
 747                                                       snd_dma_pci_data(chip->pci),
 748                                                       DEFAULT_BUFFER_BYTES,
 749                                                       BUFFER_BYTES_MAX);
 750         }
 751         return 0;
 752 }