Linux 4.6-rc6
[linux/fpc-iii.git] / arch / arc / boot / dts / axs10x_mb.dtsi
blob44a578c10732cd1ab79558415e3c66f6825c98bd
1 /*
2  * Support for peripherals on the AXS10x mainboard
3  *
4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
11 / {
12         axs10x_mb {
13                 compatible = "simple-bus";
14                 #address-cells = <1>;
15                 #size-cells = <1>;
16                 ranges = <0x00000000 0xe0000000 0x10000000>;
17                 interrupt-parent = <&mb_intc>;
19                 clocks {
20                         i2cclk: i2cclk {
21                                 compatible = "fixed-clock";
22                                 clock-frequency = <50000000>;
23                                 #clock-cells = <0>;
24                         };
26                         apbclk: apbclk {
27                                 compatible = "fixed-clock";
28                                 clock-frequency = <50000000>;
29                                 #clock-cells = <0>;
30                         };
32                         mmcclk: mmcclk {
33                                 compatible = "fixed-clock";
34                                 clock-frequency = <50000000>;
35                                 #clock-cells = <0>;
36                         };
37                 };
39                 ethernet@0x18000 {
40                         #interrupt-cells = <1>;
41                         compatible = "snps,dwmac";
42                         reg = < 0x18000 0x2000 >;
43                         interrupts = < 4 >;
44                         interrupt-names = "macirq";
45                         phy-mode = "rgmii";
46                         snps,pbl = < 32 >;
47                         clocks = <&apbclk>;
48                         clock-names = "stmmaceth";
49                         max-speed = <100>;
50                 };
52                 ehci@0x40000 {
53                         compatible = "generic-ehci";
54                         reg = < 0x40000 0x100 >;
55                         interrupts = < 8 >;
56                 };
58                 ohci@0x60000 {
59                         compatible = "generic-ohci";
60                         reg = < 0x60000 0x100 >;
61                         interrupts = < 8 >;
62                 };
64                 /*
65                  * According to DW Mobile Storage databook it is required
66                  * to use  "Hold Register" if card is enumerated in SDR12 or
67                  * SDR25 modes.
68                  *
69                  * Utilization of "Hold Register" is already implemented via
70                  * dw_mci_pltfm_prepare_command() which in its turn gets
71                  * used through dw_mci_drv_data->prepare_command call-back.
72                  * This call-back is used in Altera Socfpga platform and so
73                  * we may reuse it saying that we're compatible with their
74                  * "altr,socfpga-dw-mshc".
75                  *
76                  * Most probably "Hold Register" utilization is platform-
77                  * independent requirement which means that single unified
78                  * "snps,dw-mshc" should be enough for all users of DW MMC once
79                  * dw_mci_pltfm_prepare_command() is used in generic platform
80                  * code.
81                  */
82                 mmc@0x15000 {
83                         compatible = "altr,socfpga-dw-mshc";
84                         reg = < 0x15000 0x400 >;
85                         num-slots = < 1 >;
86                         fifo-depth = < 16 >;
87                         card-detect-delay = < 200 >;
88                         clocks = <&apbclk>, <&mmcclk>;
89                         clock-names = "biu", "ciu";
90                         interrupts = < 7 >;
91                         bus-width = < 4 >;
92                 };
94                 uart@0x20000 {
95                         compatible = "snps,dw-apb-uart";
96                         reg = <0x20000 0x100>;
97                         clock-frequency = <33333333>;
98                         interrupts = <17>;
99                         baud = <115200>;
100                         reg-shift = <2>;
101                         reg-io-width = <4>;
102                 };
104                 uart@0x21000 {
105                         compatible = "snps,dw-apb-uart";
106                         reg = <0x21000 0x100>;
107                         clock-frequency = <33333333>;
108                         interrupts = <18>;
109                         baud = <115200>;
110                         reg-shift = <2>;
111                         reg-io-width = <4>;
112                 };
114                 /* UART muxed with USB data port (ttyS3) */
115                 uart@0x22000 {
116                         compatible = "snps,dw-apb-uart";
117                         reg = <0x22000 0x100>;
118                         clock-frequency = <33333333>;
119                         interrupts = <19>;
120                         baud = <115200>;
121                         reg-shift = <2>;
122                         reg-io-width = <4>;
123                 };
125                 i2c@0x1d000 {
126                         compatible = "snps,designware-i2c";
127                         reg = <0x1d000 0x100>;
128                         clock-frequency = <400000>;
129                         clocks = <&i2cclk>;
130                         interrupts = <14>;
131                 };
133                 i2c@0x1e000 {
134                         compatible = "snps,designware-i2c";
135                         reg = <0x1e000 0x100>;
136                         clock-frequency = <400000>;
137                         clocks = <&i2cclk>;
138                         interrupts = <15>;
139                 };
141                 i2c@0x1f000 {
142                         compatible = "snps,designware-i2c";
143                         #address-cells = <1>;
144                         #size-cells = <0>;
145                         reg = <0x1f000 0x100>;
146                         clock-frequency = <400000>;
147                         clocks = <&i2cclk>;
148                         interrupts = <16>;
150                         eeprom@0x54{
151                                 compatible = "24c01";
152                                 reg = <0x54>;
153                                 pagesize = <0x8>;
154                         };
156                         eeprom@0x57{
157                                 compatible = "24c04";
158                                 reg = <0x57>;
159                                 pagesize = <0x8>;
160                         };
161                 };
163                 gpio0:gpio@13000 {
164                         compatible = "snps,dw-apb-gpio";
165                         reg = <0x13000 0x1000>;
166                         #address-cells = <1>;
167                         #size-cells = <0>;
169                         gpio0_banka: gpio-controller@0 {
170                                 compatible = "snps,dw-apb-gpio-port";
171                                 gpio-controller;
172                                 #gpio-cells = <2>;
173                                 snps,nr-gpios = <32>;
174                                 reg = <0>;
175                         };
177                         gpio0_bankb: gpio-controller@1 {
178                                 compatible = "snps,dw-apb-gpio-port";
179                                 gpio-controller;
180                                 #gpio-cells = <2>;
181                                 snps,nr-gpios = <8>;
182                                 reg = <1>;
183                         };
185                         gpio0_bankc: gpio-controller@2 {
186                                 compatible = "snps,dw-apb-gpio-port";
187                                 gpio-controller;
188                                 #gpio-cells = <2>;
189                                 snps,nr-gpios = <8>;
190                                 reg = <2>;
191                         };
192                 };
194                 gpio1:gpio@14000 {
195                         compatible = "snps,dw-apb-gpio";
196                         reg = <0x14000 0x1000>;
197                         #address-cells = <1>;
198                         #size-cells = <0>;
200                         gpio1_banka: gpio-controller@0 {
201                                 compatible = "snps,dw-apb-gpio-port";
202                                 gpio-controller;
203                                 #gpio-cells = <2>;
204                                 snps,nr-gpios = <30>;
205                                 reg = <0>;
206                         };
208                         gpio1_bankb: gpio-controller@1 {
209                                 compatible = "snps,dw-apb-gpio-port";
210                                 gpio-controller;
211                                 #gpio-cells = <2>;
212                                 snps,nr-gpios = <10>;
213                                 reg = <1>;
214                         };
216                         gpio1_bankc: gpio-controller@2 {
217                                 compatible = "snps,dw-apb-gpio-port";
218                                 gpio-controller;
219                                 #gpio-cells = <2>;
220                                 snps,nr-gpios = <8>;
221                                 reg = <2>;
222                         };
223                 };
224         };