2 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
4 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
12 #include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
13 #include <asm/errno.h>
14 #include <asm/arcregs.h>
15 #include <asm/irqflags.h>
21 ;############################ Vector Table #################################
23 .section .vector,"a",@progbits
26 # Initial 16 slots are Exception Vectors
27 VECTOR res_service ; Reset Vector
28 VECTOR mem_service ; Mem exception
29 VECTOR instr_service ; Instrn Error
30 VECTOR EV_MachineCheck ; Fatal Machine check
31 VECTOR EV_TLBMissI ; Intruction TLB miss
32 VECTOR EV_TLBMissD ; Data TLB miss
33 VECTOR EV_TLBProtV ; Protection Violation
34 VECTOR EV_PrivilegeV ; Privilege Violation
35 VECTOR EV_SWI ; Software Breakpoint
36 VECTOR EV_Trap ; Trap exception
37 VECTOR EV_Extension ; Extn Instruction Exception
38 VECTOR EV_DivZero ; Divide by Zero
39 VECTOR EV_DCError ; Data Cache Error
40 VECTOR EV_Misaligned ; Misaligned Data Access
41 VECTOR reserved ; Reserved slots
42 VECTOR reserved ; Reserved slots
44 # Begin Interrupt Vectors
45 VECTOR handle_interrupt ; (16) Timer0
46 VECTOR handle_interrupt ; unused (Timer1)
47 VECTOR handle_interrupt ; unused (WDT)
48 VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
49 VECTOR handle_interrupt ; (20) perf Interrupt
50 VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
51 VECTOR handle_interrupt ; unused
52 VECTOR handle_interrupt ; (23) unused
55 .rept CONFIG_ARC_NUMBER_OF_INTERRUPTS - 8
56 VECTOR handle_interrupt
59 .section .text, "ax",@progbits
62 flag 1 ; Unexpected event, halt
64 ;##################### Interrupt Handling ##############################
66 ENTRY(handle_interrupt)
68 INTERRUPT_PROLOGUE irq
70 clri ; To make status32.IE agree with CPU internal state
72 #ifdef CONFIG_TRACE_IRQFLAGS
77 mov blink, ret_from_exception
84 ;################### Non TLB Exception Handling #############################
98 ; ---------------------------------------------
99 ; Memory Error Exception Handler
100 ; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
101 ; Instruction fetch or Data access, under a single Exception Vector
102 ; ---------------------------------------------
121 lr r0, [efa] ; Faulting Data address
126 SAVE_CALLEE_SAVED_USER
127 mov r2, sp ; callee_regs
129 bl do_misaligned_access
131 ; TBD: optimize - do this only if a callee reg was involved
132 ; either a dst of emulated LD/ST or src with address-writeback
133 RESTORE_CALLEE_SAVED_USER
138 ; ---------------------------------------------
139 ; Protection Violation Exception Handler
140 ; ---------------------------------------------
146 lr r0, [efa] ; Faulting Data address
151 mov blink, ret_from_exception
156 ; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
157 ; need to call do_page_fault().
158 ; ECR in pt_regs provides whether access was R/W/X
160 .global call_do_page_fault
161 .set call_do_page_fault, EV_TLBProtV
163 ;############# Common Handlers for ARCompact and ARCv2 ##############
167 ;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
169 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
170 ; IRQ shd definitely not happen between now and rtie
171 ; All 2 entry points to here already disable interrupts
175 # Interrpts are actually disabled from this point on, but will get
176 # reenabled after we return from interrupt/exception.
177 # But irq tracer needs to be told now...
180 ld r0, [sp, PT_status32] ; U/K mode at time of entry
181 lr r10, [AUX_IRQ_ACT]
183 bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE
184 breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
186 ;####### Return from Intr #######
189 bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
192 ; Handle special case #1: (Entry via Exception, Return via IRQ)
194 ; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
195 ; task now returning to U mode (riding the Intr)
196 ; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
197 ; won't be switched to correct U mode value (from AUX_SP)
198 ; So force AUX_IRQ_ACT.U for such a case
200 btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
201 bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
202 sr r11, [AUX_IRQ_ACT]
204 INTERRUPT_EPILOGUE irq
207 ;####### Return from Exception / pure kernel mode #######
209 .Lexcept_ret: ; Expects r0 has PT_status32
211 debug_marker_syscall:
215 ;####### Return from Intr to insn in delay slot #######
217 ; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
219 ; Intr returning to a Delay Slot (DS) insn
220 ; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
221 ; entry was via Exception in DS which got preempted in kernel).
223 ; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
225 ; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
226 ; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
228 .Lintr_ret_to_delay_slot:
231 ld r2, [@intr_to_DE_cnt]
233 st r2, [@intr_to_DE_cnt]
236 ld r3, [sp, PT_status32]
238 ; STAT32 for Int return created from scratch
239 ; (No delay dlot, disable Further intr in trampoline)
241 bic r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
242 st r0, [sp, PT_status32]
244 mov r1, .Lintr_ret_to_delay_slot_2
247 ; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
251 b .Lisr_ret_fast_path
253 .Lintr_ret_to_delay_slot_2:
254 ; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
255 sub sp, sp, SZ_PT_REGS
264 ; restore AUX_USER_SP if returning to U mode
265 bbit0 r9, STATUS_U_BIT, 1f
274 add sp, sp, SZ_PT_REGS
276 ; return from pure kernel mode to delay slot
279 END(ret_from_exception)