arch/arc/plat-axs10x/axs10x.c

   1 /*
   2  * AXS101/AXS103 Software Development Platform
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/of_platform.h>
  18
  19 #include <asm/asm-offsets.h>
  20 #include <asm/clk.h>
  21 #include <asm/io.h>
  22 #include <asm/mach_desc.h>
  23 #include <asm/mcip.h>
  24
  25 #define AXS_MB_CGU              0xE0010000
  26 #define AXS_MB_CREG             0xE0011000
  27
  28 #define CREG_MB_IRQ_MUX         (AXS_MB_CREG + 0x214)
  29 #define CREG_MB_SW_RESET        (AXS_MB_CREG + 0x220)
  30 #define CREG_MB_VER             (AXS_MB_CREG + 0x230)
  31 #define CREG_MB_CONFIG          (AXS_MB_CREG + 0x234)
  32
  33 #define AXC001_CREG             0xF0001000
  34 #define AXC001_GPIO_INTC        0xF0003000
  35
  36 static void __init axs10x_enable_gpio_intc_wire(void)
  37 {
  38         /*
  39          * Peripherals on CPU Card and Mother Board are wired to cpu intc via
  40          * intermediate DW APB GPIO blocks (mainly for debouncing)
  41          *
  42          *         ---------------------
  43          *        |  snps,arc700-intc |
  44          *        ---------------------
  45          *          | #7          | #15
  46          * -------------------   -------------------
  47          * | snps,dw-apb-gpio |  | snps,dw-apb-gpio |
  48          * -------------------   -------------------
  49          *        | #12                     |
  50          *        |                 [ Debug UART on cpu card ]
  51          *        |
  52          * ------------------------
  53          * | snps,dw-apb-intc (MB)|
  54          * ------------------------
  55          *  |      |       |      |
  56          * [eth] [uart]        [... other perip on Main Board]
  57          *
  58          * Current implementation of "irq-dw-apb-ictl" driver doesn't work well
  59          * with stacked INTCs. In particular problem happens if its master INTC
  60          * not yet instantiated. See discussion here -
  61          * https://lkml.org/lkml/2015/3/4/755
  62          *
  63          * So setup the first gpio block as a passive pass thru and hide it from
  64          * DT hardware topology - connect MB intc directly to cpu intc
  65          * The GPIO "wire" needs to be init nevertheless (here)
  66          *
  67          * One side adv is that peripheral interrupt handling avoids one nested
  68          * intc ISR hop
  69          */
  70 #define GPIO_INTEN              (AXC001_GPIO_INTC + 0x30)
  71 #define GPIO_INTMASK            (AXC001_GPIO_INTC + 0x34)
  72 #define GPIO_INTTYPE_LEVEL      (AXC001_GPIO_INTC + 0x38)
  73 #define GPIO_INT_POLARITY       (AXC001_GPIO_INTC + 0x3c)
  74 #define MB_TO_GPIO_IRQ          12
  75
  76         iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK);
  77         iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL);
  78         iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY);
  79         iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN);
  80 }
  81
  82 static inline void __init
  83 write_cgu_reg(uint32_t value, void __iomem *reg, void __iomem *lock_reg)
  84 {
  85         unsigned int loops = 128 * 1024, ctr;
  86
  87         iowrite32(value, reg);
  88
  89         ctr = loops;
  90         while (((ioread32(lock_reg) & 1) == 1) && ctr--) /* wait for unlock */
  91                 cpu_relax();
  92
  93         ctr = loops;
  94         while (((ioread32(lock_reg) & 1) == 0) && ctr--) /* wait for re-lock */
  95                 cpu_relax();
  96 }
  97
  98 static void __init axs10x_print_board_ver(unsigned int creg, const char *str)
  99 {
 100         union ver {
 101                 struct {
 102 #ifdef CONFIG_CPU_BIG_ENDIAN
 103                         unsigned int pad:11, y:12, m:4, d:5;
 104 #else
 105                         unsigned int d:5, m:4, y:12, pad:11;
 106 #endif
 107                 };
 108                 unsigned int val;
 109         } board;
 110
 111         board.val = ioread32((void __iomem *)creg);
 112         pr_info("AXS: %s FPGA Date: %u-%u-%u\n", str, board.d, board.m,
 113                 board.y);
 114 }
 115
 116 static void __init axs10x_early_init(void)
 117 {
 118         int mb_rev;
 119         char mb[32];
 120
 121         /* Determine motherboard version */
 122         if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28))
 123                 mb_rev = 3;     /* HT-3 (rev3.0) */
 124         else
 125                 mb_rev = 2;     /* HT-2 (rev2.0) */
 126
 127         axs10x_enable_gpio_intc_wire();
 128
 129         scnprintf(mb, 32, "MainBoard v%d", mb_rev);
 130         axs10x_print_board_ver(CREG_MB_VER, mb);
 131 }
 132
 133 #ifdef CONFIG_AXS101
 134
 135 #define CREG_CPU_ADDR_770       (AXC001_CREG + 0x20)
 136 #define CREG_CPU_ADDR_TUNN      (AXC001_CREG + 0x60)
 137 #define CREG_CPU_ADDR_770_UPD   (AXC001_CREG + 0x34)
 138 #define CREG_CPU_ADDR_TUNN_UPD  (AXC001_CREG + 0x74)
 139
 140 #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114)
 141 #define CREG_CPU_GPIO_UART_MUX  (AXC001_CREG + 0x120)
 142
 143 /*
 144  * Set up System Memory Map for ARC cpu / peripherals controllers
 145  *
 146  * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
 147  * of which maps to a corresponding 256MB aperture in Target slave memory map.
 148  *
 149  * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0
 150  * (0x0000_0000) of DDR Port 0 (slave #1)
 151  *
 152  * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
 153  * which has master/slaves on both ends.
 154  * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14
 155  * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to
 156  * MB AXI Tunnel Master, which also has a mem map setup
 157  *
 158  * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
 159  * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master
 160  */
 161 struct aperture {
 162         unsigned int slave_sel:4, slave_off:4, pad:24;
 163 };
 164
 165 /* CPU Card target slaves */
 166 #define AXC001_SLV_NONE                 0
 167 #define AXC001_SLV_DDR_PORT0            1
 168 #define AXC001_SLV_SRAM                 2
 169 #define AXC001_SLV_AXI_TUNNEL           3
 170 #define AXC001_SLV_AXI2APB              6
 171 #define AXC001_SLV_DDR_PORT1            7
 172
 173 /* MB AXI Target slaves */
 174 #define AXS_MB_SLV_NONE                 0
 175 #define AXS_MB_SLV_AXI_TUNNEL_CPU       1
 176 #define AXS_MB_SLV_AXI_TUNNEL_HAPS      2
 177 #define AXS_MB_SLV_SRAM                 3
 178 #define AXS_MB_SLV_CONTROL              4
 179
 180 /* MB AXI masters */
 181 #define AXS_MB_MST_TUNNEL_CPU           0
 182 #define AXS_MB_MST_USB_OHCI             10
 183
 184 /*
 185  * memmap for ARC core on CPU Card
 186  */
 187 static const struct aperture axc001_memmap[16] = {
 188         {AXC001_SLV_AXI_TUNNEL,         0x0},
 189         {AXC001_SLV_AXI_TUNNEL,         0x1},
 190         {AXC001_SLV_SRAM,               0x0}, /* 0x2000_0000: Local SRAM */
 191         {AXC001_SLV_NONE,               0x0},
 192         {AXC001_SLV_NONE,               0x0},
 193         {AXC001_SLV_NONE,               0x0},
 194         {AXC001_SLV_NONE,               0x0},
 195         {AXC001_SLV_NONE,               0x0},
 196         {AXC001_SLV_DDR_PORT0,          0x0}, /* 0x8000_0000: DDR   0..256M */
 197         {AXC001_SLV_DDR_PORT0,          0x1}, /* 0x9000_0000: DDR 256..512M */
 198         {AXC001_SLV_DDR_PORT0,          0x2},
 199         {AXC001_SLV_DDR_PORT0,          0x3},
 200         {AXC001_SLV_NONE,               0x0},
 201         {AXC001_SLV_AXI_TUNNEL,         0xD},
 202         {AXC001_SLV_AXI_TUNNEL,         0xE}, /* MB: CREG, CGU... */
 203         {AXC001_SLV_AXI2APB,            0x0}, /* CPU Card local CREG, CGU... */
 204 };
 205
 206 /*
 207  * memmap for CPU Card AXI Tunnel Master (for access by MB controllers)
 208  * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR
 209  */
 210 static const struct aperture axc001_axi_tunnel_memmap[16] = {
 211         {AXC001_SLV_AXI_TUNNEL,         0x0},
 212         {AXC001_SLV_AXI_TUNNEL,         0x1},
 213         {AXC001_SLV_SRAM,               0x0},
 214         {AXC001_SLV_NONE,               0x0},
 215         {AXC001_SLV_NONE,               0x0},
 216         {AXC001_SLV_NONE,               0x0},
 217         {AXC001_SLV_NONE,               0x0},
 218         {AXC001_SLV_NONE,               0x0},
 219         {AXC001_SLV_DDR_PORT1,          0x0},
 220         {AXC001_SLV_DDR_PORT1,          0x1},
 221         {AXC001_SLV_DDR_PORT1,          0x2},
 222         {AXC001_SLV_DDR_PORT1,          0x3},
 223         {AXC001_SLV_NONE,               0x0},
 224         {AXC001_SLV_AXI_TUNNEL,         0xD},
 225         {AXC001_SLV_AXI_TUNNEL,         0xE},
 226         {AXC001_SLV_AXI2APB,            0x0},
 227 };
 228
 229 /*
 230  * memmap for MB AXI Masters
 231  * Same mem map for all perip controllers as well as MB AXI Tunnel Master
 232  */
 233 static const struct aperture axs_mb_memmap[16] = {
 234         {AXS_MB_SLV_SRAM,               0x0},
 235         {AXS_MB_SLV_SRAM,               0x0},
 236         {AXS_MB_SLV_NONE,               0x0},
 237         {AXS_MB_SLV_NONE,               0x0},
 238         {AXS_MB_SLV_NONE,               0x0},
 239         {AXS_MB_SLV_NONE,               0x0},
 240         {AXS_MB_SLV_NONE,               0x0},
 241         {AXS_MB_SLV_NONE,               0x0},
 242         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x8},   /* DDR on CPU Card */
 243         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0x9},   /* DDR on CPU Card */
 244         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xA},
 245         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xB},
 246         {AXS_MB_SLV_NONE,               0x0},
 247         {AXS_MB_SLV_AXI_TUNNEL_HAPS,    0xD},
 248         {AXS_MB_SLV_CONTROL,            0x0},   /* MB Local CREG, CGU... */
 249         {AXS_MB_SLV_AXI_TUNNEL_CPU,     0xF},
 250 };
 251
 252 static noinline void __init
 253 axs101_set_memmap(void __iomem *base, const struct aperture map[16])
 254 {
 255         unsigned int slave_select, slave_offset;
 256         int i;
 257
 258         slave_select = slave_offset = 0;
 259         for (i = 0; i < 8; i++) {
 260                 slave_select |= map[i].slave_sel << (i << 2);
 261                 slave_offset |= map[i].slave_off << (i << 2);
 262         }
 263
 264         iowrite32(slave_select, base + 0x0);    /* SLV0 */
 265         iowrite32(slave_offset, base + 0x8);    /* OFFSET0 */
 266
 267         slave_select = slave_offset = 0;
 268         for (i = 0; i < 8; i++) {
 269                 slave_select |= map[i+8].slave_sel << (i << 2);
 270                 slave_offset |= map[i+8].slave_off << (i << 2);
 271         }
 272
 273         iowrite32(slave_select, base + 0x4);    /* SLV1 */
 274         iowrite32(slave_offset, base + 0xC);    /* OFFSET1 */
 275 }
 276
 277 static void __init axs101_early_init(void)
 278 {
 279         int i;
 280
 281         /* ARC 770D memory view */
 282         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap);
 283         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD);
 284
 285         /* AXI tunnel memory map (incoming traffic from MB into CPU Card */
 286         axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN,
 287                               axc001_axi_tunnel_memmap);
 288         iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD);
 289
 290         /* MB peripherals memory map */
 291         for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++)
 292                 axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4),
 293                                       axs_mb_memmap);
 294
 295         iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */
 296
 297         /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */
 298         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 299
 300         /* Set up the MB interrupt system: mux interrupts to GPIO7) */
 301         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 302
 303         /* reset ethernet and ULPI interfaces */
 304         iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET);
 305
 306         /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */
 307         iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX);
 308
 309         axs10x_early_init();
 310 }
 311
 312 #endif  /* CONFIG_AXS101 */
 313
 314 #ifdef CONFIG_AXS103
 315
 316 #define AXC003_CGU      0xF0000000
 317 #define AXC003_CREG     0xF0001000
 318 #define AXC003_MST_AXI_TUNNEL   0
 319 #define AXC003_MST_HS38         1
 320
 321 #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440)
 322 #define CREG_CPU_GPIO_UART_MUX  (AXC003_CREG + 0x480)
 323 #define CREG_CPU_TUN_IO_CTRL    (AXC003_CREG + 0x494)
 324
 325
 326 union pll_reg {
 327         struct {
 328 #ifdef CONFIG_CPU_BIG_ENDIAN
 329                 unsigned int pad:17, noupd:1, bypass:1, edge:1, high:6, low:6;
 330 #else
 331                 unsigned int low:6, high:6, edge:1, bypass:1, noupd:1, pad:17;
 332 #endif
 333         };
 334         unsigned int val;
 335 };
 336
 337 static unsigned int __init axs103_get_freq(void)
 338 {
 339         union pll_reg idiv, fbdiv, odiv;
 340         unsigned int f = 33333333;
 341
 342         idiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 0);
 343         fbdiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 4);
 344         odiv.val = ioread32((void __iomem *)AXC003_CGU + 0x80 + 8);
 345
 346         if (idiv.bypass != 1)
 347                 f = f / (idiv.low + idiv.high);
 348
 349         if (fbdiv.bypass != 1)
 350                 f = f * (fbdiv.low + fbdiv.high);
 351
 352         if (odiv.bypass != 1)
 353                 f = f / (odiv.low + odiv.high);
 354
 355         f = (f + 500000) / 1000000; /* Rounding */
 356         return f;
 357 }
 358
 359 static inline unsigned int __init encode_div(unsigned int id, int upd)
 360 {
 361         union pll_reg div;
 362
 363         div.val = 0;
 364
 365         div.noupd = !upd;
 366         div.bypass = id == 1 ? 1 : 0;
 367         div.edge = (id%2 == 0) ? 0 : 1;  /* 0 = rising */
 368         div.low = (id%2 == 0) ? id >> 1 : (id >> 1)+1;
 369         div.high = id >> 1;
 370
 371         return div.val;
 372 }
 373
 374 noinline static void __init
 375 axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od)
 376 {
 377         write_cgu_reg(encode_div(id, 0),
 378                       (void __iomem *)AXC003_CGU + 0x80 + 0,
 379                       (void __iomem *)AXC003_CGU + 0x110);
 380
 381         write_cgu_reg(encode_div(fd, 0),
 382                       (void __iomem *)AXC003_CGU + 0x80 + 4,
 383                       (void __iomem *)AXC003_CGU + 0x110);
 384
 385         write_cgu_reg(encode_div(od, 1),
 386                       (void __iomem *)AXC003_CGU + 0x80 + 8,
 387                       (void __iomem *)AXC003_CGU + 0x110);
 388 }
 389
 390 static void __init axs103_early_init(void)
 391 {
 392         /*
 393          * AXS103 configurations for SMP/QUAD configurations share device tree
 394          * which defaults to 90 MHz. However recent failures of Quad config
 395          * revealed P&R timing violations so clamp it down to safe 50 MHz
 396          * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack
 397          *
 398          * This hack is really hacky as of now. Fix it properly by getting the
 399          * number of cores as return value of platform's early SMP callback
 400          */
 401 #ifdef CONFIG_ARC_MCIP
 402         unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F;
 403         if (num_cores > 2)
 404                 arc_set_core_freq(50 * 1000000);
 405         else if (num_cores == 2)
 406                 arc_set_core_freq(75 * 1000000);
 407 #endif
 408
 409         switch (arc_get_core_freq()/1000000) {
 410         case 33:
 411                 axs103_set_freq(1, 1, 1);
 412                 break;
 413         case 50:
 414                 axs103_set_freq(1, 30, 20);
 415                 break;
 416         case 75:
 417                 axs103_set_freq(2, 45, 10);
 418                 break;
 419         case 90:
 420                 axs103_set_freq(2, 54, 10);
 421                 break;
 422         case 100:
 423                 axs103_set_freq(1, 30, 10);
 424                 break;
 425         case 125:
 426                 axs103_set_freq(2, 45,  6);
 427                 break;
 428         default:
 429                 /*
 430                  * In this case, core_frequency derived from
 431                  * DT "clock-frequency" might not match with board value.
 432                  * Hence update it to match the board value.
 433                  */
 434                 arc_set_core_freq(axs103_get_freq() * 1000000);
 435                 break;
 436         }
 437
 438         pr_info("Freq is %dMHz\n", axs103_get_freq());
 439
 440         /* Memory maps already config in pre-bootloader */
 441
 442         /* set GPIO mux to UART */
 443         iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX);
 444
 445         iowrite32((0x00100000U | 0x000C0000U | 0x00003322U),
 446                   (void __iomem *) CREG_CPU_TUN_IO_CTRL);
 447
 448         /* Set up the AXS_MB interrupt system.*/
 449         iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX
 450                                          + (AXC003_MST_HS38 << 2)));
 451
 452         /* connect ICTL - Main Board with GPIO line */
 453         iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX);
 454
 455         axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card");
 456
 457         axs10x_early_init();
 458 }
 459 #endif
 460
 461 #ifdef CONFIG_AXS101
 462
 463 static const char *axs101_compat[] __initconst = {
 464         "snps,axs101",
 465         NULL,
 466 };
 467
 468 MACHINE_START(AXS101, "axs101")
 469         .dt_compat      = axs101_compat,
 470         .init_early     = axs101_early_init,
 471 MACHINE_END
 472
 473 #endif  /* CONFIG_AXS101 */
 474
 475 #ifdef CONFIG_AXS103
 476
 477 static const char *axs103_compat[] __initconst = {
 478         "snps,axs103",
 479         NULL,
 480 };
 481
 482 MACHINE_START(AXS103, "axs103")
 483         .dt_compat      = axs103_compat,
 484         .init_early     = axs103_early_init,
 485 MACHINE_END
 486
 487 /*
 488  * For the VDK OS-kit, to get the offset to pid and command fields
 489  */
 490 char coware_swa_pid_offset[TASK_PID];
 491 char coware_swa_comm_offset[TASK_COMM];
 492
 493 #endif  /* CONFIG_AXS103 */