arch/powerpc/sysdev/cpm_common.c

   1 /*
   2  * Common CPM code
   3  *
   4  * Author: Scott Wood <scottwood@freescale.com>
   5  *
   6  * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
   7  *
   8  * Some parts derived from commproc.c/cpm2_common.c, which is:
   9  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
  10  * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
  11  * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
  12  * 2006 (c) MontaVista Software, Inc.
  13  * Vitaly Bordug <vbordug@ru.mvista.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of version 2 of the GNU General Public License as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/of_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/export.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/slab.h>
  27
  28 #include <asm/udbg.h>
  29 #include <asm/io.h>
  30 #include <asm/cpm.h>
  31 #include <soc/fsl/qe/qe.h>
  32
  33 #include <mm/mmu_decl.h>
  34
  35 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
  36 #include <linux/of_gpio.h>
  37 #endif
  38
  39 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
  40 static u32 __iomem *cpm_udbg_txdesc =
  41         (u32 __iomem __force *)CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
  42
  43 static void udbg_putc_cpm(char c)
  44 {
  45         u8 __iomem *txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
  46
  47         if (c == '\n')
  48                 udbg_putc_cpm('\r');
  49
  50         while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
  51                 ;
  52
  53         out_8(txbuf, c);
  54         out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
  55 }
  56
  57 void __init udbg_init_cpm(void)
  58 {
  59         if (cpm_udbg_txdesc) {
  60 #ifdef CONFIG_CPM2
  61                 setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
  62 #endif
  63                 udbg_putc = udbg_putc_cpm;
  64         }
  65 }
  66 #endif
  67
  68 #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
  69
  70 struct cpm2_ioports {
  71         u32 dir, par, sor, odr, dat;
  72         u32 res[3];
  73 };
  74
  75 struct cpm2_gpio32_chip {
  76         struct of_mm_gpio_chip mm_gc;
  77         spinlock_t lock;
  78
  79         /* shadowed data register to clear/set bits safely */
  80         u32 cpdata;
  81 };
  82
  83 static inline struct cpm2_gpio32_chip *
  84 to_cpm2_gpio32_chip(struct of_mm_gpio_chip *mm_gc)
  85 {
  86         return container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
  87 }
  88
  89 static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
  90 {
  91         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
  92         struct cpm2_ioports __iomem *iop = mm_gc->regs;
  93
  94         cpm2_gc->cpdata = in_be32(&iop->dat);
  95 }
  96
  97 static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
  98 {
  99         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 100         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 101         u32 pin_mask;
 102
 103         pin_mask = 1 << (31 - gpio);
 104
 105         return !!(in_be32(&iop->dat) & pin_mask);
 106 }
 107
 108 static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
 109         int value)
 110 {
 111         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 112         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 113
 114         if (value)
 115                 cpm2_gc->cpdata |= pin_mask;
 116         else
 117                 cpm2_gc->cpdata &= ~pin_mask;
 118
 119         out_be32(&iop->dat, cpm2_gc->cpdata);
 120 }
 121
 122 static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
 123 {
 124         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 125         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 126         unsigned long flags;
 127         u32 pin_mask = 1 << (31 - gpio);
 128
 129         spin_lock_irqsave(&cpm2_gc->lock, flags);
 130
 131         __cpm2_gpio32_set(mm_gc, pin_mask, value);
 132
 133         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 134 }
 135
 136 static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 137 {
 138         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 139         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 140         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 141         unsigned long flags;
 142         u32 pin_mask = 1 << (31 - gpio);
 143
 144         spin_lock_irqsave(&cpm2_gc->lock, flags);
 145
 146         setbits32(&iop->dir, pin_mask);
 147         __cpm2_gpio32_set(mm_gc, pin_mask, val);
 148
 149         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 150
 151         return 0;
 152 }
 153
 154 static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
 155 {
 156         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 157         struct cpm2_gpio32_chip *cpm2_gc = to_cpm2_gpio32_chip(mm_gc);
 158         struct cpm2_ioports __iomem *iop = mm_gc->regs;
 159         unsigned long flags;
 160         u32 pin_mask = 1 << (31 - gpio);
 161
 162         spin_lock_irqsave(&cpm2_gc->lock, flags);
 163
 164         clrbits32(&iop->dir, pin_mask);
 165
 166         spin_unlock_irqrestore(&cpm2_gc->lock, flags);
 167
 168         return 0;
 169 }
 170
 171 int cpm2_gpiochip_add32(struct device_node *np)
 172 {
 173         struct cpm2_gpio32_chip *cpm2_gc;
 174         struct of_mm_gpio_chip *mm_gc;
 175         struct gpio_chip *gc;
 176
 177         cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
 178         if (!cpm2_gc)
 179                 return -ENOMEM;
 180
 181         spin_lock_init(&cpm2_gc->lock);
 182
 183         mm_gc = &cpm2_gc->mm_gc;
 184         gc = &mm_gc->gc;
 185
 186         mm_gc->save_regs = cpm2_gpio32_save_regs;
 187         gc->ngpio = 32;
 188         gc->direction_input = cpm2_gpio32_dir_in;
 189         gc->direction_output = cpm2_gpio32_dir_out;
 190         gc->get = cpm2_gpio32_get;
 191         gc->set = cpm2_gpio32_set;
 192
 193         return of_mm_gpiochip_add(np, mm_gc);
 194 }
 195 #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */