arch/powerpc/sysdev/fsl_rio.h

   1 /*
   2  * Freescale MPC85xx/MPC86xx RapidIO support
   3  *
   4  * Copyright 2009 Sysgo AG
   5  * Thomas Moll <thomas.moll@sysgo.com>
   6  * - fixed maintenance access routines, check for aligned access
   7  *
   8  * Copyright 2009 Integrated Device Technology, Inc.
   9  * Alex Bounine <alexandre.bounine@idt.com>
  10  * - Added Port-Write message handling
  11  * - Added Machine Check exception handling
  12  *
  13  * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
  14  * Zhang Wei <wei.zhang@freescale.com>
  15  * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
  16  * Liu Gang <Gang.Liu@freescale.com>
  17  *
  18  * Copyright 2005 MontaVista Software, Inc.
  19  * Matt Porter <mporter@kernel.crashing.org>
  20  *
  21  * This program is free software; you can redistribute  it and/or modify it
  22  * under  the terms of  the GNU General  Public License as published by the
  23  * Free Software Foundation;  either version 2 of the  License, or (at your
  24  * option) any later version.
  25  */
  26
  27 #ifndef __FSL_RIO_H
  28 #define __FSL_RIO_H
  29
  30 #include <linux/rio.h>
  31 #include <linux/rio_drv.h>
  32 #include <linux/kfifo.h>
  33
  34 #define RIO_REGS_WIN(mport)     (((struct rio_priv *)(mport->priv))->regs_win)
  35
  36 #define RIO_MAINT_WIN_SIZE      0x400000
  37 #define RIO_LTLEDCSR            0x0608
  38
  39 #define DOORBELL_ROWAR_EN       0x80000000
  40 #define DOORBELL_ROWAR_TFLOWLV  0x08000000 /* highest priority level */
  41 #define DOORBELL_ROWAR_PCI      0x02000000 /* PCI window */
  42 #define DOORBELL_ROWAR_NREAD    0x00040000 /* NREAD */
  43 #define DOORBELL_ROWAR_MAINTRD  0x00070000  /* maintenance read */
  44 #define DOORBELL_ROWAR_RES      0x00002000 /* wrtpy: reserverd */
  45 #define DOORBELL_ROWAR_MAINTWD  0x00007000
  46 #define DOORBELL_ROWAR_SIZE     0x0000000b /* window size is 4k */
  47
  48 #define RIO_ATMU_REGS_PORT1_OFFSET      0x10c00
  49 #define RIO_ATMU_REGS_PORT2_OFFSET      0x10e00
  50 #define RIO_S_DBELL_REGS_OFFSET 0x13400
  51 #define RIO_S_PW_REGS_OFFSET    0x134e0
  52 #define RIO_ATMU_REGS_DBELL_OFFSET      0x10C40
  53 #define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
  54 #define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60
  55
  56 #define MAX_MSG_UNIT_NUM        2
  57 #define MAX_PORT_NUM            4
  58 #define RIO_INB_ATMU_COUNT      4
  59
  60 struct rio_atmu_regs {
  61          u32 rowtar;
  62          u32 rowtear;
  63          u32 rowbar;
  64          u32 pad1;
  65          u32 rowar;
  66          u32 pad2[3];
  67 };
  68
  69 struct rio_inb_atmu_regs {
  70         u32 riwtar;
  71         u32 pad1;
  72         u32 riwbar;
  73         u32 pad2;
  74         u32 riwar;
  75         u32 pad3[3];
  76 };
  77
  78 struct rio_dbell_ring {
  79         void *virt;
  80         dma_addr_t phys;
  81 };
  82
  83 struct rio_port_write_msg {
  84          void *virt;
  85          dma_addr_t phys;
  86          u32 msg_count;
  87          u32 err_count;
  88          u32 discard_count;
  89 };
  90
  91 struct fsl_rio_dbell {
  92         struct rio_mport *mport[MAX_PORT_NUM];
  93         struct device *dev;
  94         struct rio_dbell_regs __iomem *dbell_regs;
  95         struct rio_dbell_ring dbell_ring;
  96         int bellirq;
  97 };
  98
  99 struct fsl_rio_pw {
 100         struct rio_mport *mport[MAX_PORT_NUM];
 101         struct device *dev;
 102         struct rio_pw_regs __iomem *pw_regs;
 103         struct rio_port_write_msg port_write_msg;
 104         int pwirq;
 105         struct work_struct pw_work;
 106         struct kfifo pw_fifo;
 107         spinlock_t pw_fifo_lock;
 108 };
 109
 110 struct rio_priv {
 111         struct device *dev;
 112         void __iomem *regs_win;
 113         struct rio_atmu_regs __iomem *atmu_regs;
 114         struct rio_atmu_regs __iomem *maint_atmu_regs;
 115         struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
 116         void __iomem *maint_win;
 117         void *rmm_handle; /* RapidIO message manager(unit) Handle */
 118 };
 119
 120 extern void __iomem *rio_regs_win;
 121 extern void __iomem *rmu_regs_win;
 122
 123 extern resource_size_t rio_law_start;
 124
 125 extern struct fsl_rio_dbell *dbell;
 126 extern struct fsl_rio_pw *pw;
 127
 128 extern int fsl_rio_setup_rmu(struct rio_mport *mport,
 129         struct device_node *node);
 130 extern int fsl_rio_port_write_init(struct fsl_rio_pw *pw);
 131 extern int fsl_rio_pw_enable(struct rio_mport *mport, int enable);
 132 extern void fsl_rio_port_error_handler(int offset);
 133 extern int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell);
 134
 135 extern int fsl_rio_doorbell_send(struct rio_mport *mport,
 136                                 int index, u16 destid, u16 data);
 137 extern int fsl_add_outb_message(struct rio_mport *mport,
 138         struct rio_dev *rdev,
 139         int mbox, void *buffer, size_t len);
 140 extern int fsl_open_outb_mbox(struct rio_mport *mport,
 141         void *dev_id, int mbox, int entries);
 142 extern void fsl_close_outb_mbox(struct rio_mport *mport, int mbox);
 143 extern int fsl_open_inb_mbox(struct rio_mport *mport,
 144         void *dev_id, int mbox, int entries);
 145 extern void fsl_close_inb_mbox(struct rio_mport *mport, int mbox);
 146 extern int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf);
 147 extern void *fsl_get_inb_message(struct rio_mport *mport, int mbox);
 148
 149 #endif