2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation being IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2012 Freescale Semiconductor, Inc.
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/ratelimit.h>
33 #include <asm/ptrace.h>
34 #include <asm/signal.h>
36 #include <asm/pgtable.h>
38 #include <asm/machdep.h>
45 #define DBG(fmt...) printk(fmt)
50 struct bus_type mpic_subsys
= {
54 EXPORT_SYMBOL_GPL(mpic_subsys
);
56 static struct mpic
*mpics
;
57 static struct mpic
*mpic_primary
;
58 static DEFINE_RAW_SPINLOCK(mpic_lock
);
60 #ifdef CONFIG_PPC32 /* XXX for now */
61 #ifdef CONFIG_IRQ_ALL_CPUS
62 #define distribute_irqs (1)
64 #define distribute_irqs (0)
68 #ifdef CONFIG_MPIC_WEIRD
69 static u32 mpic_infos
[][MPIC_IDX_END
] = {
70 [0] = { /* Original OpenPIC compatible MPIC */
73 MPIC_GREG_GLOBAL_CONF_0
,
75 MPIC_GREG_IPI_VECTOR_PRI_0
,
82 MPIC_TIMER_CURRENT_CNT
,
84 MPIC_TIMER_VECTOR_PRI
,
85 MPIC_TIMER_DESTINATION
,
89 MPIC_CPU_IPI_DISPATCH_0
,
90 MPIC_CPU_IPI_DISPATCH_STRIDE
,
91 MPIC_CPU_CURRENT_TASK_PRI
,
100 MPIC_VECPRI_VECTOR_MASK
,
101 MPIC_VECPRI_POLARITY_POSITIVE
,
102 MPIC_VECPRI_POLARITY_NEGATIVE
,
103 MPIC_VECPRI_SENSE_LEVEL
,
104 MPIC_VECPRI_SENSE_EDGE
,
105 MPIC_VECPRI_POLARITY_MASK
,
106 MPIC_VECPRI_SENSE_MASK
,
109 [1] = { /* Tsi108/109 PIC */
111 TSI108_GREG_FEATURE_0
,
112 TSI108_GREG_GLOBAL_CONF_0
,
113 TSI108_GREG_VENDOR_ID
,
114 TSI108_GREG_IPI_VECTOR_PRI_0
,
115 TSI108_GREG_IPI_STRIDE
,
116 TSI108_GREG_SPURIOUS
,
117 TSI108_GREG_TIMER_FREQ
,
121 TSI108_TIMER_CURRENT_CNT
,
122 TSI108_TIMER_BASE_CNT
,
123 TSI108_TIMER_VECTOR_PRI
,
124 TSI108_TIMER_DESTINATION
,
128 TSI108_CPU_IPI_DISPATCH_0
,
129 TSI108_CPU_IPI_DISPATCH_STRIDE
,
130 TSI108_CPU_CURRENT_TASK_PRI
,
138 TSI108_IRQ_VECTOR_PRI
,
139 TSI108_VECPRI_VECTOR_MASK
,
140 TSI108_VECPRI_POLARITY_POSITIVE
,
141 TSI108_VECPRI_POLARITY_NEGATIVE
,
142 TSI108_VECPRI_SENSE_LEVEL
,
143 TSI108_VECPRI_SENSE_EDGE
,
144 TSI108_VECPRI_POLARITY_MASK
,
145 TSI108_VECPRI_SENSE_MASK
,
146 TSI108_IRQ_DESTINATION
150 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
152 #else /* CONFIG_MPIC_WEIRD */
154 #define MPIC_INFO(name) MPIC_##name
156 #endif /* CONFIG_MPIC_WEIRD */
158 static inline unsigned int mpic_processor_id(struct mpic
*mpic
)
160 unsigned int cpu
= 0;
162 if (!(mpic
->flags
& MPIC_SECONDARY
))
163 cpu
= hard_smp_processor_id();
169 * Register accessor functions
173 static inline u32
_mpic_read(enum mpic_reg_type type
,
174 struct mpic_reg_bank
*rb
,
178 #ifdef CONFIG_PPC_DCR
179 case mpic_access_dcr
:
180 return dcr_read(rb
->dhost
, reg
);
182 case mpic_access_mmio_be
:
183 return in_be32(rb
->base
+ (reg
>> 2));
184 case mpic_access_mmio_le
:
186 return in_le32(rb
->base
+ (reg
>> 2));
190 static inline void _mpic_write(enum mpic_reg_type type
,
191 struct mpic_reg_bank
*rb
,
192 unsigned int reg
, u32 value
)
195 #ifdef CONFIG_PPC_DCR
196 case mpic_access_dcr
:
197 dcr_write(rb
->dhost
, reg
, value
);
200 case mpic_access_mmio_be
:
201 out_be32(rb
->base
+ (reg
>> 2), value
);
203 case mpic_access_mmio_le
:
205 out_le32(rb
->base
+ (reg
>> 2), value
);
210 static inline u32
_mpic_ipi_read(struct mpic
*mpic
, unsigned int ipi
)
212 enum mpic_reg_type type
= mpic
->reg_type
;
213 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
214 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
216 if ((mpic
->flags
& MPIC_BROKEN_IPI
) && type
== mpic_access_mmio_le
)
217 type
= mpic_access_mmio_be
;
218 return _mpic_read(type
, &mpic
->gregs
, offset
);
221 static inline void _mpic_ipi_write(struct mpic
*mpic
, unsigned int ipi
, u32 value
)
223 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
224 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
226 _mpic_write(mpic
->reg_type
, &mpic
->gregs
, offset
, value
);
229 static inline unsigned int mpic_tm_offset(struct mpic
*mpic
, unsigned int tm
)
231 return (tm
>> 2) * MPIC_TIMER_GROUP_STRIDE
+
232 (tm
& 3) * MPIC_INFO(TIMER_STRIDE
);
235 static inline u32
_mpic_tm_read(struct mpic
*mpic
, unsigned int tm
)
237 unsigned int offset
= mpic_tm_offset(mpic
, tm
) +
238 MPIC_INFO(TIMER_VECTOR_PRI
);
240 return _mpic_read(mpic
->reg_type
, &mpic
->tmregs
, offset
);
243 static inline void _mpic_tm_write(struct mpic
*mpic
, unsigned int tm
, u32 value
)
245 unsigned int offset
= mpic_tm_offset(mpic
, tm
) +
246 MPIC_INFO(TIMER_VECTOR_PRI
);
248 _mpic_write(mpic
->reg_type
, &mpic
->tmregs
, offset
, value
);
251 static inline u32
_mpic_cpu_read(struct mpic
*mpic
, unsigned int reg
)
253 unsigned int cpu
= mpic_processor_id(mpic
);
255 return _mpic_read(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
);
258 static inline void _mpic_cpu_write(struct mpic
*mpic
, unsigned int reg
, u32 value
)
260 unsigned int cpu
= mpic_processor_id(mpic
);
262 _mpic_write(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
, value
);
265 static inline u32
_mpic_irq_read(struct mpic
*mpic
, unsigned int src_no
, unsigned int reg
)
267 unsigned int isu
= src_no
>> mpic
->isu_shift
;
268 unsigned int idx
= src_no
& mpic
->isu_mask
;
271 val
= _mpic_read(mpic
->reg_type
, &mpic
->isus
[isu
],
272 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)));
273 #ifdef CONFIG_MPIC_BROKEN_REGREAD
275 val
= (val
& (MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
)) |
276 mpic
->isu_reg0_shadow
[src_no
];
281 static inline void _mpic_irq_write(struct mpic
*mpic
, unsigned int src_no
,
282 unsigned int reg
, u32 value
)
284 unsigned int isu
= src_no
>> mpic
->isu_shift
;
285 unsigned int idx
= src_no
& mpic
->isu_mask
;
287 _mpic_write(mpic
->reg_type
, &mpic
->isus
[isu
],
288 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)), value
);
290 #ifdef CONFIG_MPIC_BROKEN_REGREAD
292 mpic
->isu_reg0_shadow
[src_no
] =
293 value
& ~(MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
);
297 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
298 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
299 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
300 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
301 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
302 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
303 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
304 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
305 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
306 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
310 * Low level utility functions
314 static void _mpic_map_mmio(struct mpic
*mpic
, phys_addr_t phys_addr
,
315 struct mpic_reg_bank
*rb
, unsigned int offset
,
318 rb
->base
= ioremap(phys_addr
+ offset
, size
);
319 BUG_ON(rb
->base
== NULL
);
322 #ifdef CONFIG_PPC_DCR
323 static void _mpic_map_dcr(struct mpic
*mpic
, struct mpic_reg_bank
*rb
,
324 unsigned int offset
, unsigned int size
)
326 phys_addr_t phys_addr
= dcr_resource_start(mpic
->node
, 0);
327 rb
->dhost
= dcr_map(mpic
->node
, phys_addr
+ offset
, size
);
328 BUG_ON(!DCR_MAP_OK(rb
->dhost
));
331 static inline void mpic_map(struct mpic
*mpic
,
332 phys_addr_t phys_addr
, struct mpic_reg_bank
*rb
,
333 unsigned int offset
, unsigned int size
)
335 if (mpic
->flags
& MPIC_USES_DCR
)
336 _mpic_map_dcr(mpic
, rb
, offset
, size
);
338 _mpic_map_mmio(mpic
, phys_addr
, rb
, offset
, size
);
340 #else /* CONFIG_PPC_DCR */
341 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
342 #endif /* !CONFIG_PPC_DCR */
346 /* Check if we have one of those nice broken MPICs with a flipped endian on
347 * reads from IPI registers
349 static void __init
mpic_test_broken_ipi(struct mpic
*mpic
)
353 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
), MPIC_VECPRI_MASK
);
354 r
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
));
356 if (r
== le32_to_cpu(MPIC_VECPRI_MASK
)) {
357 printk(KERN_INFO
"mpic: Detected reversed IPI registers\n");
358 mpic
->flags
|= MPIC_BROKEN_IPI
;
362 #ifdef CONFIG_MPIC_U3_HT_IRQS
364 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
365 * to force the edge setting on the MPIC and do the ack workaround.
367 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
369 if (source
>= 128 || !mpic
->fixups
)
371 return mpic
->fixups
[source
].base
!= NULL
;
375 static inline void mpic_ht_end_irq(struct mpic
*mpic
, unsigned int source
)
377 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
379 if (fixup
->applebase
) {
380 unsigned int soff
= (fixup
->index
>> 3) & ~3;
381 unsigned int mask
= 1U << (fixup
->index
& 0x1f);
382 writel(mask
, fixup
->applebase
+ soff
);
384 raw_spin_lock(&mpic
->fixup_lock
);
385 writeb(0x11 + 2 * fixup
->index
, fixup
->base
+ 2);
386 writel(fixup
->data
, fixup
->base
+ 4);
387 raw_spin_unlock(&mpic
->fixup_lock
);
391 static void mpic_startup_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
394 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
398 if (fixup
->base
== NULL
)
401 DBG("startup_ht_interrupt(0x%x) index: %d\n",
402 source
, fixup
->index
);
403 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
404 /* Enable and configure */
405 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
406 tmp
= readl(fixup
->base
+ 4);
410 writel(tmp
, fixup
->base
+ 4);
411 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
414 /* use the lowest bit inverted to the actual HW,
415 * set if this fixup was enabled, clear otherwise */
416 mpic
->save_data
[source
].fixup_data
= tmp
| 1;
420 static void mpic_shutdown_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
422 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
426 if (fixup
->base
== NULL
)
429 DBG("shutdown_ht_interrupt(0x%x)\n", source
);
432 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
433 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
434 tmp
= readl(fixup
->base
+ 4);
436 writel(tmp
, fixup
->base
+ 4);
437 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
440 /* use the lowest bit inverted to the actual HW,
441 * set if this fixup was enabled, clear otherwise */
442 mpic
->save_data
[source
].fixup_data
= tmp
& ~1;
446 #ifdef CONFIG_PCI_MSI
447 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
454 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
455 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
456 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
457 if (id
== PCI_CAP_ID_HT
) {
458 id
= readb(devbase
+ pos
+ 3);
459 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_MSI_MAPPING
)
467 base
= devbase
+ pos
;
469 flags
= readb(base
+ HT_MSI_FLAGS
);
470 if (!(flags
& HT_MSI_FLAGS_FIXED
)) {
471 addr
= readl(base
+ HT_MSI_ADDR_LO
) & HT_MSI_ADDR_LO_MASK
;
472 addr
= addr
| ((u64
)readl(base
+ HT_MSI_ADDR_HI
) << 32);
475 printk(KERN_DEBUG
"mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
476 PCI_SLOT(devfn
), PCI_FUNC(devfn
),
477 flags
& HT_MSI_FLAGS_ENABLE
? "enabled" : "disabled", addr
);
479 if (!(flags
& HT_MSI_FLAGS_ENABLE
))
480 writeb(flags
| HT_MSI_FLAGS_ENABLE
, base
+ HT_MSI_FLAGS
);
483 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
490 static void __init
mpic_scan_ht_pic(struct mpic
*mpic
, u8 __iomem
*devbase
,
491 unsigned int devfn
, u32 vdid
)
498 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
499 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
500 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
501 if (id
== PCI_CAP_ID_HT
) {
502 id
= readb(devbase
+ pos
+ 3);
503 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_IRQ
)
510 base
= devbase
+ pos
;
511 writeb(0x01, base
+ 2);
512 n
= (readl(base
+ 4) >> 16) & 0xff;
514 printk(KERN_INFO
"mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
516 devfn
>> 3, devfn
& 0x7, pos
, vdid
& 0xffff, vdid
>> 16, n
+ 1);
518 for (i
= 0; i
<= n
; i
++) {
519 writeb(0x10 + 2 * i
, base
+ 2);
520 tmp
= readl(base
+ 4);
521 irq
= (tmp
>> 16) & 0xff;
522 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i
, irq
, tmp
);
523 /* mask it , will be unmasked later */
525 writel(tmp
, base
+ 4);
526 mpic
->fixups
[irq
].index
= i
;
527 mpic
->fixups
[irq
].base
= base
;
528 /* Apple HT PIC has a non-standard way of doing EOIs */
529 if ((vdid
& 0xffff) == 0x106b)
530 mpic
->fixups
[irq
].applebase
= devbase
+ 0x60;
532 mpic
->fixups
[irq
].applebase
= NULL
;
533 writeb(0x11 + 2 * i
, base
+ 2);
534 mpic
->fixups
[irq
].data
= readl(base
+ 4) | 0x80000000;
539 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
542 u8 __iomem
*cfgspace
;
544 printk(KERN_INFO
"mpic: Setting up HT PICs workarounds for U3/U4\n");
546 /* Allocate fixups array */
547 mpic
->fixups
= kzalloc(128 * sizeof(*mpic
->fixups
), GFP_KERNEL
);
548 BUG_ON(mpic
->fixups
== NULL
);
551 raw_spin_lock_init(&mpic
->fixup_lock
);
553 /* Map U3 config space. We assume all IO-APICs are on the primary bus
554 * so we only need to map 64kB.
556 cfgspace
= ioremap(0xf2000000, 0x10000);
557 BUG_ON(cfgspace
== NULL
);
559 /* Now we scan all slots. We do a very quick scan, we read the header
560 * type, vendor ID and device ID only, that's plenty enough
562 for (devfn
= 0; devfn
< 0x100; devfn
++) {
563 u8 __iomem
*devbase
= cfgspace
+ (devfn
<< 8);
564 u8 hdr_type
= readb(devbase
+ PCI_HEADER_TYPE
);
565 u32 l
= readl(devbase
+ PCI_VENDOR_ID
);
568 DBG("devfn %x, l: %x\n", devfn
, l
);
570 /* If no device, skip */
571 if (l
== 0xffffffff || l
== 0x00000000 ||
572 l
== 0x0000ffff || l
== 0xffff0000)
574 /* Check if is supports capability lists */
575 s
= readw(devbase
+ PCI_STATUS
);
576 if (!(s
& PCI_STATUS_CAP_LIST
))
579 mpic_scan_ht_pic(mpic
, devbase
, devfn
, l
);
580 mpic_scan_ht_msi(mpic
, devbase
, devfn
);
583 /* next device, if function 0 */
584 if (PCI_FUNC(devfn
) == 0 && (hdr_type
& 0x80) == 0)
589 #else /* CONFIG_MPIC_U3_HT_IRQS */
591 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
596 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
600 #endif /* CONFIG_MPIC_U3_HT_IRQS */
602 /* Find an mpic associated with a given linux interrupt */
603 static struct mpic
*mpic_find(unsigned int irq
)
605 if (irq
< NUM_ISA_INTERRUPTS
)
608 return irq_get_chip_data(irq
);
611 /* Determine if the linux irq is an IPI */
612 static unsigned int mpic_is_ipi(struct mpic
*mpic
, unsigned int src
)
614 return (src
>= mpic
->ipi_vecs
[0] && src
<= mpic
->ipi_vecs
[3]);
617 /* Determine if the linux irq is a timer */
618 static unsigned int mpic_is_tm(struct mpic
*mpic
, unsigned int src
)
620 return (src
>= mpic
->timer_vecs
[0] && src
<= mpic
->timer_vecs
[7]);
623 /* Convert a cpu mask from logical to physical cpu numbers. */
624 static inline u32
mpic_physmask(u32 cpumask
)
629 for (i
= 0; i
< min(32, NR_CPUS
); ++i
, cpumask
>>= 1)
630 mask
|= (cpumask
& 1) << get_hard_smp_processor_id(i
);
635 /* Get the mpic structure from the IPI number */
636 static inline struct mpic
* mpic_from_ipi(struct irq_data
*d
)
638 return irq_data_get_irq_chip_data(d
);
642 /* Get the mpic structure from the irq number */
643 static inline struct mpic
* mpic_from_irq(unsigned int irq
)
645 return irq_get_chip_data(irq
);
648 /* Get the mpic structure from the irq data */
649 static inline struct mpic
* mpic_from_irq_data(struct irq_data
*d
)
651 return irq_data_get_irq_chip_data(d
);
655 static inline void mpic_eoi(struct mpic
*mpic
)
657 mpic_cpu_write(MPIC_INFO(CPU_EOI
), 0);
661 * Linux descriptor level callbacks
665 void mpic_unmask_irq(struct irq_data
*d
)
667 unsigned int loops
= 100000;
668 struct mpic
*mpic
= mpic_from_irq_data(d
);
669 unsigned int src
= irqd_to_hwirq(d
);
671 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic
, mpic
->name
, d
->irq
, src
);
673 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
674 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) &
676 /* make sure mask gets to controller before we return to user */
679 printk(KERN_ERR
"%s: timeout on hwirq %u\n",
683 } while(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
);
686 void mpic_mask_irq(struct irq_data
*d
)
688 unsigned int loops
= 100000;
689 struct mpic
*mpic
= mpic_from_irq_data(d
);
690 unsigned int src
= irqd_to_hwirq(d
);
692 DBG("%s: disable_irq: %d (src %d)\n", mpic
->name
, d
->irq
, src
);
694 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
695 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) |
698 /* make sure mask gets to controller before we return to user */
701 printk(KERN_ERR
"%s: timeout on hwirq %u\n",
705 } while(!(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
));
708 void mpic_end_irq(struct irq_data
*d
)
710 struct mpic
*mpic
= mpic_from_irq_data(d
);
713 DBG("%s: end_irq: %d\n", mpic
->name
, d
->irq
);
715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
723 #ifdef CONFIG_MPIC_U3_HT_IRQS
725 static void mpic_unmask_ht_irq(struct irq_data
*d
)
727 struct mpic
*mpic
= mpic_from_irq_data(d
);
728 unsigned int src
= irqd_to_hwirq(d
);
732 if (irqd_is_level_type(d
))
733 mpic_ht_end_irq(mpic
, src
);
736 static unsigned int mpic_startup_ht_irq(struct irq_data
*d
)
738 struct mpic
*mpic
= mpic_from_irq_data(d
);
739 unsigned int src
= irqd_to_hwirq(d
);
742 mpic_startup_ht_interrupt(mpic
, src
, irqd_is_level_type(d
));
747 static void mpic_shutdown_ht_irq(struct irq_data
*d
)
749 struct mpic
*mpic
= mpic_from_irq_data(d
);
750 unsigned int src
= irqd_to_hwirq(d
);
752 mpic_shutdown_ht_interrupt(mpic
, src
);
756 static void mpic_end_ht_irq(struct irq_data
*d
)
758 struct mpic
*mpic
= mpic_from_irq_data(d
);
759 unsigned int src
= irqd_to_hwirq(d
);
762 DBG("%s: end_irq: %d\n", mpic
->name
, d
->irq
);
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
769 if (irqd_is_level_type(d
))
770 mpic_ht_end_irq(mpic
, src
);
773 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
777 static void mpic_unmask_ipi(struct irq_data
*d
)
779 struct mpic
*mpic
= mpic_from_ipi(d
);
780 unsigned int src
= virq_to_hw(d
->irq
) - mpic
->ipi_vecs
[0];
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic
->name
, d
->irq
, src
);
783 mpic_ipi_write(src
, mpic_ipi_read(src
) & ~MPIC_VECPRI_MASK
);
786 static void mpic_mask_ipi(struct irq_data
*d
)
788 /* NEVER disable an IPI... that's just plain wrong! */
791 static void mpic_end_ipi(struct irq_data
*d
)
793 struct mpic
*mpic
= mpic_from_ipi(d
);
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
803 #endif /* CONFIG_SMP */
805 static void mpic_unmask_tm(struct irq_data
*d
)
807 struct mpic
*mpic
= mpic_from_irq_data(d
);
808 unsigned int src
= virq_to_hw(d
->irq
) - mpic
->timer_vecs
[0];
810 DBG("%s: enable_tm: %d (tm %d)\n", mpic
->name
, d
->irq
, src
);
811 mpic_tm_write(src
, mpic_tm_read(src
) & ~MPIC_VECPRI_MASK
);
815 static void mpic_mask_tm(struct irq_data
*d
)
817 struct mpic
*mpic
= mpic_from_irq_data(d
);
818 unsigned int src
= virq_to_hw(d
->irq
) - mpic
->timer_vecs
[0];
820 mpic_tm_write(src
, mpic_tm_read(src
) | MPIC_VECPRI_MASK
);
824 int mpic_set_affinity(struct irq_data
*d
, const struct cpumask
*cpumask
,
827 struct mpic
*mpic
= mpic_from_irq_data(d
);
828 unsigned int src
= irqd_to_hwirq(d
);
830 if (mpic
->flags
& MPIC_SINGLE_DEST_CPU
) {
831 int cpuid
= irq_choose_cpu(cpumask
);
833 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpuid
);
835 u32 mask
= cpumask_bits(cpumask
)[0];
837 mask
&= cpumask_bits(cpu_online_mask
)[0];
839 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
),
840 mpic_physmask(mask
));
843 return IRQ_SET_MASK_OK
;
846 static unsigned int mpic_type_to_vecpri(struct mpic
*mpic
, unsigned int type
)
848 /* Now convert sense value */
849 switch(type
& IRQ_TYPE_SENSE_MASK
) {
850 case IRQ_TYPE_EDGE_RISING
:
851 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
852 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
853 case IRQ_TYPE_EDGE_FALLING
:
854 case IRQ_TYPE_EDGE_BOTH
:
855 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
856 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
857 case IRQ_TYPE_LEVEL_HIGH
:
858 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
859 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
860 case IRQ_TYPE_LEVEL_LOW
:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
863 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
867 int mpic_set_irq_type(struct irq_data
*d
, unsigned int flow_type
)
869 struct mpic
*mpic
= mpic_from_irq_data(d
);
870 unsigned int src
= irqd_to_hwirq(d
);
871 unsigned int vecpri
, vold
, vnew
;
873 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
874 mpic
, d
->irq
, src
, flow_type
);
876 if (src
>= mpic
->num_sources
)
879 vold
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
881 /* We don't support "none" type */
882 if (flow_type
== IRQ_TYPE_NONE
)
883 flow_type
= IRQ_TYPE_DEFAULT
;
885 /* Default: read HW settings */
886 if (flow_type
== IRQ_TYPE_DEFAULT
) {
889 vold_ps
= vold
& (MPIC_INFO(VECPRI_POLARITY_MASK
) |
890 MPIC_INFO(VECPRI_SENSE_MASK
));
892 if (vold_ps
== (MPIC_INFO(VECPRI_SENSE_EDGE
) |
893 MPIC_INFO(VECPRI_POLARITY_POSITIVE
)))
894 flow_type
= IRQ_TYPE_EDGE_RISING
;
895 else if (vold_ps
== (MPIC_INFO(VECPRI_SENSE_EDGE
) |
896 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
)))
897 flow_type
= IRQ_TYPE_EDGE_FALLING
;
898 else if (vold_ps
== (MPIC_INFO(VECPRI_SENSE_LEVEL
) |
899 MPIC_INFO(VECPRI_POLARITY_POSITIVE
)))
900 flow_type
= IRQ_TYPE_LEVEL_HIGH
;
901 else if (vold_ps
== (MPIC_INFO(VECPRI_SENSE_LEVEL
) |
902 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
)))
903 flow_type
= IRQ_TYPE_LEVEL_LOW
;
905 WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold
);
908 /* Apply to irq desc */
909 irqd_set_trigger_type(d
, flow_type
);
912 if (mpic_is_ht_interrupt(mpic
, src
))
913 vecpri
= MPIC_VECPRI_POLARITY_POSITIVE
|
914 MPIC_VECPRI_SENSE_EDGE
;
916 vecpri
= mpic_type_to_vecpri(mpic
, flow_type
);
918 vnew
= vold
& ~(MPIC_INFO(VECPRI_POLARITY_MASK
) |
919 MPIC_INFO(VECPRI_SENSE_MASK
));
922 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vnew
);
924 return IRQ_SET_MASK_OK_NOCOPY
;
927 void mpic_set_vector(unsigned int virq
, unsigned int vector
)
929 struct mpic
*mpic
= mpic_from_irq(virq
);
930 unsigned int src
= virq_to_hw(virq
);
933 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
934 mpic
, virq
, src
, vector
);
936 if (src
>= mpic
->num_sources
)
939 vecpri
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
940 vecpri
= vecpri
& ~MPIC_INFO(VECPRI_VECTOR_MASK
);
942 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
945 static void mpic_set_destination(unsigned int virq
, unsigned int cpuid
)
947 struct mpic
*mpic
= mpic_from_irq(virq
);
948 unsigned int src
= virq_to_hw(virq
);
950 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
951 mpic
, virq
, src
, cpuid
);
953 if (src
>= mpic
->num_sources
)
956 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpuid
);
959 static struct irq_chip mpic_irq_chip
= {
960 .irq_mask
= mpic_mask_irq
,
961 .irq_unmask
= mpic_unmask_irq
,
962 .irq_eoi
= mpic_end_irq
,
963 .irq_set_type
= mpic_set_irq_type
,
967 static struct irq_chip mpic_ipi_chip
= {
968 .irq_mask
= mpic_mask_ipi
,
969 .irq_unmask
= mpic_unmask_ipi
,
970 .irq_eoi
= mpic_end_ipi
,
972 #endif /* CONFIG_SMP */
974 static struct irq_chip mpic_tm_chip
= {
975 .irq_mask
= mpic_mask_tm
,
976 .irq_unmask
= mpic_unmask_tm
,
977 .irq_eoi
= mpic_end_irq
,
980 #ifdef CONFIG_MPIC_U3_HT_IRQS
981 static struct irq_chip mpic_irq_ht_chip
= {
982 .irq_startup
= mpic_startup_ht_irq
,
983 .irq_shutdown
= mpic_shutdown_ht_irq
,
984 .irq_mask
= mpic_mask_irq
,
985 .irq_unmask
= mpic_unmask_ht_irq
,
986 .irq_eoi
= mpic_end_ht_irq
,
987 .irq_set_type
= mpic_set_irq_type
,
989 #endif /* CONFIG_MPIC_U3_HT_IRQS */
992 static int mpic_host_match(struct irq_domain
*h
, struct device_node
*node
,
993 enum irq_domain_bus_token bus_token
)
995 /* Exact match, unless mpic node is NULL */
996 struct device_node
*of_node
= irq_domain_get_of_node(h
);
997 return of_node
== NULL
|| of_node
== node
;
1000 static int mpic_host_map(struct irq_domain
*h
, unsigned int virq
,
1003 struct mpic
*mpic
= h
->host_data
;
1004 struct irq_chip
*chip
;
1006 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq
, hw
);
1008 if (hw
== mpic
->spurious_vec
)
1010 if (mpic
->protected && test_bit(hw
, mpic
->protected)) {
1011 pr_warning("mpic: Mapping of source 0x%x failed, "
1012 "source protected by firmware !\n",\
1018 else if (hw
>= mpic
->ipi_vecs
[0]) {
1019 WARN_ON(mpic
->flags
& MPIC_SECONDARY
);
1021 DBG("mpic: mapping as IPI\n");
1022 irq_set_chip_data(virq
, mpic
);
1023 irq_set_chip_and_handler(virq
, &mpic
->hc_ipi
,
1027 #endif /* CONFIG_SMP */
1029 if (hw
>= mpic
->timer_vecs
[0] && hw
<= mpic
->timer_vecs
[7]) {
1030 WARN_ON(mpic
->flags
& MPIC_SECONDARY
);
1032 DBG("mpic: mapping as timer\n");
1033 irq_set_chip_data(virq
, mpic
);
1034 irq_set_chip_and_handler(virq
, &mpic
->hc_tm
,
1035 handle_fasteoi_irq
);
1039 if (mpic_map_error_int(mpic
, virq
, hw
))
1042 if (hw
>= mpic
->num_sources
) {
1043 pr_warning("mpic: Mapping of source 0x%x failed, "
1044 "source out of range !\n",\
1049 mpic_msi_reserve_hwirq(mpic
, hw
);
1052 chip
= &mpic
->hc_irq
;
1054 #ifdef CONFIG_MPIC_U3_HT_IRQS
1055 /* Check for HT interrupts, override vecpri */
1056 if (mpic_is_ht_interrupt(mpic
, hw
))
1057 chip
= &mpic
->hc_ht_irq
;
1058 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1060 DBG("mpic: mapping to irq chip @%p\n", chip
);
1062 irq_set_chip_data(virq
, mpic
);
1063 irq_set_chip_and_handler(virq
, chip
, handle_fasteoi_irq
);
1065 /* Set default irq type */
1066 irq_set_irq_type(virq
, IRQ_TYPE_DEFAULT
);
1068 /* If the MPIC was reset, then all vectors have already been
1069 * initialized. Otherwise, a per source lazy initialization
1072 if (!mpic_is_ipi(mpic
, hw
) && (mpic
->flags
& MPIC_NO_RESET
)) {
1076 cpu
= mpic_processor_id(mpic
);
1079 mpic_set_vector(virq
, hw
);
1080 mpic_set_destination(virq
, cpu
);
1081 mpic_irq_set_priority(virq
, 8);
1087 static int mpic_host_xlate(struct irq_domain
*h
, struct device_node
*ct
,
1088 const u32
*intspec
, unsigned int intsize
,
1089 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
1092 struct mpic
*mpic
= h
->host_data
;
1093 static unsigned char map_mpic_senses
[4] = {
1094 IRQ_TYPE_EDGE_RISING
,
1096 IRQ_TYPE_LEVEL_HIGH
,
1097 IRQ_TYPE_EDGE_FALLING
,
1100 *out_hwirq
= intspec
[0];
1101 if (intsize
>= 4 && (mpic
->flags
& MPIC_FSL
)) {
1103 * Freescale MPIC with extended intspec:
1104 * First two cells are as usual. Third specifies
1105 * an "interrupt type". Fourth is type-specific data.
1107 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1109 switch (intspec
[2]) {
1113 if (!(mpic
->flags
& MPIC_FSL_HAS_EIMR
))
1116 if (intspec
[3] >= ARRAY_SIZE(mpic
->err_int_vecs
))
1119 *out_hwirq
= mpic
->err_int_vecs
[intspec
[3]];
1123 if (intspec
[0] >= ARRAY_SIZE(mpic
->ipi_vecs
))
1126 *out_hwirq
= mpic
->ipi_vecs
[intspec
[0]];
1129 if (intspec
[0] >= ARRAY_SIZE(mpic
->timer_vecs
))
1132 *out_hwirq
= mpic
->timer_vecs
[intspec
[0]];
1135 pr_debug("%s: unknown irq type %u\n",
1136 __func__
, intspec
[2]);
1140 *out_flags
= map_mpic_senses
[intspec
[1] & 3];
1141 } else if (intsize
> 1) {
1144 /* Apple invented a new race of encoding on machines with
1145 * an HT APIC. They encode, among others, the index within
1146 * the HT APIC. We don't care about it here since thankfully,
1147 * it appears that they have the APIC already properly
1148 * configured, and thus our current fixup code that reads the
1149 * APIC config works fine. However, we still need to mask out
1150 * bits in the specifier to make sure we only get bit 0 which
1151 * is the level/edge bit (the only sense bit exposed by Apple),
1152 * as their bit 1 means something else.
1154 if (machine_is(powermac
))
1156 *out_flags
= map_mpic_senses
[intspec
[1] & mask
];
1158 *out_flags
= IRQ_TYPE_NONE
;
1160 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1161 intsize
, intspec
[0], intspec
[1], *out_hwirq
, *out_flags
);
1166 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1167 static void mpic_cascade(struct irq_desc
*desc
)
1169 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
1170 struct mpic
*mpic
= irq_desc_get_handler_data(desc
);
1173 BUG_ON(!(mpic
->flags
& MPIC_SECONDARY
));
1175 virq
= mpic_get_one_irq(mpic
);
1177 generic_handle_irq(virq
);
1179 chip
->irq_eoi(&desc
->irq_data
);
1182 static const struct irq_domain_ops mpic_host_ops
= {
1183 .match
= mpic_host_match
,
1184 .map
= mpic_host_map
,
1185 .xlate
= mpic_host_xlate
,
1188 static u32
fsl_mpic_get_version(struct mpic
*mpic
)
1192 if (!(mpic
->flags
& MPIC_FSL
))
1195 brr1
= _mpic_read(mpic
->reg_type
, &mpic
->thiscpuregs
,
1198 return brr1
& MPIC_FSL_BRR1_VER
;
1202 * Exported functions
1205 u32
fsl_mpic_primary_get_version(void)
1207 struct mpic
*mpic
= mpic_primary
;
1210 return fsl_mpic_get_version(mpic
);
1215 struct mpic
* __init
mpic_alloc(struct device_node
*node
,
1216 phys_addr_t phys_addr
,
1218 unsigned int isu_size
,
1219 unsigned int irq_count
,
1222 int i
, psize
, intvec_top
;
1228 u32 fsl_version
= 0;
1230 /* Default MPIC search parameters */
1231 static const struct of_device_id __initconst mpic_device_id
[] = {
1232 { .type
= "open-pic", },
1233 { .compatible
= "open-pic", },
1238 * If we were not passed a device-tree node, then perform the default
1239 * search for standardized a standardized OpenPIC.
1242 node
= of_node_get(node
);
1244 node
= of_find_matching_node(NULL
, mpic_device_id
);
1249 /* Pick the physical address from the device tree if unspecified */
1251 /* Check if it is DCR-based */
1252 if (of_get_property(node
, "dcr-reg", NULL
)) {
1253 flags
|= MPIC_USES_DCR
;
1256 if (of_address_to_resource(node
, 0, &r
))
1257 goto err_of_node_put
;
1258 phys_addr
= r
.start
;
1262 /* Read extra device-tree properties into the flags variable */
1263 if (of_get_property(node
, "big-endian", NULL
))
1264 flags
|= MPIC_BIG_ENDIAN
;
1265 if (of_get_property(node
, "pic-no-reset", NULL
))
1266 flags
|= MPIC_NO_RESET
;
1267 if (of_get_property(node
, "single-cpu-affinity", NULL
))
1268 flags
|= MPIC_SINGLE_DEST_CPU
;
1269 if (of_device_is_compatible(node
, "fsl,mpic")) {
1270 flags
|= MPIC_FSL
| MPIC_LARGE_VECTORS
;
1271 mpic_irq_chip
.flags
|= IRQCHIP_SKIP_SET_WAKE
;
1272 mpic_tm_chip
.flags
|= IRQCHIP_SKIP_SET_WAKE
;
1275 mpic
= kzalloc(sizeof(struct mpic
), GFP_KERNEL
);
1277 goto err_of_node_put
;
1281 mpic
->paddr
= phys_addr
;
1282 mpic
->flags
= flags
;
1284 mpic
->hc_irq
= mpic_irq_chip
;
1285 mpic
->hc_irq
.name
= name
;
1286 if (!(mpic
->flags
& MPIC_SECONDARY
))
1287 mpic
->hc_irq
.irq_set_affinity
= mpic_set_affinity
;
1288 #ifdef CONFIG_MPIC_U3_HT_IRQS
1289 mpic
->hc_ht_irq
= mpic_irq_ht_chip
;
1290 mpic
->hc_ht_irq
.name
= name
;
1291 if (!(mpic
->flags
& MPIC_SECONDARY
))
1292 mpic
->hc_ht_irq
.irq_set_affinity
= mpic_set_affinity
;
1293 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1296 mpic
->hc_ipi
= mpic_ipi_chip
;
1297 mpic
->hc_ipi
.name
= name
;
1298 #endif /* CONFIG_SMP */
1300 mpic
->hc_tm
= mpic_tm_chip
;
1301 mpic
->hc_tm
.name
= name
;
1303 mpic
->num_sources
= 0; /* so far */
1305 if (mpic
->flags
& MPIC_LARGE_VECTORS
)
1310 mpic
->timer_vecs
[0] = intvec_top
- 12;
1311 mpic
->timer_vecs
[1] = intvec_top
- 11;
1312 mpic
->timer_vecs
[2] = intvec_top
- 10;
1313 mpic
->timer_vecs
[3] = intvec_top
- 9;
1314 mpic
->timer_vecs
[4] = intvec_top
- 8;
1315 mpic
->timer_vecs
[5] = intvec_top
- 7;
1316 mpic
->timer_vecs
[6] = intvec_top
- 6;
1317 mpic
->timer_vecs
[7] = intvec_top
- 5;
1318 mpic
->ipi_vecs
[0] = intvec_top
- 4;
1319 mpic
->ipi_vecs
[1] = intvec_top
- 3;
1320 mpic
->ipi_vecs
[2] = intvec_top
- 2;
1321 mpic
->ipi_vecs
[3] = intvec_top
- 1;
1322 mpic
->spurious_vec
= intvec_top
;
1324 /* Look for protected sources */
1325 psrc
= of_get_property(mpic
->node
, "protected-sources", &psize
);
1327 /* Allocate a bitmap with one bit per interrupt */
1328 unsigned int mapsize
= BITS_TO_LONGS(intvec_top
+ 1);
1329 mpic
->protected = kzalloc(mapsize
*sizeof(long), GFP_KERNEL
);
1330 BUG_ON(mpic
->protected == NULL
);
1331 for (i
= 0; i
< psize
/sizeof(u32
); i
++) {
1332 if (psrc
[i
] > intvec_top
)
1334 __set_bit(psrc
[i
], mpic
->protected);
1338 #ifdef CONFIG_MPIC_WEIRD
1339 mpic
->hw_set
= mpic_infos
[MPIC_GET_REGSET(mpic
->flags
)];
1342 /* default register type */
1343 if (mpic
->flags
& MPIC_BIG_ENDIAN
)
1344 mpic
->reg_type
= mpic_access_mmio_be
;
1346 mpic
->reg_type
= mpic_access_mmio_le
;
1349 * An MPIC with a "dcr-reg" property must be accessed that way, but
1350 * only if the kernel includes DCR support.
1352 #ifdef CONFIG_PPC_DCR
1353 if (mpic
->flags
& MPIC_USES_DCR
)
1354 mpic
->reg_type
= mpic_access_dcr
;
1356 BUG_ON(mpic
->flags
& MPIC_USES_DCR
);
1359 /* Map the global registers */
1360 mpic_map(mpic
, mpic
->paddr
, &mpic
->gregs
, MPIC_INFO(GREG_BASE
), 0x1000);
1361 mpic_map(mpic
, mpic
->paddr
, &mpic
->tmregs
, MPIC_INFO(TIMER_BASE
), 0x1000);
1363 if (mpic
->flags
& MPIC_FSL
) {
1367 * Yes, Freescale really did put global registers in the
1368 * magic per-cpu area -- and they don't even show up in the
1369 * non-magic per-cpu copies that this driver normally uses.
1371 mpic_map(mpic
, mpic
->paddr
, &mpic
->thiscpuregs
,
1372 MPIC_CPU_THISBASE
, 0x1000);
1374 fsl_version
= fsl_mpic_get_version(mpic
);
1376 /* Error interrupt mask register (EIMR) is required for
1377 * handling individual device error interrupts. EIMR
1378 * was added in MPIC version 4.1.
1380 * Over here we reserve vector number space for error
1381 * interrupt vectors. This space is stolen from the
1382 * global vector number space, as in case of ipis
1383 * and timer interrupts.
1385 * Available vector space = intvec_top - 12, where 12
1386 * is the number of vectors which have been consumed by
1387 * ipis and timer interrupts.
1389 if (fsl_version
>= 0x401) {
1390 ret
= mpic_setup_error_int(mpic
, intvec_top
- 12);
1398 * EPR is only available starting with v4.0. To support
1399 * platforms that don't know the MPIC version at compile-time,
1400 * such as qemu-e500, turn off coreint if this MPIC doesn't
1401 * support it. Note that we never enable it if it wasn't
1402 * requested in the first place.
1404 * This is done outside the MPIC_FSL check, so that we
1405 * also disable coreint if the MPIC node doesn't have
1406 * an "fsl,mpic" compatible at all. This will be the case
1407 * with device trees generated by older versions of QEMU.
1408 * fsl_version will be zero if MPIC_FSL is not set.
1410 if (fsl_version
< 0x400 && (flags
& MPIC_ENABLE_COREINT
)) {
1411 WARN_ON(ppc_md
.get_irq
!= mpic_get_coreint_irq
);
1412 ppc_md
.get_irq
= mpic_get_irq
;
1417 /* When using a device-node, reset requests are only honored if the MPIC
1418 * is allowed to reset.
1420 if (!(mpic
->flags
& MPIC_NO_RESET
)) {
1421 printk(KERN_DEBUG
"mpic: Resetting\n");
1422 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1423 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1424 | MPIC_GREG_GCONF_RESET
);
1425 while( mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1426 & MPIC_GREG_GCONF_RESET
)
1431 if (mpic
->flags
& MPIC_ENABLE_COREINT
)
1432 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1433 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1434 | MPIC_GREG_GCONF_COREINT
);
1436 if (mpic
->flags
& MPIC_ENABLE_MCK
)
1437 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1438 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1439 | MPIC_GREG_GCONF_MCK
);
1442 * The MPIC driver will crash if there are more cores than we
1443 * can initialize, so we may as well catch that problem here.
1445 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS
);
1447 /* Map the per-CPU registers */
1448 for_each_possible_cpu(i
) {
1449 unsigned int cpu
= get_hard_smp_processor_id(i
);
1451 mpic_map(mpic
, mpic
->paddr
, &mpic
->cpuregs
[cpu
],
1452 MPIC_INFO(CPU_BASE
) + cpu
* MPIC_INFO(CPU_STRIDE
),
1457 * Read feature register. For non-ISU MPICs, num sources as well. On
1458 * ISU MPICs, sources are counted as ISUs are added
1460 greg_feature
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_FEATURE_0
));
1463 * By default, the last source number comes from the MPIC, but the
1464 * device-tree and board support code can override it on buggy hw.
1465 * If we get passed an isu_size (multi-isu MPIC) then we use that
1466 * as a default instead of the value read from the HW.
1468 last_irq
= (greg_feature
& MPIC_GREG_FEATURE_LAST_SRC_MASK
)
1469 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT
;
1471 last_irq
= isu_size
* MPIC_MAX_ISU
- 1;
1472 of_property_read_u32(mpic
->node
, "last-interrupt-source", &last_irq
);
1474 last_irq
= irq_count
- 1;
1476 /* Initialize main ISU if none provided */
1478 isu_size
= last_irq
+ 1;
1479 mpic
->num_sources
= isu_size
;
1480 mpic_map(mpic
, mpic
->paddr
, &mpic
->isus
[0],
1481 MPIC_INFO(IRQ_BASE
),
1482 MPIC_INFO(IRQ_STRIDE
) * isu_size
);
1485 mpic
->isu_size
= isu_size
;
1486 mpic
->isu_shift
= 1 + __ilog2(mpic
->isu_size
- 1);
1487 mpic
->isu_mask
= (1 << mpic
->isu_shift
) - 1;
1489 mpic
->irqhost
= irq_domain_add_linear(mpic
->node
,
1491 &mpic_host_ops
, mpic
);
1494 * FIXME: The code leaks the MPIC object and mappings here; this
1495 * is very unlikely to fail but it ought to be fixed anyways.
1497 if (mpic
->irqhost
== NULL
)
1500 /* Display version */
1501 switch (greg_feature
& MPIC_GREG_FEATURE_VERSION_MASK
) {
1515 printk(KERN_INFO
"mpic: Setting up MPIC \"%s\" version %s at %llx,"
1517 name
, vers
, (unsigned long long)mpic
->paddr
, num_possible_cpus());
1518 printk(KERN_INFO
"mpic: ISU size: %d, shift: %d, mask: %x\n",
1519 mpic
->isu_size
, mpic
->isu_shift
, mpic
->isu_mask
);
1524 if (!(mpic
->flags
& MPIC_SECONDARY
)) {
1525 mpic_primary
= mpic
;
1526 irq_set_default_host(mpic
->irqhost
);
1536 void __init
mpic_assign_isu(struct mpic
*mpic
, unsigned int isu_num
,
1539 unsigned int isu_first
= isu_num
* mpic
->isu_size
;
1541 BUG_ON(isu_num
>= MPIC_MAX_ISU
);
1544 paddr
, &mpic
->isus
[isu_num
], 0,
1545 MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1547 if ((isu_first
+ mpic
->isu_size
) > mpic
->num_sources
)
1548 mpic
->num_sources
= isu_first
+ mpic
->isu_size
;
1551 void __init
mpic_init(struct mpic
*mpic
)
1556 BUG_ON(mpic
->num_sources
== 0);
1558 printk(KERN_INFO
"mpic: Initializing for %d sources\n", mpic
->num_sources
);
1560 /* Set current processor priority to max */
1561 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1563 if (mpic
->flags
& MPIC_FSL
) {
1564 u32 version
= fsl_mpic_get_version(mpic
);
1567 * Timer group B is present at the latest in MPIC 3.1 (e.g.
1568 * mpc8536). It is not present in MPIC 2.0 (e.g. mpc8544).
1569 * I don't know about the status of intermediate versions (or
1570 * whether they even exist).
1572 if (version
>= 0x0301)
1576 /* Initialize timers to our reserved vectors and mask them for now */
1577 for (i
= 0; i
< num_timers
; i
++) {
1578 unsigned int offset
= mpic_tm_offset(mpic
, i
);
1580 mpic_write(mpic
->tmregs
,
1581 offset
+ MPIC_INFO(TIMER_DESTINATION
),
1582 1 << hard_smp_processor_id());
1583 mpic_write(mpic
->tmregs
,
1584 offset
+ MPIC_INFO(TIMER_VECTOR_PRI
),
1586 (9 << MPIC_VECPRI_PRIORITY_SHIFT
) |
1587 (mpic
->timer_vecs
[0] + i
));
1590 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1591 mpic_test_broken_ipi(mpic
);
1592 for (i
= 0; i
< 4; i
++) {
1595 (10 << MPIC_VECPRI_PRIORITY_SHIFT
) |
1596 (mpic
->ipi_vecs
[0] + i
));
1599 /* Do the HT PIC fixups on U3 broken mpic */
1600 DBG("MPIC flags: %x\n", mpic
->flags
);
1601 if ((mpic
->flags
& MPIC_U3_HT_IRQS
) && !(mpic
->flags
& MPIC_SECONDARY
)) {
1602 mpic_scan_ht_pics(mpic
);
1603 mpic_u3msi_init(mpic
);
1606 mpic_pasemi_msi_init(mpic
);
1608 cpu
= mpic_processor_id(mpic
);
1610 if (!(mpic
->flags
& MPIC_NO_RESET
)) {
1611 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1612 /* start with vector = source number, and masked */
1613 u32 vecpri
= MPIC_VECPRI_MASK
| i
|
1614 (8 << MPIC_VECPRI_PRIORITY_SHIFT
);
1616 /* check if protected */
1617 if (mpic
->protected && test_bit(i
, mpic
->protected))
1620 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
1621 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpu
);
1625 /* Init spurious vector */
1626 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_SPURIOUS
), mpic
->spurious_vec
);
1628 /* Disable 8259 passthrough, if supported */
1629 if (!(mpic
->flags
& MPIC_NO_PTHROU_DIS
))
1630 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1631 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1632 | MPIC_GREG_GCONF_8259_PTHROU_DIS
);
1634 if (mpic
->flags
& MPIC_NO_BIAS
)
1635 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1636 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1637 | MPIC_GREG_GCONF_NO_BIAS
);
1639 /* Set current processor priority to 0 */
1640 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1643 /* allocate memory to save mpic state */
1644 mpic
->save_data
= kmalloc(mpic
->num_sources
* sizeof(*mpic
->save_data
),
1646 BUG_ON(mpic
->save_data
== NULL
);
1649 /* Check if this MPIC is chained from a parent interrupt controller */
1650 if (mpic
->flags
& MPIC_SECONDARY
) {
1651 int virq
= irq_of_parse_and_map(mpic
->node
, 0);
1652 if (virq
!= NO_IRQ
) {
1653 printk(KERN_INFO
"%s: hooking up to IRQ %d\n",
1654 mpic
->node
->full_name
, virq
);
1655 irq_set_handler_data(virq
, mpic
);
1656 irq_set_chained_handler(virq
, &mpic_cascade
);
1660 /* FSL mpic error interrupt initialization */
1661 if (mpic
->flags
& MPIC_FSL_HAS_EIMR
)
1662 mpic_err_int_init(mpic
, MPIC_FSL_ERR_INT
);
1665 void mpic_irq_set_priority(unsigned int irq
, unsigned int pri
)
1667 struct mpic
*mpic
= mpic_find(irq
);
1668 unsigned int src
= virq_to_hw(irq
);
1669 unsigned long flags
;
1675 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1676 if (mpic_is_ipi(mpic
, src
)) {
1677 reg
= mpic_ipi_read(src
- mpic
->ipi_vecs
[0]) &
1678 ~MPIC_VECPRI_PRIORITY_MASK
;
1679 mpic_ipi_write(src
- mpic
->ipi_vecs
[0],
1680 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1681 } else if (mpic_is_tm(mpic
, src
)) {
1682 reg
= mpic_tm_read(src
- mpic
->timer_vecs
[0]) &
1683 ~MPIC_VECPRI_PRIORITY_MASK
;
1684 mpic_tm_write(src
- mpic
->timer_vecs
[0],
1685 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1687 reg
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
))
1688 & ~MPIC_VECPRI_PRIORITY_MASK
;
1689 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
1690 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1692 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1695 void mpic_setup_this_cpu(void)
1698 struct mpic
*mpic
= mpic_primary
;
1699 unsigned long flags
;
1700 u32 msk
= 1 << hard_smp_processor_id();
1703 BUG_ON(mpic
== NULL
);
1705 DBG("%s: setup_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1707 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1709 /* let the mpic know we want intrs. default affinity is 0xffffffff
1710 * until changed via /proc. That's how it's done on x86. If we want
1711 * it differently, then we should make sure we also change the default
1712 * values of irq_desc[].affinity in irq.c.
1714 if (distribute_irqs
&& !(mpic
->flags
& MPIC_SINGLE_DEST_CPU
)) {
1715 for (i
= 0; i
< mpic
->num_sources
; i
++)
1716 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1717 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) | msk
);
1720 /* Set current processor priority to 0 */
1721 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1723 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1724 #endif /* CONFIG_SMP */
1727 int mpic_cpu_get_priority(void)
1729 struct mpic
*mpic
= mpic_primary
;
1731 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI
));
1734 void mpic_cpu_set_priority(int prio
)
1736 struct mpic
*mpic
= mpic_primary
;
1738 prio
&= MPIC_CPU_TASKPRI_MASK
;
1739 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), prio
);
1742 void mpic_teardown_this_cpu(int secondary
)
1744 struct mpic
*mpic
= mpic_primary
;
1745 unsigned long flags
;
1746 u32 msk
= 1 << hard_smp_processor_id();
1749 BUG_ON(mpic
== NULL
);
1751 DBG("%s: teardown_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1752 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1754 /* let the mpic know we don't want intrs. */
1755 for (i
= 0; i
< mpic
->num_sources
; i
++)
1756 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1757 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) & ~msk
);
1759 /* Set current processor priority to max */
1760 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1761 /* We need to EOI the IPI since not all platforms reset the MPIC
1762 * on boot and new interrupts wouldn't get delivered otherwise.
1766 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1770 static unsigned int _mpic_get_one_irq(struct mpic
*mpic
, int reg
)
1774 src
= mpic_cpu_read(reg
) & MPIC_INFO(VECPRI_VECTOR_MASK
);
1776 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic
->name
, reg
, src
);
1778 if (unlikely(src
== mpic
->spurious_vec
)) {
1779 if (mpic
->flags
& MPIC_SPV_EOI
)
1783 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1784 printk_ratelimited(KERN_WARNING
"%s: Got protected source %d !\n",
1785 mpic
->name
, (int)src
);
1790 return irq_linear_revmap(mpic
->irqhost
, src
);
1793 unsigned int mpic_get_one_irq(struct mpic
*mpic
)
1795 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_INTACK
));
1798 unsigned int mpic_get_irq(void)
1800 struct mpic
*mpic
= mpic_primary
;
1802 BUG_ON(mpic
== NULL
);
1804 return mpic_get_one_irq(mpic
);
1807 unsigned int mpic_get_coreint_irq(void)
1810 struct mpic
*mpic
= mpic_primary
;
1813 BUG_ON(mpic
== NULL
);
1815 src
= mfspr(SPRN_EPR
);
1817 if (unlikely(src
== mpic
->spurious_vec
)) {
1818 if (mpic
->flags
& MPIC_SPV_EOI
)
1822 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1823 printk_ratelimited(KERN_WARNING
"%s: Got protected source %d !\n",
1824 mpic
->name
, (int)src
);
1828 return irq_linear_revmap(mpic
->irqhost
, src
);
1834 unsigned int mpic_get_mcirq(void)
1836 struct mpic
*mpic
= mpic_primary
;
1838 BUG_ON(mpic
== NULL
);
1840 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_MCACK
));
1844 void mpic_request_ipis(void)
1846 struct mpic
*mpic
= mpic_primary
;
1848 BUG_ON(mpic
== NULL
);
1850 printk(KERN_INFO
"mpic: requesting IPIs...\n");
1852 for (i
= 0; i
< 4; i
++) {
1853 unsigned int vipi
= irq_create_mapping(mpic
->irqhost
,
1854 mpic
->ipi_vecs
[0] + i
);
1855 if (vipi
== NO_IRQ
) {
1856 printk(KERN_ERR
"Failed to map %s\n", smp_ipi_name
[i
]);
1859 smp_request_message_ipi(vipi
, i
);
1863 void smp_mpic_message_pass(int cpu
, int msg
)
1865 struct mpic
*mpic
= mpic_primary
;
1868 BUG_ON(mpic
== NULL
);
1870 /* make sure we're sending something that translates to an IPI */
1871 if ((unsigned int)msg
> 3) {
1872 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1873 smp_processor_id(), msg
);
1878 DBG("%s: send_ipi(ipi_no: %d)\n", mpic
->name
, msg
);
1881 physmask
= 1 << get_hard_smp_processor_id(cpu
);
1883 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0
) +
1884 msg
* MPIC_INFO(CPU_IPI_DISPATCH_STRIDE
), physmask
);
1887 void __init
smp_mpic_probe(void)
1891 DBG("smp_mpic_probe()...\n");
1893 nr_cpus
= num_possible_cpus();
1895 DBG("nr_cpus: %d\n", nr_cpus
);
1898 mpic_request_ipis();
1901 void smp_mpic_setup_cpu(int cpu
)
1903 mpic_setup_this_cpu();
1906 void mpic_reset_core(int cpu
)
1908 struct mpic
*mpic
= mpic_primary
;
1910 int cpuid
= get_hard_smp_processor_id(cpu
);
1913 /* Set target bit for core reset */
1914 pir
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1915 pir
|= (1 << cpuid
);
1916 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
), pir
);
1917 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1919 /* Restore target bit after reset complete */
1920 pir
&= ~(1 << cpuid
);
1921 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
), pir
);
1922 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_PROCESSOR_INIT
));
1924 /* Perform 15 EOI on each reset core to clear pending interrupts.
1925 * This is required for FSL CoreNet based devices */
1926 if (mpic
->flags
& MPIC_FSL
) {
1927 for (i
= 0; i
< 15; i
++) {
1928 _mpic_write(mpic
->reg_type
, &mpic
->cpuregs
[cpuid
],
1933 #endif /* CONFIG_SMP */
1936 static void mpic_suspend_one(struct mpic
*mpic
)
1940 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1941 mpic
->save_data
[i
].vecprio
=
1942 mpic_irq_read(i
, MPIC_INFO(IRQ_VECTOR_PRI
));
1943 mpic
->save_data
[i
].dest
=
1944 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
));
1948 static int mpic_suspend(void)
1950 struct mpic
*mpic
= mpics
;
1953 mpic_suspend_one(mpic
);
1960 static void mpic_resume_one(struct mpic
*mpic
)
1964 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1965 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
),
1966 mpic
->save_data
[i
].vecprio
);
1967 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1968 mpic
->save_data
[i
].dest
);
1970 #ifdef CONFIG_MPIC_U3_HT_IRQS
1972 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[i
];
1975 /* we use the lowest bit in an inverted meaning */
1976 if ((mpic
->save_data
[i
].fixup_data
& 1) == 0)
1979 /* Enable and configure */
1980 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
1982 writel(mpic
->save_data
[i
].fixup_data
& ~1,
1987 } /* end for loop */
1990 static void mpic_resume(void)
1992 struct mpic
*mpic
= mpics
;
1995 mpic_resume_one(mpic
);
2000 static struct syscore_ops mpic_syscore_ops
= {
2001 .resume
= mpic_resume
,
2002 .suspend
= mpic_suspend
,
2005 static int mpic_init_sys(void)
2007 register_syscore_ops(&mpic_syscore_ops
);
2008 subsys_system_register(&mpic_subsys
, NULL
);
2013 device_initcall(mpic_init_sys
);