2 * linux/arch/unicore32/kernel/pci.c
4 * Code specific to PKUnity SoC and UniCore ISA
6 * Copyright (C) 2001-2010 GUAN Xue-tao
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * PCI bios-type initialisation for PCI machines
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
25 #define CONFIG_CMD(bus, devfn, where) \
26 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
29 puv3_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
32 writel(CONFIG_CMD(bus
, devfn
, where
), PCICFG_ADDR
);
35 *value
= (readl(PCICFG_DATA
) >> ((where
& 3) * 8)) & 0xFF;
38 *value
= (readl(PCICFG_DATA
) >> ((where
& 2) * 8)) & 0xFFFF;
41 *value
= readl(PCICFG_DATA
);
44 return PCIBIOS_SUCCESSFUL
;
48 puv3_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
51 writel(CONFIG_CMD(bus
, devfn
, where
), PCICFG_ADDR
);
54 writel((readl(PCICFG_DATA
) & ~FMASK(8, (where
&3)*8))
55 | FIELD(value
, 8, (where
&3)*8), PCICFG_DATA
);
58 writel((readl(PCICFG_DATA
) & ~FMASK(16, (where
&2)*8))
59 | FIELD(value
, 16, (where
&2)*8), PCICFG_DATA
);
62 writel(value
, PCICFG_DATA
);
65 return PCIBIOS_SUCCESSFUL
;
68 struct pci_ops pci_puv3_ops
= {
69 .read
= puv3_read_config
,
70 .write
= puv3_write_config
,
73 void pci_puv3_preinit(void)
75 printk(KERN_DEBUG
"PCI: PKUnity PCI Controller Initializing ...\n");
76 /* config PCI bridge base */
77 writel(io_v2p(PKUNITY_PCIBRI_BASE
), PCICFG_BRIBASE
);
79 writel(0, PCIBRI_AHBCTL0
);
80 writel(io_v2p(PKUNITY_PCIBRI_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_AHBBAR0
);
81 writel(0xFFFF0000, PCIBRI_AHBAMR0
);
82 writel(0, PCIBRI_AHBTAR0
);
84 writel(PCIBRI_CTLx_AT
, PCIBRI_AHBCTL1
);
85 writel(io_v2p(PKUNITY_PCILIO_BASE
) | PCIBRI_BARx_IO
, PCIBRI_AHBBAR1
);
86 writel(0xFFFF0000, PCIBRI_AHBAMR1
);
87 writel(0x00000000, PCIBRI_AHBTAR1
);
89 writel(PCIBRI_CTLx_PREF
, PCIBRI_AHBCTL2
);
90 writel(io_v2p(PKUNITY_PCIMEM_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_AHBBAR2
);
91 writel(0xF8000000, PCIBRI_AHBAMR2
);
92 writel(0, PCIBRI_AHBTAR2
);
94 writel(io_v2p(PKUNITY_PCIAHB_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_BAR1
);
96 writel(PCIBRI_CTLx_AT
| PCIBRI_CTLx_PREF
, PCIBRI_PCICTL0
);
97 writel(io_v2p(PKUNITY_PCIAHB_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_PCIBAR0
);
98 writel(0xF8000000, PCIBRI_PCIAMR0
);
99 writel(PKUNITY_SDRAM_BASE
, PCIBRI_PCITAR0
);
101 writel(readl(PCIBRI_CMD
) | PCIBRI_CMD_IO
| PCIBRI_CMD_MEM
, PCIBRI_CMD
);
104 static int __init
pci_puv3_map_irq(const struct pci_dev
*dev
, u8 slot
, u8 pin
)
106 if (dev
->bus
->number
== 0) {
107 #ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
108 if (dev
->devfn
== 0x00)
110 else if (dev
->devfn
== 0x08)
112 else if (dev
->devfn
== 0x10)
114 else if (dev
->devfn
== 0x18)
117 #ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
118 if (dev
->devfn
== 0x30)
120 else if (dev
->devfn
== 0x60)
122 else if (dev
->devfn
== 0x58)
125 #if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
126 /* only support 2 pci devices */
127 if (dev
->devfn
== 0x00)
128 return IRQ_PCIINTC
; /* sata */
135 * Only first 128MB of memory can be accessed via PCI.
136 * We use GFP_DMA to allocate safe buffers to do map/unmap.
137 * This is really ugly and we need a better way of specifying
138 * DMA-capable regions of memory.
140 void __init
puv3_pci_adjust_zones(unsigned long *zone_size
,
141 unsigned long *zhole_size
)
143 unsigned int sz
= SZ_128M
>> PAGE_SHIFT
;
146 * Only adjust if > 128M on current system
148 if (zone_size
[0] <= sz
)
151 zone_size
[1] = zone_size
[0] - sz
;
153 zhole_size
[1] = zhole_size
[0];
158 * If the bus contains any of these devices, then we must not turn on
159 * parity checking of any kind.
161 static inline int pdev_bad_for_parity(struct pci_dev
*dev
)
167 * pcibios_fixup_bus - Called after each bus is probed,
168 * but before its children are examined.
170 void pcibios_fixup_bus(struct pci_bus
*bus
)
173 u16 features
= PCI_COMMAND_SERR
175 | PCI_COMMAND_FAST_BACK
;
177 bus
->resource
[0] = &ioport_resource
;
178 bus
->resource
[1] = &iomem_resource
;
181 * Walk the devices on this bus, working out what we can
184 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
187 pci_read_config_word(dev
, PCI_STATUS
, &status
);
190 * If any device on this bus does not support fast back
191 * to back transfers, then the bus as a whole is not able
192 * to support them. Having fast back to back transfers
193 * on saves us one PCI cycle per transaction.
195 if (!(status
& PCI_STATUS_FAST_BACK
))
196 features
&= ~PCI_COMMAND_FAST_BACK
;
198 if (pdev_bad_for_parity(dev
))
199 features
&= ~(PCI_COMMAND_SERR
200 | PCI_COMMAND_PARITY
);
202 switch (dev
->class >> 8) {
203 case PCI_CLASS_BRIDGE_PCI
:
204 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &status
);
205 status
|= PCI_BRIDGE_CTL_PARITY
206 | PCI_BRIDGE_CTL_MASTER_ABORT
;
207 status
&= ~(PCI_BRIDGE_CTL_BUS_RESET
208 | PCI_BRIDGE_CTL_FAST_BACK
);
209 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, status
);
212 case PCI_CLASS_BRIDGE_CARDBUS
:
213 pci_read_config_word(dev
, PCI_CB_BRIDGE_CONTROL
,
215 status
|= PCI_CB_BRIDGE_CTL_PARITY
216 | PCI_CB_BRIDGE_CTL_MASTER_ABORT
;
217 pci_write_config_word(dev
, PCI_CB_BRIDGE_CONTROL
,
224 * Now walk the devices again, this time setting them up.
226 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
229 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
231 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
233 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
234 L1_CACHE_BYTES
>> 2);
238 * Propagate the flags to the PCI bridge.
240 if (bus
->self
&& bus
->self
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
241 if (features
& PCI_COMMAND_FAST_BACK
)
242 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_FAST_BACK
;
243 if (features
& PCI_COMMAND_PARITY
)
244 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_PARITY
;
248 * Report what we did for this bus
250 printk(KERN_INFO
"PCI: bus%d: Fast back to back transfers %sabled\n",
251 bus
->number
, (features
& PCI_COMMAND_FAST_BACK
) ? "en" : "dis");
253 EXPORT_SYMBOL(pcibios_fixup_bus
);
255 static int __init
pci_common_init(void)
257 struct pci_bus
*puv3_bus
;
261 puv3_bus
= pci_scan_bus(0, &pci_puv3_ops
, NULL
);
264 panic("PCI: unable to scan bus!");
266 pci_fixup_irqs(pci_common_swizzle
, pci_puv3_map_irq
);
268 if (!pci_has_flag(PCI_PROBE_ONLY
)) {
269 pci_bus_size_bridges(puv3_bus
);
270 pci_bus_assign_resources(puv3_bus
);
272 pci_bus_add_devices(puv3_bus
);
275 subsys_initcall(pci_common_init
);
277 char * __init
pcibios_setup(char *str
)
279 if (!strcmp(str
, "debug")) {
282 } else if (!strcmp(str
, "firmware")) {
283 pci_add_flags(PCI_PROBE_ONLY
);
289 void pcibios_set_master(struct pci_dev
*dev
)
291 /* No special bus mastering setup handling */
295 * From arch/i386/kernel/pci-i386.c:
297 * We need to avoid collisions with `mirrored' VGA ports
298 * and other strange ISA hardware, so we always want the
299 * addresses to be allocated in the 0x000-0x0ff region
302 * Why? Because some silly external IO cards only decode
303 * the low 10 bits of the IO address. The 0x00-0xff region
304 * is reserved for motherboard devices that decode all 16
305 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
306 * but we want to try to avoid allocating at 0x2900-0x2bff
307 * which might be mirrored at 0x0100-0x03ff..
309 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
310 resource_size_t size
, resource_size_t align
)
312 resource_size_t start
= res
->start
;
314 if (res
->flags
& IORESOURCE_IO
&& start
& 0x300)
315 start
= (start
+ 0x3ff) & ~0x3ff;
317 start
= (start
+ align
- 1) & ~(align
- 1);
323 * pcibios_enable_device - Enable I/O and memory.
324 * @dev: PCI device to be enabled
326 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
332 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
334 for (idx
= 0; idx
< 6; idx
++) {
335 /* Only set up the requested stuff */
336 if (!(mask
& (1 << idx
)))
339 r
= dev
->resource
+ idx
;
340 if (!r
->start
&& r
->end
) {
341 printk(KERN_ERR
"PCI: Device %s not available because"
342 " of resource collisions\n", pci_name(dev
));
345 if (r
->flags
& IORESOURCE_IO
)
346 cmd
|= PCI_COMMAND_IO
;
347 if (r
->flags
& IORESOURCE_MEM
)
348 cmd
|= PCI_COMMAND_MEMORY
;
352 * Bridges (eg, cardbus bridges) need to be fully enabled
354 if ((dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
)
355 cmd
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
;
357 if (cmd
!= old_cmd
) {
358 printk("PCI: enabling device %s (%04x -> %04x)\n",
359 pci_name(dev
), old_cmd
, cmd
);
360 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
365 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
366 enum pci_mmap_state mmap_state
, int write_combine
)
370 if (mmap_state
== pci_mmap_io
)
373 phys
= vma
->vm_pgoff
;
378 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
380 if (remap_pfn_range(vma
, vma
->vm_start
, phys
,
381 vma
->vm_end
- vma
->vm_start
,