2 * Using hardware provided CRC32 instruction to accelerate the CRC32 disposal.
3 * CRC32C polynomial:0x1EDC6F41(BE)/0x82F63B78(LE)
4 * CRC32 is a new instruction in Intel SSE4.2, the reference can be found at:
5 * http://www.intel.com/products/processor/manuals/
6 * Intel(R) 64 and IA-32 Architectures Software Developer's Manual
7 * Volume 2A: Instruction Set Reference, A-M
9 * Copyright (C) 2008 Intel Corporation
10 * Authors: Austin Zhang <austin_zhang@linux.intel.com>
11 * Kent Liu <kent.liu@intel.com>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms and conditions of the GNU General Public License,
15 * version 2, as published by the Free Software Foundation.
17 * This program is distributed in the hope it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * You should have received a copy of the GNU General Public License along with
23 * this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/string.h>
30 #include <linux/kernel.h>
31 #include <crypto/internal/hash.h>
33 #include <asm/cpufeatures.h>
34 #include <asm/cpu_device_id.h>
35 #include <asm/fpu/internal.h>
37 #define CHKSUM_BLOCK_SIZE 1
38 #define CHKSUM_DIGEST_SIZE 4
40 #define SCALE_F sizeof(unsigned long)
43 #define REX_PRE "0x48, "
50 * use carryless multiply version of crc32c when buffer
51 * size is >= 512 (when eager fpu is enabled) or
52 * >= 1024 (when eager fpu is disabled) to account
53 * for fpu state save/restore overhead.
55 #define CRC32C_PCL_BREAKEVEN_EAGERFPU 512
56 #define CRC32C_PCL_BREAKEVEN_NOEAGERFPU 1024
58 asmlinkage
unsigned int crc_pcl(const u8
*buffer
, int len
,
59 unsigned int crc_init
);
60 static int crc32c_pcl_breakeven
= CRC32C_PCL_BREAKEVEN_EAGERFPU
;
61 #if defined(X86_FEATURE_EAGER_FPU)
62 #define set_pcl_breakeven_point() \
64 if (!use_eager_fpu()) \
65 crc32c_pcl_breakeven = CRC32C_PCL_BREAKEVEN_NOEAGERFPU; \
68 #define set_pcl_breakeven_point() \
69 (crc32c_pcl_breakeven = CRC32C_PCL_BREAKEVEN_NOEAGERFPU)
71 #endif /* CONFIG_X86_64 */
73 static u32
crc32c_intel_le_hw_byte(u32 crc
, unsigned char const *data
, size_t length
)
77 ".byte 0xf2, 0xf, 0x38, 0xf0, 0xf1"
87 static u32 __pure
crc32c_intel_le_hw(u32 crc
, unsigned char const *p
, size_t len
)
89 unsigned int iquotient
= len
/ SCALE_F
;
90 unsigned int iremainder
= len
% SCALE_F
;
91 unsigned long *ptmp
= (unsigned long *)p
;
95 ".byte 0xf2, " REX_PRE
"0xf, 0x38, 0xf1, 0xf1;"
103 crc
= crc32c_intel_le_hw_byte(crc
, (unsigned char *)ptmp
,
110 * Setting the seed allows arbitrary accumulators and flexible XOR policy
111 * If your algorithm starts with ~0, then XOR with ~0 before you set
114 static int crc32c_intel_setkey(struct crypto_shash
*hash
, const u8
*key
,
117 u32
*mctx
= crypto_shash_ctx(hash
);
119 if (keylen
!= sizeof(u32
)) {
120 crypto_shash_set_flags(hash
, CRYPTO_TFM_RES_BAD_KEY_LEN
);
123 *mctx
= le32_to_cpup((__le32
*)key
);
127 static int crc32c_intel_init(struct shash_desc
*desc
)
129 u32
*mctx
= crypto_shash_ctx(desc
->tfm
);
130 u32
*crcp
= shash_desc_ctx(desc
);
137 static int crc32c_intel_update(struct shash_desc
*desc
, const u8
*data
,
140 u32
*crcp
= shash_desc_ctx(desc
);
142 *crcp
= crc32c_intel_le_hw(*crcp
, data
, len
);
146 static int __crc32c_intel_finup(u32
*crcp
, const u8
*data
, unsigned int len
,
149 *(__le32
*)out
= ~cpu_to_le32(crc32c_intel_le_hw(*crcp
, data
, len
));
153 static int crc32c_intel_finup(struct shash_desc
*desc
, const u8
*data
,
154 unsigned int len
, u8
*out
)
156 return __crc32c_intel_finup(shash_desc_ctx(desc
), data
, len
, out
);
159 static int crc32c_intel_final(struct shash_desc
*desc
, u8
*out
)
161 u32
*crcp
= shash_desc_ctx(desc
);
163 *(__le32
*)out
= ~cpu_to_le32p(crcp
);
167 static int crc32c_intel_digest(struct shash_desc
*desc
, const u8
*data
,
168 unsigned int len
, u8
*out
)
170 return __crc32c_intel_finup(crypto_shash_ctx(desc
->tfm
), data
, len
,
174 static int crc32c_intel_cra_init(struct crypto_tfm
*tfm
)
176 u32
*key
= crypto_tfm_ctx(tfm
);
184 static int crc32c_pcl_intel_update(struct shash_desc
*desc
, const u8
*data
,
187 u32
*crcp
= shash_desc_ctx(desc
);
190 * use faster PCL version if datasize is large enough to
191 * overcome kernel fpu state save/restore overhead
193 if (len
>= crc32c_pcl_breakeven
&& irq_fpu_usable()) {
195 *crcp
= crc_pcl(data
, len
, *crcp
);
198 *crcp
= crc32c_intel_le_hw(*crcp
, data
, len
);
202 static int __crc32c_pcl_intel_finup(u32
*crcp
, const u8
*data
, unsigned int len
,
205 if (len
>= crc32c_pcl_breakeven
&& irq_fpu_usable()) {
207 *(__le32
*)out
= ~cpu_to_le32(crc_pcl(data
, len
, *crcp
));
211 ~cpu_to_le32(crc32c_intel_le_hw(*crcp
, data
, len
));
215 static int crc32c_pcl_intel_finup(struct shash_desc
*desc
, const u8
*data
,
216 unsigned int len
, u8
*out
)
218 return __crc32c_pcl_intel_finup(shash_desc_ctx(desc
), data
, len
, out
);
221 static int crc32c_pcl_intel_digest(struct shash_desc
*desc
, const u8
*data
,
222 unsigned int len
, u8
*out
)
224 return __crc32c_pcl_intel_finup(crypto_shash_ctx(desc
->tfm
), data
, len
,
227 #endif /* CONFIG_X86_64 */
229 static struct shash_alg alg
= {
230 .setkey
= crc32c_intel_setkey
,
231 .init
= crc32c_intel_init
,
232 .update
= crc32c_intel_update
,
233 .final
= crc32c_intel_final
,
234 .finup
= crc32c_intel_finup
,
235 .digest
= crc32c_intel_digest
,
236 .descsize
= sizeof(u32
),
237 .digestsize
= CHKSUM_DIGEST_SIZE
,
239 .cra_name
= "crc32c",
240 .cra_driver_name
= "crc32c-intel",
242 .cra_blocksize
= CHKSUM_BLOCK_SIZE
,
243 .cra_ctxsize
= sizeof(u32
),
244 .cra_module
= THIS_MODULE
,
245 .cra_init
= crc32c_intel_cra_init
,
249 static const struct x86_cpu_id crc32c_cpu_id
[] = {
250 X86_FEATURE_MATCH(X86_FEATURE_XMM4_2
),
253 MODULE_DEVICE_TABLE(x86cpu
, crc32c_cpu_id
);
255 static int __init
crc32c_intel_mod_init(void)
257 if (!x86_match_cpu(crc32c_cpu_id
))
260 if (boot_cpu_has(X86_FEATURE_PCLMULQDQ
)) {
261 alg
.update
= crc32c_pcl_intel_update
;
262 alg
.finup
= crc32c_pcl_intel_finup
;
263 alg
.digest
= crc32c_pcl_intel_digest
;
264 set_pcl_breakeven_point();
267 return crypto_register_shash(&alg
);
270 static void __exit
crc32c_intel_mod_fini(void)
272 crypto_unregister_shash(&alg
);
275 module_init(crc32c_intel_mod_init
);
276 module_exit(crc32c_intel_mod_fini
);
278 MODULE_AUTHOR("Austin Zhang <austin.zhang@intel.com>, Kent Liu <kent.liu@intel.com>");
279 MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware.");
280 MODULE_LICENSE("GPL");
282 MODULE_ALIAS_CRYPTO("crc32c");
283 MODULE_ALIAS_CRYPTO("crc32c-intel");