Linux 4.6-rc6
[linux/fpc-iii.git] / arch / x86 / kernel / aperture_64.c
blob0a2bb1f62e724d5820632eb59bbdaea18acdc659
1 /*
2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture, only set the
5 * aperture in the AGP bridge, or set too small aperture.
7 * If all fails map the aperture over some low memory. This is cheaper than
8 * doing bounce buffering. The memory is lost. This is done at early boot
9 * because only the bootmem allocator can allocate 32+MB.
11 * Copyright 2002 Andi Kleen, SuSE Labs.
13 #define pr_fmt(fmt) "AGP: " fmt
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
18 #include <linux/memblock.h>
19 #include <linux/mmzone.h>
20 #include <linux/pci_ids.h>
21 #include <linux/pci.h>
22 #include <linux/bitops.h>
23 #include <linux/suspend.h>
24 #include <asm/e820.h>
25 #include <asm/io.h>
26 #include <asm/iommu.h>
27 #include <asm/gart.h>
28 #include <asm/pci-direct.h>
29 #include <asm/dma.h>
30 #include <asm/amd_nb.h>
31 #include <asm/x86_init.h>
34 * Using 512M as goal, in case kexec will load kernel_big
35 * that will do the on-position decompress, and could overlap with
36 * with the gart aperture that is used.
37 * Sequence:
38 * kernel_small
39 * ==> kexec (with kdump trigger path or gart still enabled)
40 * ==> kernel_small (gart area become e820_reserved)
41 * ==> kexec (with kdump trigger path or gart still enabled)
42 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
43 * So don't use 512M below as gart iommu, leave the space for kernel
44 * code for safe.
46 #define GART_MIN_ADDR (512ULL << 20)
47 #define GART_MAX_ADDR (1ULL << 32)
49 int gart_iommu_aperture;
50 int gart_iommu_aperture_disabled __initdata;
51 int gart_iommu_aperture_allowed __initdata;
53 int fallback_aper_order __initdata = 1; /* 64MB */
54 int fallback_aper_force __initdata;
56 int fix_aperture __initdata = 1;
58 /* This code runs before the PCI subsystem is initialized, so just
59 access the northbridge directly. */
61 static u32 __init allocate_aperture(void)
63 u32 aper_size;
64 unsigned long addr;
66 /* aper_size should <= 1G */
67 if (fallback_aper_order > 5)
68 fallback_aper_order = 5;
69 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
72 * Aperture has to be naturally aligned. This means a 2GB aperture
73 * won't have much chance of finding a place in the lower 4GB of
74 * memory. Unfortunately we cannot move it up because that would
75 * make the IOMMU useless.
77 addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
78 aper_size, aper_size);
79 if (!addr) {
80 pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
81 addr, addr + aper_size - 1, aper_size >> 10);
82 return 0;
84 memblock_reserve(addr, aper_size);
85 pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
86 addr, addr + aper_size - 1, aper_size >> 10);
87 register_nosave_region(addr >> PAGE_SHIFT,
88 (addr+aper_size) >> PAGE_SHIFT);
90 return (u32)addr;
94 /* Find a PCI capability */
95 static u32 __init find_cap(int bus, int slot, int func, int cap)
97 int bytes;
98 u8 pos;
100 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
101 PCI_STATUS_CAP_LIST))
102 return 0;
104 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
105 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
106 u8 id;
108 pos &= ~3;
109 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
110 if (id == 0xff)
111 break;
112 if (id == cap)
113 return pos;
114 pos = read_pci_config_byte(bus, slot, func,
115 pos+PCI_CAP_LIST_NEXT);
117 return 0;
120 /* Read a standard AGPv3 bridge header */
121 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
123 u32 apsize;
124 u32 apsizereg;
125 int nbits;
126 u32 aper_low, aper_hi;
127 u64 aper;
128 u32 old_order;
130 pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
131 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
132 if (apsizereg == 0xffffffff) {
133 pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
134 bus, slot, func);
135 return 0;
138 /* old_order could be the value from NB gart setting */
139 old_order = *order;
141 apsize = apsizereg & 0xfff;
142 /* Some BIOS use weird encodings not in the AGPv3 table. */
143 if (apsize & 0xff)
144 apsize |= 0xf00;
145 nbits = hweight16(apsize);
146 *order = 7 - nbits;
147 if ((int)*order < 0) /* < 32MB */
148 *order = 0;
150 aper_low = read_pci_config(bus, slot, func, 0x10);
151 aper_hi = read_pci_config(bus, slot, func, 0x14);
152 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
155 * On some sick chips, APSIZE is 0. It means it wants 4G
156 * so let double check that order, and lets trust AMD NB settings:
158 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
159 bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
160 32 << old_order);
161 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
162 pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
163 bus, slot, func, 32 << *order, apsizereg);
164 *order = old_order;
167 pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
168 bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
169 32 << *order, apsizereg);
171 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
172 return 0;
173 return (u32)aper;
177 * Look for an AGP bridge. Windows only expects the aperture in the
178 * AGP bridge and some BIOS forget to initialize the Northbridge too.
179 * Work around this here.
181 * Do an PCI bus scan by hand because we're running before the PCI
182 * subsystem.
184 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
185 * generically. It's probably overkill to always scan all slots because
186 * the AGP bridges should be always an own bus on the HT hierarchy,
187 * but do it here for future safety.
189 static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
191 int bus, slot, func;
193 /* Poor man's PCI discovery */
194 for (bus = 0; bus < 256; bus++) {
195 for (slot = 0; slot < 32; slot++) {
196 for (func = 0; func < 8; func++) {
197 u32 class, cap;
198 u8 type;
199 class = read_pci_config(bus, slot, func,
200 PCI_CLASS_REVISION);
201 if (class == 0xffffffff)
202 break;
204 switch (class >> 16) {
205 case PCI_CLASS_BRIDGE_HOST:
206 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
207 /* AGP bridge? */
208 cap = find_cap(bus, slot, func,
209 PCI_CAP_ID_AGP);
210 if (!cap)
211 break;
212 *valid_agp = 1;
213 return read_agp(bus, slot, func, cap,
214 order);
217 /* No multi-function device? */
218 type = read_pci_config_byte(bus, slot, func,
219 PCI_HEADER_TYPE);
220 if (!(type & 0x80))
221 break;
225 pr_info("No AGP bridge found\n");
227 return 0;
230 static bool gart_fix_e820 __initdata = true;
232 static int __init parse_gart_mem(char *p)
234 return kstrtobool(p, &gart_fix_e820);
236 early_param("gart_fix_e820", parse_gart_mem);
238 void __init early_gart_iommu_check(void)
241 * in case it is enabled before, esp for kexec/kdump,
242 * previous kernel already enable that. memset called
243 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
244 * or second kernel have different position for GART hole. and new
245 * kernel could use hole as RAM that is still used by GART set by
246 * first kernel
247 * or BIOS forget to put that in reserved.
248 * try to update e820 to make that region as reserved.
250 u32 agp_aper_order = 0;
251 int i, fix, slot, valid_agp = 0;
252 u32 ctl;
253 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
254 u64 aper_base = 0, last_aper_base = 0;
255 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
257 if (!amd_gart_present())
258 return;
260 if (!early_pci_allowed())
261 return;
263 /* This is mostly duplicate of iommu_hole_init */
264 search_agp_bridge(&agp_aper_order, &valid_agp);
266 fix = 0;
267 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
268 int bus;
269 int dev_base, dev_limit;
271 bus = amd_nb_bus_dev_ranges[i].bus;
272 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
273 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
275 for (slot = dev_base; slot < dev_limit; slot++) {
276 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
277 continue;
279 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
280 aper_enabled = ctl & GARTEN;
281 aper_order = (ctl >> 1) & 7;
282 aper_size = (32 * 1024 * 1024) << aper_order;
283 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
284 aper_base <<= 25;
286 if (last_valid) {
287 if ((aper_order != last_aper_order) ||
288 (aper_base != last_aper_base) ||
289 (aper_enabled != last_aper_enabled)) {
290 fix = 1;
291 break;
295 last_aper_order = aper_order;
296 last_aper_base = aper_base;
297 last_aper_enabled = aper_enabled;
298 last_valid = 1;
302 if (!fix && !aper_enabled)
303 return;
305 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
306 fix = 1;
308 if (gart_fix_e820 && !fix && aper_enabled) {
309 if (e820_any_mapped(aper_base, aper_base + aper_size,
310 E820_RAM)) {
311 /* reserve it, so we can reuse it in second kernel */
312 pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
313 aper_base, aper_base + aper_size - 1);
314 e820_add_region(aper_base, aper_size, E820_RESERVED);
315 update_e820();
319 if (valid_agp)
320 return;
322 /* disable them all at first */
323 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
324 int bus;
325 int dev_base, dev_limit;
327 bus = amd_nb_bus_dev_ranges[i].bus;
328 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
329 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
331 for (slot = dev_base; slot < dev_limit; slot++) {
332 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
333 continue;
335 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
336 ctl &= ~GARTEN;
337 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
343 static int __initdata printed_gart_size_msg;
345 int __init gart_iommu_hole_init(void)
347 u32 agp_aper_base = 0, agp_aper_order = 0;
348 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
349 u64 aper_base, last_aper_base = 0;
350 int fix, slot, valid_agp = 0;
351 int i, node;
353 if (!amd_gart_present())
354 return -ENODEV;
356 if (gart_iommu_aperture_disabled || !fix_aperture ||
357 !early_pci_allowed())
358 return -ENODEV;
360 pr_info("Checking aperture...\n");
362 if (!fallback_aper_force)
363 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
365 fix = 0;
366 node = 0;
367 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
368 int bus;
369 int dev_base, dev_limit;
370 u32 ctl;
372 bus = amd_nb_bus_dev_ranges[i].bus;
373 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
374 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
376 for (slot = dev_base; slot < dev_limit; slot++) {
377 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
378 continue;
380 iommu_detected = 1;
381 gart_iommu_aperture = 1;
382 x86_init.iommu.iommu_init = gart_iommu_init;
384 ctl = read_pci_config(bus, slot, 3,
385 AMD64_GARTAPERTURECTL);
388 * Before we do anything else disable the GART. It may
389 * still be enabled if we boot into a crash-kernel here.
390 * Reconfiguring the GART while it is enabled could have
391 * unknown side-effects.
393 ctl &= ~GARTEN;
394 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
396 aper_order = (ctl >> 1) & 7;
397 aper_size = (32 * 1024 * 1024) << aper_order;
398 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
399 aper_base <<= 25;
401 pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
402 node, aper_base, aper_base + aper_size - 1,
403 aper_size >> 20);
404 node++;
406 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
407 if (valid_agp && agp_aper_base &&
408 agp_aper_base == aper_base &&
409 agp_aper_order == aper_order) {
410 /* the same between two setting from NB and agp */
411 if (!no_iommu &&
412 max_pfn > MAX_DMA32_PFN &&
413 !printed_gart_size_msg) {
414 pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
415 pr_err("please increase GART size in your BIOS setup\n");
416 pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
417 printed_gart_size_msg = 1;
419 } else {
420 fix = 1;
421 goto out;
425 if ((last_aper_order && aper_order != last_aper_order) ||
426 (last_aper_base && aper_base != last_aper_base)) {
427 fix = 1;
428 goto out;
430 last_aper_order = aper_order;
431 last_aper_base = aper_base;
435 out:
436 if (!fix && !fallback_aper_force) {
437 if (last_aper_base)
438 return 1;
439 return 0;
442 if (!fallback_aper_force) {
443 aper_alloc = agp_aper_base;
444 aper_order = agp_aper_order;
447 if (aper_alloc) {
448 /* Got the aperture from the AGP bridge */
449 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
450 force_iommu ||
451 valid_agp ||
452 fallback_aper_force) {
453 pr_info("Your BIOS doesn't leave an aperture memory hole\n");
454 pr_info("Please enable the IOMMU option in the BIOS setup\n");
455 pr_info("This costs you %dMB of RAM\n",
456 32 << fallback_aper_order);
458 aper_order = fallback_aper_order;
459 aper_alloc = allocate_aperture();
460 if (!aper_alloc) {
462 * Could disable AGP and IOMMU here, but it's
463 * probably not worth it. But the later users
464 * cannot deal with bad apertures and turning
465 * on the aperture over memory causes very
466 * strange problems, so it's better to panic
467 * early.
469 panic("Not enough memory for aperture");
471 } else {
472 return 0;
475 /* Fix up the north bridges */
476 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
477 int bus, dev_base, dev_limit;
480 * Don't enable translation yet but enable GART IO and CPU
481 * accesses and set DISTLBWALKPRB since GART table memory is UC.
483 u32 ctl = aper_order << 1;
485 bus = amd_nb_bus_dev_ranges[i].bus;
486 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
487 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
488 for (slot = dev_base; slot < dev_limit; slot++) {
489 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
490 continue;
492 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
493 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
497 set_up_gart_resume(aper_order, aper_alloc);
499 return 1;