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[linux/fpc-iii.git] / arch / x86 / kernel / apic / apic.c
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1 /*
2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/module.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/apic.h>
48 #include <asm/io_apic.h>
49 #include <asm/desc.h>
50 #include <asm/hpet.h>
51 #include <asm/idle.h>
52 #include <asm/mtrr.h>
53 #include <asm/time.h>
54 #include <asm/smp.h>
55 #include <asm/mce.h>
56 #include <asm/tsc.h>
57 #include <asm/hypervisor.h>
59 unsigned int num_processors;
61 unsigned disabled_cpus;
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid = -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
68 * The highest APIC ID seen during enumeration.
70 static unsigned int max_physical_apicid;
73 * Bitmask of physically existing CPUs:
75 physid_mask_t phys_cpu_present_map;
78 * Processor to be disabled specified by kernel parameter
79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
80 * avoid undefined behaviour caused by sending INIT from AP to BSP.
82 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
85 * This variable controls which CPUs receive external NMIs. By default,
86 * external NMIs are delivered only to the BSP.
88 static int apic_extnmi = APIC_EXTNMI_BSP;
91 * Map cpu index to physical APIC ID
93 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
95 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
96 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
98 #ifdef CONFIG_X86_32
101 * On x86_32, the mapping between cpu and logical apicid may vary
102 * depending on apic in use. The following early percpu variable is
103 * used for the mapping. This is where the behaviors of x86_64 and 32
104 * actually diverge. Let's keep it ugly for now.
106 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
108 /* Local APIC was disabled by the BIOS and enabled by the kernel */
109 static int enabled_via_apicbase;
112 * Handle interrupt mode configuration register (IMCR).
113 * This register controls whether the interrupt signals
114 * that reach the BSP come from the master PIC or from the
115 * local APIC. Before entering Symmetric I/O Mode, either
116 * the BIOS or the operating system must switch out of
117 * PIC Mode by changing the IMCR.
119 static inline void imcr_pic_to_apic(void)
121 /* select IMCR register */
122 outb(0x70, 0x22);
123 /* NMI and 8259 INTR go through APIC */
124 outb(0x01, 0x23);
127 static inline void imcr_apic_to_pic(void)
129 /* select IMCR register */
130 outb(0x70, 0x22);
131 /* NMI and 8259 INTR go directly to BSP */
132 outb(0x00, 0x23);
134 #endif
137 * Knob to control our willingness to enable the local APIC.
139 * +1=force-enable
141 static int force_enable_local_apic __initdata;
144 * APIC command line parameters
146 static int __init parse_lapic(char *arg)
148 if (config_enabled(CONFIG_X86_32) && !arg)
149 force_enable_local_apic = 1;
150 else if (arg && !strncmp(arg, "notscdeadline", 13))
151 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
152 return 0;
154 early_param("lapic", parse_lapic);
156 #ifdef CONFIG_X86_64
157 static int apic_calibrate_pmtmr __initdata;
158 static __init int setup_apicpmtimer(char *s)
160 apic_calibrate_pmtmr = 1;
161 notsc_setup(NULL);
162 return 0;
164 __setup("apicpmtimer", setup_apicpmtimer);
165 #endif
167 unsigned long mp_lapic_addr;
168 int disable_apic;
169 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
170 static int disable_apic_timer __initdata;
171 /* Local APIC timer works in C2 */
172 int local_apic_timer_c2_ok;
173 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
175 int first_system_vector = FIRST_SYSTEM_VECTOR;
178 * Debug level, exported for io_apic.c
180 unsigned int apic_verbosity;
182 int pic_mode;
184 /* Have we found an MP table */
185 int smp_found_config;
187 static struct resource lapic_resource = {
188 .name = "Local APIC",
189 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
192 unsigned int lapic_timer_frequency = 0;
194 static void apic_pm_activate(void);
196 static unsigned long apic_phys;
199 * Get the LAPIC version
201 static inline int lapic_get_version(void)
203 return GET_APIC_VERSION(apic_read(APIC_LVR));
207 * Check, if the APIC is integrated or a separate chip
209 static inline int lapic_is_integrated(void)
211 #ifdef CONFIG_X86_64
212 return 1;
213 #else
214 return APIC_INTEGRATED(lapic_get_version());
215 #endif
219 * Check, whether this is a modern or a first generation APIC
221 static int modern_apic(void)
223 /* AMD systems use old APIC versions, so check the CPU */
224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
225 boot_cpu_data.x86 >= 0xf)
226 return 1;
227 return lapic_get_version() >= 0x14;
231 * right after this call apic become NOOP driven
232 * so apic->write/read doesn't do anything
234 static void __init apic_disable(void)
236 pr_info("APIC: switched to apic NOOP\n");
237 apic = &apic_noop;
240 void native_apic_wait_icr_idle(void)
242 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
243 cpu_relax();
246 u32 native_safe_apic_wait_icr_idle(void)
248 u32 send_status;
249 int timeout;
251 timeout = 0;
252 do {
253 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
254 if (!send_status)
255 break;
256 inc_irq_stat(icr_read_retry_count);
257 udelay(100);
258 } while (timeout++ < 1000);
260 return send_status;
263 void native_apic_icr_write(u32 low, u32 id)
265 unsigned long flags;
267 local_irq_save(flags);
268 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
269 apic_write(APIC_ICR, low);
270 local_irq_restore(flags);
273 u64 native_apic_icr_read(void)
275 u32 icr1, icr2;
277 icr2 = apic_read(APIC_ICR2);
278 icr1 = apic_read(APIC_ICR);
280 return icr1 | ((u64)icr2 << 32);
283 #ifdef CONFIG_X86_32
285 * get_physical_broadcast - Get number of physical broadcast IDs
287 int get_physical_broadcast(void)
289 return modern_apic() ? 0xff : 0xf;
291 #endif
294 * lapic_get_maxlvt - get the maximum number of local vector table entries
296 int lapic_get_maxlvt(void)
298 unsigned int v;
300 v = apic_read(APIC_LVR);
302 * - we always have APIC integrated on 64bit mode
303 * - 82489DXs do not report # of LVT entries
305 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
309 * Local APIC timer
312 /* Clock divisor */
313 #define APIC_DIVISOR 16
314 #define TSC_DIVISOR 32
317 * This function sets up the local APIC timer, with a timeout of
318 * 'clocks' APIC bus clock. During calibration we actually call
319 * this function twice on the boot CPU, once with a bogus timeout
320 * value, second time for real. The other (noncalibrating) CPUs
321 * call this function only once, with the real, calibrated value.
323 * We do reads before writes even if unnecessary, to get around the
324 * P5 APIC double write bug.
326 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
328 unsigned int lvtt_value, tmp_value;
330 lvtt_value = LOCAL_TIMER_VECTOR;
331 if (!oneshot)
332 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
333 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
334 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
336 if (!lapic_is_integrated())
337 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
339 if (!irqen)
340 lvtt_value |= APIC_LVT_MASKED;
342 apic_write(APIC_LVTT, lvtt_value);
344 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
346 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
347 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
348 * According to Intel, MFENCE can do the serialization here.
350 asm volatile("mfence" : : : "memory");
352 printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
353 return;
357 * Divide PICLK by 16
359 tmp_value = apic_read(APIC_TDCR);
360 apic_write(APIC_TDCR,
361 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
362 APIC_TDR_DIV_16);
364 if (!oneshot)
365 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
369 * Setup extended LVT, AMD specific
371 * Software should use the LVT offsets the BIOS provides. The offsets
372 * are determined by the subsystems using it like those for MCE
373 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
374 * are supported. Beginning with family 10h at least 4 offsets are
375 * available.
377 * Since the offsets must be consistent for all cores, we keep track
378 * of the LVT offsets in software and reserve the offset for the same
379 * vector also to be used on other cores. An offset is freed by
380 * setting the entry to APIC_EILVT_MASKED.
382 * If the BIOS is right, there should be no conflicts. Otherwise a
383 * "[Firmware Bug]: ..." error message is generated. However, if
384 * software does not properly determines the offsets, it is not
385 * necessarily a BIOS bug.
388 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
390 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
392 return (old & APIC_EILVT_MASKED)
393 || (new == APIC_EILVT_MASKED)
394 || ((new & ~APIC_EILVT_MASKED) == old);
397 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
399 unsigned int rsvd, vector;
401 if (offset >= APIC_EILVT_NR_MAX)
402 return ~0;
404 rsvd = atomic_read(&eilvt_offsets[offset]);
405 do {
406 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
407 if (vector && !eilvt_entry_is_changeable(vector, new))
408 /* may not change if vectors are different */
409 return rsvd;
410 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
411 } while (rsvd != new);
413 rsvd &= ~APIC_EILVT_MASKED;
414 if (rsvd && rsvd != vector)
415 pr_info("LVT offset %d assigned for vector 0x%02x\n",
416 offset, rsvd);
418 return new;
422 * If mask=1, the LVT entry does not generate interrupts while mask=0
423 * enables the vector. See also the BKDGs. Must be called with
424 * preemption disabled.
427 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
429 unsigned long reg = APIC_EILVTn(offset);
430 unsigned int new, old, reserved;
432 new = (mask << 16) | (msg_type << 8) | vector;
433 old = apic_read(reg);
434 reserved = reserve_eilvt_offset(offset, new);
436 if (reserved != new) {
437 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
438 "vector 0x%x, but the register is already in use for "
439 "vector 0x%x on another cpu\n",
440 smp_processor_id(), reg, offset, new, reserved);
441 return -EINVAL;
444 if (!eilvt_entry_is_changeable(old, new)) {
445 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
446 "vector 0x%x, but the register is already in use for "
447 "vector 0x%x on this cpu\n",
448 smp_processor_id(), reg, offset, new, old);
449 return -EBUSY;
452 apic_write(reg, new);
454 return 0;
456 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
459 * Program the next event, relative to now
461 static int lapic_next_event(unsigned long delta,
462 struct clock_event_device *evt)
464 apic_write(APIC_TMICT, delta);
465 return 0;
468 static int lapic_next_deadline(unsigned long delta,
469 struct clock_event_device *evt)
471 u64 tsc;
473 tsc = rdtsc();
474 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
475 return 0;
478 static int lapic_timer_shutdown(struct clock_event_device *evt)
480 unsigned int v;
482 /* Lapic used as dummy for broadcast ? */
483 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
484 return 0;
486 v = apic_read(APIC_LVTT);
487 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
488 apic_write(APIC_LVTT, v);
489 apic_write(APIC_TMICT, 0);
490 return 0;
493 static inline int
494 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
496 /* Lapic used as dummy for broadcast ? */
497 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
498 return 0;
500 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
501 return 0;
504 static int lapic_timer_set_periodic(struct clock_event_device *evt)
506 return lapic_timer_set_periodic_oneshot(evt, false);
509 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
511 return lapic_timer_set_periodic_oneshot(evt, true);
515 * Local APIC timer broadcast function
517 static void lapic_timer_broadcast(const struct cpumask *mask)
519 #ifdef CONFIG_SMP
520 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
521 #endif
526 * The local apic timer can be used for any function which is CPU local.
528 static struct clock_event_device lapic_clockevent = {
529 .name = "lapic",
530 .features = CLOCK_EVT_FEAT_PERIODIC |
531 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
532 | CLOCK_EVT_FEAT_DUMMY,
533 .shift = 32,
534 .set_state_shutdown = lapic_timer_shutdown,
535 .set_state_periodic = lapic_timer_set_periodic,
536 .set_state_oneshot = lapic_timer_set_oneshot,
537 .set_next_event = lapic_next_event,
538 .broadcast = lapic_timer_broadcast,
539 .rating = 100,
540 .irq = -1,
542 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
545 * Setup the local APIC timer for this CPU. Copy the initialized values
546 * of the boot CPU and register the clock event in the framework.
548 static void setup_APIC_timer(void)
550 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
552 if (this_cpu_has(X86_FEATURE_ARAT)) {
553 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
554 /* Make LAPIC timer preferrable over percpu HPET */
555 lapic_clockevent.rating = 150;
558 memcpy(levt, &lapic_clockevent, sizeof(*levt));
559 levt->cpumask = cpumask_of(smp_processor_id());
561 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
562 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
563 CLOCK_EVT_FEAT_DUMMY);
564 levt->set_next_event = lapic_next_deadline;
565 clockevents_config_and_register(levt,
566 (tsc_khz / TSC_DIVISOR) * 1000,
567 0xF, ~0UL);
568 } else
569 clockevents_register_device(levt);
573 * In this functions we calibrate APIC bus clocks to the external timer.
575 * We want to do the calibration only once since we want to have local timer
576 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
577 * frequency.
579 * This was previously done by reading the PIT/HPET and waiting for a wrap
580 * around to find out, that a tick has elapsed. I have a box, where the PIT
581 * readout is broken, so it never gets out of the wait loop again. This was
582 * also reported by others.
584 * Monitoring the jiffies value is inaccurate and the clockevents
585 * infrastructure allows us to do a simple substitution of the interrupt
586 * handler.
588 * The calibration routine also uses the pm_timer when possible, as the PIT
589 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
590 * back to normal later in the boot process).
593 #define LAPIC_CAL_LOOPS (HZ/10)
595 static __initdata int lapic_cal_loops = -1;
596 static __initdata long lapic_cal_t1, lapic_cal_t2;
597 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
598 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
599 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
602 * Temporary interrupt handler.
604 static void __init lapic_cal_handler(struct clock_event_device *dev)
606 unsigned long long tsc = 0;
607 long tapic = apic_read(APIC_TMCCT);
608 unsigned long pm = acpi_pm_read_early();
610 if (cpu_has_tsc)
611 tsc = rdtsc();
613 switch (lapic_cal_loops++) {
614 case 0:
615 lapic_cal_t1 = tapic;
616 lapic_cal_tsc1 = tsc;
617 lapic_cal_pm1 = pm;
618 lapic_cal_j1 = jiffies;
619 break;
621 case LAPIC_CAL_LOOPS:
622 lapic_cal_t2 = tapic;
623 lapic_cal_tsc2 = tsc;
624 if (pm < lapic_cal_pm1)
625 pm += ACPI_PM_OVRRUN;
626 lapic_cal_pm2 = pm;
627 lapic_cal_j2 = jiffies;
628 break;
632 static int __init
633 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
635 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
636 const long pm_thresh = pm_100ms / 100;
637 unsigned long mult;
638 u64 res;
640 #ifndef CONFIG_X86_PM_TIMER
641 return -1;
642 #endif
644 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
646 /* Check, if the PM timer is available */
647 if (!deltapm)
648 return -1;
650 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
652 if (deltapm > (pm_100ms - pm_thresh) &&
653 deltapm < (pm_100ms + pm_thresh)) {
654 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
655 return 0;
658 res = (((u64)deltapm) * mult) >> 22;
659 do_div(res, 1000000);
660 pr_warning("APIC calibration not consistent "
661 "with PM-Timer: %ldms instead of 100ms\n",(long)res);
663 /* Correct the lapic counter value */
664 res = (((u64)(*delta)) * pm_100ms);
665 do_div(res, deltapm);
666 pr_info("APIC delta adjusted to PM-Timer: "
667 "%lu (%ld)\n", (unsigned long)res, *delta);
668 *delta = (long)res;
670 /* Correct the tsc counter value */
671 if (cpu_has_tsc) {
672 res = (((u64)(*deltatsc)) * pm_100ms);
673 do_div(res, deltapm);
674 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
675 "PM-Timer: %lu (%ld)\n",
676 (unsigned long)res, *deltatsc);
677 *deltatsc = (long)res;
680 return 0;
683 static int __init calibrate_APIC_clock(void)
685 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
686 void (*real_handler)(struct clock_event_device *dev);
687 unsigned long deltaj;
688 long delta, deltatsc;
689 int pm_referenced = 0;
692 * check if lapic timer has already been calibrated by platform
693 * specific routine, such as tsc calibration code. if so, we just fill
694 * in the clockevent structure and return.
697 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
698 return 0;
699 } else if (lapic_timer_frequency) {
700 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
701 lapic_timer_frequency);
702 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
703 TICK_NSEC, lapic_clockevent.shift);
704 lapic_clockevent.max_delta_ns =
705 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
706 lapic_clockevent.min_delta_ns =
707 clockevent_delta2ns(0xF, &lapic_clockevent);
708 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
709 return 0;
712 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
713 "calibrating APIC timer ...\n");
715 local_irq_disable();
717 /* Replace the global interrupt handler */
718 real_handler = global_clock_event->event_handler;
719 global_clock_event->event_handler = lapic_cal_handler;
722 * Setup the APIC counter to maximum. There is no way the lapic
723 * can underflow in the 100ms detection time frame
725 __setup_APIC_LVTT(0xffffffff, 0, 0);
727 /* Let the interrupts run */
728 local_irq_enable();
730 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
731 cpu_relax();
733 local_irq_disable();
735 /* Restore the real event handler */
736 global_clock_event->event_handler = real_handler;
738 /* Build delta t1-t2 as apic timer counts down */
739 delta = lapic_cal_t1 - lapic_cal_t2;
740 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
742 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
744 /* we trust the PM based calibration if possible */
745 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
746 &delta, &deltatsc);
748 /* Calculate the scaled math multiplication factor */
749 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
750 lapic_clockevent.shift);
751 lapic_clockevent.max_delta_ns =
752 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
753 lapic_clockevent.min_delta_ns =
754 clockevent_delta2ns(0xF, &lapic_clockevent);
756 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
758 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
759 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
760 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
761 lapic_timer_frequency);
763 if (cpu_has_tsc) {
764 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
765 "%ld.%04ld MHz.\n",
766 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
767 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
770 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
771 "%u.%04u MHz.\n",
772 lapic_timer_frequency / (1000000 / HZ),
773 lapic_timer_frequency % (1000000 / HZ));
776 * Do a sanity check on the APIC calibration result
778 if (lapic_timer_frequency < (1000000 / HZ)) {
779 local_irq_enable();
780 pr_warning("APIC frequency too slow, disabling apic timer\n");
781 return -1;
784 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
787 * PM timer calibration failed or not turned on
788 * so lets try APIC timer based calibration
790 if (!pm_referenced) {
791 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
794 * Setup the apic timer manually
796 levt->event_handler = lapic_cal_handler;
797 lapic_timer_set_periodic(levt);
798 lapic_cal_loops = -1;
800 /* Let the interrupts run */
801 local_irq_enable();
803 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
804 cpu_relax();
806 /* Stop the lapic timer */
807 local_irq_disable();
808 lapic_timer_shutdown(levt);
810 /* Jiffies delta */
811 deltaj = lapic_cal_j2 - lapic_cal_j1;
812 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
814 /* Check, if the jiffies result is consistent */
815 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
816 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
817 else
818 levt->features |= CLOCK_EVT_FEAT_DUMMY;
820 local_irq_enable();
822 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
823 pr_warning("APIC timer disabled due to verification failure\n");
824 return -1;
827 return 0;
831 * Setup the boot APIC
833 * Calibrate and verify the result.
835 void __init setup_boot_APIC_clock(void)
838 * The local apic timer can be disabled via the kernel
839 * commandline or from the CPU detection code. Register the lapic
840 * timer as a dummy clock event source on SMP systems, so the
841 * broadcast mechanism is used. On UP systems simply ignore it.
843 if (disable_apic_timer) {
844 pr_info("Disabling APIC timer\n");
845 /* No broadcast on UP ! */
846 if (num_possible_cpus() > 1) {
847 lapic_clockevent.mult = 1;
848 setup_APIC_timer();
850 return;
853 if (calibrate_APIC_clock()) {
854 /* No broadcast on UP ! */
855 if (num_possible_cpus() > 1)
856 setup_APIC_timer();
857 return;
861 * If nmi_watchdog is set to IO_APIC, we need the
862 * PIT/HPET going. Otherwise register lapic as a dummy
863 * device.
865 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
867 /* Setup the lapic or request the broadcast */
868 setup_APIC_timer();
871 void setup_secondary_APIC_clock(void)
873 setup_APIC_timer();
877 * The guts of the apic timer interrupt
879 static void local_apic_timer_interrupt(void)
881 int cpu = smp_processor_id();
882 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
885 * Normally we should not be here till LAPIC has been initialized but
886 * in some cases like kdump, its possible that there is a pending LAPIC
887 * timer interrupt from previous kernel's context and is delivered in
888 * new kernel the moment interrupts are enabled.
890 * Interrupts are enabled early and LAPIC is setup much later, hence
891 * its possible that when we get here evt->event_handler is NULL.
892 * Check for event_handler being NULL and discard the interrupt as
893 * spurious.
895 if (!evt->event_handler) {
896 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
897 /* Switch it off */
898 lapic_timer_shutdown(evt);
899 return;
903 * the NMI deadlock-detector uses this.
905 inc_irq_stat(apic_timer_irqs);
907 evt->event_handler(evt);
911 * Local APIC timer interrupt. This is the most natural way for doing
912 * local interrupts, but local timer interrupts can be emulated by
913 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
915 * [ if a single-CPU system runs an SMP kernel then we call the local
916 * interrupt as well. Thus we cannot inline the local irq ... ]
918 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
920 struct pt_regs *old_regs = set_irq_regs(regs);
923 * NOTE! We'd better ACK the irq immediately,
924 * because timer handling can be slow.
926 * update_process_times() expects us to have done irq_enter().
927 * Besides, if we don't timer interrupts ignore the global
928 * interrupt lock, which is the WrongThing (tm) to do.
930 entering_ack_irq();
931 local_apic_timer_interrupt();
932 exiting_irq();
934 set_irq_regs(old_regs);
937 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
939 struct pt_regs *old_regs = set_irq_regs(regs);
942 * NOTE! We'd better ACK the irq immediately,
943 * because timer handling can be slow.
945 * update_process_times() expects us to have done irq_enter().
946 * Besides, if we don't timer interrupts ignore the global
947 * interrupt lock, which is the WrongThing (tm) to do.
949 entering_ack_irq();
950 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
951 local_apic_timer_interrupt();
952 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
953 exiting_irq();
955 set_irq_regs(old_regs);
958 int setup_profiling_timer(unsigned int multiplier)
960 return -EINVAL;
964 * Local APIC start and shutdown
968 * clear_local_APIC - shutdown the local APIC
970 * This is called, when a CPU is disabled and before rebooting, so the state of
971 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
972 * leftovers during boot.
974 void clear_local_APIC(void)
976 int maxlvt;
977 u32 v;
979 /* APIC hasn't been mapped yet */
980 if (!x2apic_mode && !apic_phys)
981 return;
983 maxlvt = lapic_get_maxlvt();
985 * Masking an LVT entry can trigger a local APIC error
986 * if the vector is zero. Mask LVTERR first to prevent this.
988 if (maxlvt >= 3) {
989 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
990 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
993 * Careful: we have to set masks only first to deassert
994 * any level-triggered sources.
996 v = apic_read(APIC_LVTT);
997 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
998 v = apic_read(APIC_LVT0);
999 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1000 v = apic_read(APIC_LVT1);
1001 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1002 if (maxlvt >= 4) {
1003 v = apic_read(APIC_LVTPC);
1004 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1007 /* lets not touch this if we didn't frob it */
1008 #ifdef CONFIG_X86_THERMAL_VECTOR
1009 if (maxlvt >= 5) {
1010 v = apic_read(APIC_LVTTHMR);
1011 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1013 #endif
1014 #ifdef CONFIG_X86_MCE_INTEL
1015 if (maxlvt >= 6) {
1016 v = apic_read(APIC_LVTCMCI);
1017 if (!(v & APIC_LVT_MASKED))
1018 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1020 #endif
1023 * Clean APIC state for other OSs:
1025 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1026 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1027 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1028 if (maxlvt >= 3)
1029 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1030 if (maxlvt >= 4)
1031 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1033 /* Integrated APIC (!82489DX) ? */
1034 if (lapic_is_integrated()) {
1035 if (maxlvt > 3)
1036 /* Clear ESR due to Pentium errata 3AP and 11AP */
1037 apic_write(APIC_ESR, 0);
1038 apic_read(APIC_ESR);
1043 * disable_local_APIC - clear and disable the local APIC
1045 void disable_local_APIC(void)
1047 unsigned int value;
1049 /* APIC hasn't been mapped yet */
1050 if (!x2apic_mode && !apic_phys)
1051 return;
1053 clear_local_APIC();
1056 * Disable APIC (implies clearing of registers
1057 * for 82489DX!).
1059 value = apic_read(APIC_SPIV);
1060 value &= ~APIC_SPIV_APIC_ENABLED;
1061 apic_write(APIC_SPIV, value);
1063 #ifdef CONFIG_X86_32
1065 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1066 * restore the disabled state.
1068 if (enabled_via_apicbase) {
1069 unsigned int l, h;
1071 rdmsr(MSR_IA32_APICBASE, l, h);
1072 l &= ~MSR_IA32_APICBASE_ENABLE;
1073 wrmsr(MSR_IA32_APICBASE, l, h);
1075 #endif
1079 * If Linux enabled the LAPIC against the BIOS default disable it down before
1080 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1081 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1082 * for the case where Linux didn't enable the LAPIC.
1084 void lapic_shutdown(void)
1086 unsigned long flags;
1088 if (!cpu_has_apic && !apic_from_smp_config())
1089 return;
1091 local_irq_save(flags);
1093 #ifdef CONFIG_X86_32
1094 if (!enabled_via_apicbase)
1095 clear_local_APIC();
1096 else
1097 #endif
1098 disable_local_APIC();
1101 local_irq_restore(flags);
1105 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1107 void __init sync_Arb_IDs(void)
1110 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1111 * needed on AMD.
1113 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1114 return;
1117 * Wait for idle.
1119 apic_wait_icr_idle();
1121 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1122 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1123 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1127 * An initial setup of the virtual wire mode.
1129 void __init init_bsp_APIC(void)
1131 unsigned int value;
1134 * Don't do the setup now if we have a SMP BIOS as the
1135 * through-I/O-APIC virtual wire mode might be active.
1137 if (smp_found_config || !cpu_has_apic)
1138 return;
1141 * Do not trust the local APIC being empty at bootup.
1143 clear_local_APIC();
1146 * Enable APIC.
1148 value = apic_read(APIC_SPIV);
1149 value &= ~APIC_VECTOR_MASK;
1150 value |= APIC_SPIV_APIC_ENABLED;
1152 #ifdef CONFIG_X86_32
1153 /* This bit is reserved on P4/Xeon and should be cleared */
1154 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1155 (boot_cpu_data.x86 == 15))
1156 value &= ~APIC_SPIV_FOCUS_DISABLED;
1157 else
1158 #endif
1159 value |= APIC_SPIV_FOCUS_DISABLED;
1160 value |= SPURIOUS_APIC_VECTOR;
1161 apic_write(APIC_SPIV, value);
1164 * Set up the virtual wire mode.
1166 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1167 value = APIC_DM_NMI;
1168 if (!lapic_is_integrated()) /* 82489DX */
1169 value |= APIC_LVT_LEVEL_TRIGGER;
1170 if (apic_extnmi == APIC_EXTNMI_NONE)
1171 value |= APIC_LVT_MASKED;
1172 apic_write(APIC_LVT1, value);
1175 static void lapic_setup_esr(void)
1177 unsigned int oldvalue, value, maxlvt;
1179 if (!lapic_is_integrated()) {
1180 pr_info("No ESR for 82489DX.\n");
1181 return;
1184 if (apic->disable_esr) {
1186 * Something untraceable is creating bad interrupts on
1187 * secondary quads ... for the moment, just leave the
1188 * ESR disabled - we can't do anything useful with the
1189 * errors anyway - mbligh
1191 pr_info("Leaving ESR disabled.\n");
1192 return;
1195 maxlvt = lapic_get_maxlvt();
1196 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1197 apic_write(APIC_ESR, 0);
1198 oldvalue = apic_read(APIC_ESR);
1200 /* enables sending errors */
1201 value = ERROR_APIC_VECTOR;
1202 apic_write(APIC_LVTERR, value);
1205 * spec says clear errors after enabling vector.
1207 if (maxlvt > 3)
1208 apic_write(APIC_ESR, 0);
1209 value = apic_read(APIC_ESR);
1210 if (value != oldvalue)
1211 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1212 "vector: 0x%08x after: 0x%08x\n",
1213 oldvalue, value);
1217 * setup_local_APIC - setup the local APIC
1219 * Used to setup local APIC while initializing BSP or bringin up APs.
1220 * Always called with preemption disabled.
1222 void setup_local_APIC(void)
1224 int cpu = smp_processor_id();
1225 unsigned int value, queued;
1226 int i, j, acked = 0;
1227 unsigned long long tsc = 0, ntsc;
1228 long long max_loops = cpu_khz ? cpu_khz : 1000000;
1230 if (cpu_has_tsc)
1231 tsc = rdtsc();
1233 if (disable_apic) {
1234 disable_ioapic_support();
1235 return;
1238 #ifdef CONFIG_X86_32
1239 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1240 if (lapic_is_integrated() && apic->disable_esr) {
1241 apic_write(APIC_ESR, 0);
1242 apic_write(APIC_ESR, 0);
1243 apic_write(APIC_ESR, 0);
1244 apic_write(APIC_ESR, 0);
1246 #endif
1247 perf_events_lapic_init();
1250 * Double-check whether this APIC is really registered.
1251 * This is meaningless in clustered apic mode, so we skip it.
1253 BUG_ON(!apic->apic_id_registered());
1256 * Intel recommends to set DFR, LDR and TPR before enabling
1257 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1258 * document number 292116). So here it goes...
1260 apic->init_apic_ldr();
1262 #ifdef CONFIG_X86_32
1264 * APIC LDR is initialized. If logical_apicid mapping was
1265 * initialized during get_smp_config(), make sure it matches the
1266 * actual value.
1268 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1269 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1270 /* always use the value from LDR */
1271 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1272 logical_smp_processor_id();
1273 #endif
1276 * Set Task Priority to 'accept all'. We never change this
1277 * later on.
1279 value = apic_read(APIC_TASKPRI);
1280 value &= ~APIC_TPRI_MASK;
1281 apic_write(APIC_TASKPRI, value);
1284 * After a crash, we no longer service the interrupts and a pending
1285 * interrupt from previous kernel might still have ISR bit set.
1287 * Most probably by now CPU has serviced that pending interrupt and
1288 * it might not have done the ack_APIC_irq() because it thought,
1289 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1290 * does not clear the ISR bit and cpu thinks it has already serivced
1291 * the interrupt. Hence a vector might get locked. It was noticed
1292 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1294 do {
1295 queued = 0;
1296 for (i = APIC_ISR_NR - 1; i >= 0; i--)
1297 queued |= apic_read(APIC_IRR + i*0x10);
1299 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1300 value = apic_read(APIC_ISR + i*0x10);
1301 for (j = 31; j >= 0; j--) {
1302 if (value & (1<<j)) {
1303 ack_APIC_irq();
1304 acked++;
1308 if (acked > 256) {
1309 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1310 acked);
1311 break;
1313 if (queued) {
1314 if (cpu_has_tsc && cpu_khz) {
1315 ntsc = rdtsc();
1316 max_loops = (cpu_khz << 10) - (ntsc - tsc);
1317 } else
1318 max_loops--;
1320 } while (queued && max_loops > 0);
1321 WARN_ON(max_loops <= 0);
1324 * Now that we are all set up, enable the APIC
1326 value = apic_read(APIC_SPIV);
1327 value &= ~APIC_VECTOR_MASK;
1329 * Enable APIC
1331 value |= APIC_SPIV_APIC_ENABLED;
1333 #ifdef CONFIG_X86_32
1335 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1336 * certain networking cards. If high frequency interrupts are
1337 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1338 * entry is masked/unmasked at a high rate as well then sooner or
1339 * later IOAPIC line gets 'stuck', no more interrupts are received
1340 * from the device. If focus CPU is disabled then the hang goes
1341 * away, oh well :-(
1343 * [ This bug can be reproduced easily with a level-triggered
1344 * PCI Ne2000 networking cards and PII/PIII processors, dual
1345 * BX chipset. ]
1348 * Actually disabling the focus CPU check just makes the hang less
1349 * frequent as it makes the interrupt distributon model be more
1350 * like LRU than MRU (the short-term load is more even across CPUs).
1351 * See also the comment in end_level_ioapic_irq(). --macro
1355 * - enable focus processor (bit==0)
1356 * - 64bit mode always use processor focus
1357 * so no need to set it
1359 value &= ~APIC_SPIV_FOCUS_DISABLED;
1360 #endif
1363 * Set spurious IRQ vector
1365 value |= SPURIOUS_APIC_VECTOR;
1366 apic_write(APIC_SPIV, value);
1369 * Set up LVT0, LVT1:
1371 * set up through-local-APIC on the BP's LINT0. This is not
1372 * strictly necessary in pure symmetric-IO mode, but sometimes
1373 * we delegate interrupts to the 8259A.
1376 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1378 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1379 if (!cpu && (pic_mode || !value)) {
1380 value = APIC_DM_EXTINT;
1381 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1382 } else {
1383 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1384 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1386 apic_write(APIC_LVT0, value);
1389 * Only the BSP sees the LINT1 NMI signal by default. This can be
1390 * modified by apic_extnmi= boot option.
1392 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1393 apic_extnmi == APIC_EXTNMI_ALL)
1394 value = APIC_DM_NMI;
1395 else
1396 value = APIC_DM_NMI | APIC_LVT_MASKED;
1397 if (!lapic_is_integrated()) /* 82489DX */
1398 value |= APIC_LVT_LEVEL_TRIGGER;
1399 apic_write(APIC_LVT1, value);
1401 #ifdef CONFIG_X86_MCE_INTEL
1402 /* Recheck CMCI information after local APIC is up on CPU #0 */
1403 if (!cpu)
1404 cmci_recheck();
1405 #endif
1408 static void end_local_APIC_setup(void)
1410 lapic_setup_esr();
1412 #ifdef CONFIG_X86_32
1414 unsigned int value;
1415 /* Disable the local apic timer */
1416 value = apic_read(APIC_LVTT);
1417 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1418 apic_write(APIC_LVTT, value);
1420 #endif
1422 apic_pm_activate();
1426 * APIC setup function for application processors. Called from smpboot.c
1428 void apic_ap_setup(void)
1430 setup_local_APIC();
1431 end_local_APIC_setup();
1434 #ifdef CONFIG_X86_X2APIC
1435 int x2apic_mode;
1437 enum {
1438 X2APIC_OFF,
1439 X2APIC_ON,
1440 X2APIC_DISABLED,
1442 static int x2apic_state;
1444 static void __x2apic_disable(void)
1446 u64 msr;
1448 if (!cpu_has_apic)
1449 return;
1451 rdmsrl(MSR_IA32_APICBASE, msr);
1452 if (!(msr & X2APIC_ENABLE))
1453 return;
1454 /* Disable xapic and x2apic first and then reenable xapic mode */
1455 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1456 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1457 printk_once(KERN_INFO "x2apic disabled\n");
1460 static void __x2apic_enable(void)
1462 u64 msr;
1464 rdmsrl(MSR_IA32_APICBASE, msr);
1465 if (msr & X2APIC_ENABLE)
1466 return;
1467 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1468 printk_once(KERN_INFO "x2apic enabled\n");
1471 static int __init setup_nox2apic(char *str)
1473 if (x2apic_enabled()) {
1474 int apicid = native_apic_msr_read(APIC_ID);
1476 if (apicid >= 255) {
1477 pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1478 apicid);
1479 return 0;
1481 pr_warning("x2apic already enabled.\n");
1482 __x2apic_disable();
1484 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1485 x2apic_state = X2APIC_DISABLED;
1486 x2apic_mode = 0;
1487 return 0;
1489 early_param("nox2apic", setup_nox2apic);
1491 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1492 void x2apic_setup(void)
1495 * If x2apic is not in ON state, disable it if already enabled
1496 * from BIOS.
1498 if (x2apic_state != X2APIC_ON) {
1499 __x2apic_disable();
1500 return;
1502 __x2apic_enable();
1505 static __init void x2apic_disable(void)
1507 u32 x2apic_id, state = x2apic_state;
1509 x2apic_mode = 0;
1510 x2apic_state = X2APIC_DISABLED;
1512 if (state != X2APIC_ON)
1513 return;
1515 x2apic_id = read_apic_id();
1516 if (x2apic_id >= 255)
1517 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1519 __x2apic_disable();
1520 register_lapic_address(mp_lapic_addr);
1523 static __init void x2apic_enable(void)
1525 if (x2apic_state != X2APIC_OFF)
1526 return;
1528 x2apic_mode = 1;
1529 x2apic_state = X2APIC_ON;
1530 __x2apic_enable();
1533 static __init void try_to_enable_x2apic(int remap_mode)
1535 if (x2apic_state == X2APIC_DISABLED)
1536 return;
1538 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1539 /* IR is required if there is APIC ID > 255 even when running
1540 * under KVM
1542 if (max_physical_apicid > 255 ||
1543 !hypervisor_x2apic_available()) {
1544 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1545 x2apic_disable();
1546 return;
1550 * without IR all CPUs can be addressed by IOAPIC/MSI
1551 * only in physical mode
1553 x2apic_phys = 1;
1555 x2apic_enable();
1558 void __init check_x2apic(void)
1560 if (x2apic_enabled()) {
1561 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1562 x2apic_mode = 1;
1563 x2apic_state = X2APIC_ON;
1564 } else if (!cpu_has_x2apic) {
1565 x2apic_state = X2APIC_DISABLED;
1568 #else /* CONFIG_X86_X2APIC */
1569 static int __init validate_x2apic(void)
1571 if (!apic_is_x2apic_enabled())
1572 return 0;
1574 * Checkme: Can we simply turn off x2apic here instead of panic?
1576 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1578 early_initcall(validate_x2apic);
1580 static inline void try_to_enable_x2apic(int remap_mode) { }
1581 static inline void __x2apic_enable(void) { }
1582 #endif /* !CONFIG_X86_X2APIC */
1584 static int __init try_to_enable_IR(void)
1586 #ifdef CONFIG_X86_IO_APIC
1587 if (!x2apic_enabled() && skip_ioapic_setup) {
1588 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1589 return -1;
1591 #endif
1592 return irq_remapping_enable();
1595 void __init enable_IR_x2apic(void)
1597 unsigned long flags;
1598 int ret, ir_stat;
1600 ir_stat = irq_remapping_prepare();
1601 if (ir_stat < 0 && !x2apic_supported())
1602 return;
1604 ret = save_ioapic_entries();
1605 if (ret) {
1606 pr_info("Saving IO-APIC state failed: %d\n", ret);
1607 return;
1610 local_irq_save(flags);
1611 legacy_pic->mask_all();
1612 mask_ioapic_entries();
1614 /* If irq_remapping_prepare() succeeded, try to enable it */
1615 if (ir_stat >= 0)
1616 ir_stat = try_to_enable_IR();
1617 /* ir_stat contains the remap mode or an error code */
1618 try_to_enable_x2apic(ir_stat);
1620 if (ir_stat < 0)
1621 restore_ioapic_entries();
1622 legacy_pic->restore_mask();
1623 local_irq_restore(flags);
1626 #ifdef CONFIG_X86_64
1628 * Detect and enable local APICs on non-SMP boards.
1629 * Original code written by Keir Fraser.
1630 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1631 * not correctly set up (usually the APIC timer won't work etc.)
1633 static int __init detect_init_APIC(void)
1635 if (!cpu_has_apic) {
1636 pr_info("No local APIC present\n");
1637 return -1;
1640 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1641 return 0;
1643 #else
1645 static int __init apic_verify(void)
1647 u32 features, h, l;
1650 * The APIC feature bit should now be enabled
1651 * in `cpuid'
1653 features = cpuid_edx(1);
1654 if (!(features & (1 << X86_FEATURE_APIC))) {
1655 pr_warning("Could not enable APIC!\n");
1656 return -1;
1658 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1659 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1661 /* The BIOS may have set up the APIC at some other address */
1662 if (boot_cpu_data.x86 >= 6) {
1663 rdmsr(MSR_IA32_APICBASE, l, h);
1664 if (l & MSR_IA32_APICBASE_ENABLE)
1665 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1668 pr_info("Found and enabled local APIC!\n");
1669 return 0;
1672 int __init apic_force_enable(unsigned long addr)
1674 u32 h, l;
1676 if (disable_apic)
1677 return -1;
1680 * Some BIOSes disable the local APIC in the APIC_BASE
1681 * MSR. This can only be done in software for Intel P6 or later
1682 * and AMD K7 (Model > 1) or later.
1684 if (boot_cpu_data.x86 >= 6) {
1685 rdmsr(MSR_IA32_APICBASE, l, h);
1686 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1687 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1688 l &= ~MSR_IA32_APICBASE_BASE;
1689 l |= MSR_IA32_APICBASE_ENABLE | addr;
1690 wrmsr(MSR_IA32_APICBASE, l, h);
1691 enabled_via_apicbase = 1;
1694 return apic_verify();
1698 * Detect and initialize APIC
1700 static int __init detect_init_APIC(void)
1702 /* Disabled by kernel option? */
1703 if (disable_apic)
1704 return -1;
1706 switch (boot_cpu_data.x86_vendor) {
1707 case X86_VENDOR_AMD:
1708 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1709 (boot_cpu_data.x86 >= 15))
1710 break;
1711 goto no_apic;
1712 case X86_VENDOR_INTEL:
1713 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1714 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1715 break;
1716 goto no_apic;
1717 default:
1718 goto no_apic;
1721 if (!cpu_has_apic) {
1723 * Over-ride BIOS and try to enable the local APIC only if
1724 * "lapic" specified.
1726 if (!force_enable_local_apic) {
1727 pr_info("Local APIC disabled by BIOS -- "
1728 "you can enable it with \"lapic\"\n");
1729 return -1;
1731 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1732 return -1;
1733 } else {
1734 if (apic_verify())
1735 return -1;
1738 apic_pm_activate();
1740 return 0;
1742 no_apic:
1743 pr_info("No local APIC present or hardware disabled\n");
1744 return -1;
1746 #endif
1749 * init_apic_mappings - initialize APIC mappings
1751 void __init init_apic_mappings(void)
1753 unsigned int new_apicid;
1755 if (x2apic_mode) {
1756 boot_cpu_physical_apicid = read_apic_id();
1757 return;
1760 /* If no local APIC can be found return early */
1761 if (!smp_found_config && detect_init_APIC()) {
1762 /* lets NOP'ify apic operations */
1763 pr_info("APIC: disable apic facility\n");
1764 apic_disable();
1765 } else {
1766 apic_phys = mp_lapic_addr;
1769 * acpi lapic path already maps that address in
1770 * acpi_register_lapic_address()
1772 if (!acpi_lapic && !smp_found_config)
1773 register_lapic_address(apic_phys);
1777 * Fetch the APIC ID of the BSP in case we have a
1778 * default configuration (or the MP table is broken).
1780 new_apicid = read_apic_id();
1781 if (boot_cpu_physical_apicid != new_apicid) {
1782 boot_cpu_physical_apicid = new_apicid;
1784 * yeah -- we lie about apic_version
1785 * in case if apic was disabled via boot option
1786 * but it's not a problem for SMP compiled kernel
1787 * since smp_sanity_check is prepared for such a case
1788 * and disable smp mode
1790 apic_version[new_apicid] =
1791 GET_APIC_VERSION(apic_read(APIC_LVR));
1795 void __init register_lapic_address(unsigned long address)
1797 mp_lapic_addr = address;
1799 if (!x2apic_mode) {
1800 set_fixmap_nocache(FIX_APIC_BASE, address);
1801 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1802 APIC_BASE, mp_lapic_addr);
1804 if (boot_cpu_physical_apicid == -1U) {
1805 boot_cpu_physical_apicid = read_apic_id();
1806 apic_version[boot_cpu_physical_apicid] =
1807 GET_APIC_VERSION(apic_read(APIC_LVR));
1811 int apic_version[MAX_LOCAL_APIC];
1814 * Local APIC interrupts
1818 * This interrupt should _never_ happen with our APIC/SMP architecture
1820 static void __smp_spurious_interrupt(u8 vector)
1822 u32 v;
1825 * Check if this really is a spurious interrupt and ACK it
1826 * if it is a vectored one. Just in case...
1827 * Spurious interrupts should not be ACKed.
1829 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1830 if (v & (1 << (vector & 0x1f)))
1831 ack_APIC_irq();
1833 inc_irq_stat(irq_spurious_count);
1835 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1836 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1837 "should never happen.\n", vector, smp_processor_id());
1840 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1842 entering_irq();
1843 __smp_spurious_interrupt(~regs->orig_ax);
1844 exiting_irq();
1847 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1849 u8 vector = ~regs->orig_ax;
1851 entering_irq();
1852 trace_spurious_apic_entry(vector);
1853 __smp_spurious_interrupt(vector);
1854 trace_spurious_apic_exit(vector);
1855 exiting_irq();
1859 * This interrupt should never happen with our APIC/SMP architecture
1861 static void __smp_error_interrupt(struct pt_regs *regs)
1863 u32 v;
1864 u32 i = 0;
1865 static const char * const error_interrupt_reason[] = {
1866 "Send CS error", /* APIC Error Bit 0 */
1867 "Receive CS error", /* APIC Error Bit 1 */
1868 "Send accept error", /* APIC Error Bit 2 */
1869 "Receive accept error", /* APIC Error Bit 3 */
1870 "Redirectable IPI", /* APIC Error Bit 4 */
1871 "Send illegal vector", /* APIC Error Bit 5 */
1872 "Received illegal vector", /* APIC Error Bit 6 */
1873 "Illegal register address", /* APIC Error Bit 7 */
1876 /* First tickle the hardware, only then report what went on. -- REW */
1877 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
1878 apic_write(APIC_ESR, 0);
1879 v = apic_read(APIC_ESR);
1880 ack_APIC_irq();
1881 atomic_inc(&irq_err_count);
1883 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1884 smp_processor_id(), v);
1886 v &= 0xff;
1887 while (v) {
1888 if (v & 0x1)
1889 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1890 i++;
1891 v >>= 1;
1894 apic_printk(APIC_DEBUG, KERN_CONT "\n");
1898 __visible void smp_error_interrupt(struct pt_regs *regs)
1900 entering_irq();
1901 __smp_error_interrupt(regs);
1902 exiting_irq();
1905 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
1907 entering_irq();
1908 trace_error_apic_entry(ERROR_APIC_VECTOR);
1909 __smp_error_interrupt(regs);
1910 trace_error_apic_exit(ERROR_APIC_VECTOR);
1911 exiting_irq();
1915 * connect_bsp_APIC - attach the APIC to the interrupt system
1917 static void __init connect_bsp_APIC(void)
1919 #ifdef CONFIG_X86_32
1920 if (pic_mode) {
1922 * Do not trust the local APIC being empty at bootup.
1924 clear_local_APIC();
1926 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1927 * local APIC to INT and NMI lines.
1929 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1930 "enabling APIC mode.\n");
1931 imcr_pic_to_apic();
1933 #endif
1937 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1938 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1940 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1941 * APIC is disabled.
1943 void disconnect_bsp_APIC(int virt_wire_setup)
1945 unsigned int value;
1947 #ifdef CONFIG_X86_32
1948 if (pic_mode) {
1950 * Put the board back into PIC mode (has an effect only on
1951 * certain older boards). Note that APIC interrupts, including
1952 * IPIs, won't work beyond this point! The only exception are
1953 * INIT IPIs.
1955 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1956 "entering PIC mode.\n");
1957 imcr_apic_to_pic();
1958 return;
1960 #endif
1962 /* Go back to Virtual Wire compatibility mode */
1964 /* For the spurious interrupt use vector F, and enable it */
1965 value = apic_read(APIC_SPIV);
1966 value &= ~APIC_VECTOR_MASK;
1967 value |= APIC_SPIV_APIC_ENABLED;
1968 value |= 0xf;
1969 apic_write(APIC_SPIV, value);
1971 if (!virt_wire_setup) {
1973 * For LVT0 make it edge triggered, active high,
1974 * external and enabled
1976 value = apic_read(APIC_LVT0);
1977 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1978 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1979 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1980 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1981 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1982 apic_write(APIC_LVT0, value);
1983 } else {
1984 /* Disable LVT0 */
1985 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1989 * For LVT1 make it edge triggered, active high,
1990 * nmi and enabled
1992 value = apic_read(APIC_LVT1);
1993 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1994 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1995 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1996 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1997 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1998 apic_write(APIC_LVT1, value);
2001 int generic_processor_info(int apicid, int version)
2003 int cpu, max = nr_cpu_ids;
2004 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2005 phys_cpu_present_map);
2008 * boot_cpu_physical_apicid is designed to have the apicid
2009 * returned by read_apic_id(), i.e, the apicid of the
2010 * currently booting-up processor. However, on some platforms,
2011 * it is temporarily modified by the apicid reported as BSP
2012 * through MP table. Concretely:
2014 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2015 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2017 * This function is executed with the modified
2018 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2019 * parameter doesn't work to disable APs on kdump 2nd kernel.
2021 * Since fixing handling of boot_cpu_physical_apicid requires
2022 * another discussion and tests on each platform, we leave it
2023 * for now and here we use read_apic_id() directly in this
2024 * function, generic_processor_info().
2026 if (disabled_cpu_apicid != BAD_APICID &&
2027 disabled_cpu_apicid != read_apic_id() &&
2028 disabled_cpu_apicid == apicid) {
2029 int thiscpu = num_processors + disabled_cpus;
2031 pr_warning("APIC: Disabling requested cpu."
2032 " Processor %d/0x%x ignored.\n",
2033 thiscpu, apicid);
2035 disabled_cpus++;
2036 return -ENODEV;
2040 * If boot cpu has not been detected yet, then only allow upto
2041 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2043 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2044 apicid != boot_cpu_physical_apicid) {
2045 int thiscpu = max + disabled_cpus - 1;
2047 pr_warning(
2048 "ACPI: NR_CPUS/possible_cpus limit of %i almost"
2049 " reached. Keeping one slot for boot cpu."
2050 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2052 disabled_cpus++;
2053 return -ENODEV;
2056 if (num_processors >= nr_cpu_ids) {
2057 int thiscpu = max + disabled_cpus;
2059 pr_warning(
2060 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
2061 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2063 disabled_cpus++;
2064 return -EINVAL;
2067 num_processors++;
2068 if (apicid == boot_cpu_physical_apicid) {
2070 * x86_bios_cpu_apicid is required to have processors listed
2071 * in same order as logical cpu numbers. Hence the first
2072 * entry is BSP, and so on.
2073 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2074 * for BSP.
2076 cpu = 0;
2077 } else
2078 cpu = cpumask_next_zero(-1, cpu_present_mask);
2081 * This can happen on physical hotplug. The sanity check at boot time
2082 * is done from native_smp_prepare_cpus() after num_possible_cpus() is
2083 * established.
2085 if (topology_update_package_map(apicid, cpu) < 0) {
2086 int thiscpu = max + disabled_cpus;
2088 pr_warning("ACPI: Package limit reached. Processor %d/0x%x ignored.\n",
2089 thiscpu, apicid);
2090 disabled_cpus++;
2091 return -ENOSPC;
2095 * Validate version
2097 if (version == 0x0) {
2098 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2099 cpu, apicid);
2100 version = 0x10;
2102 apic_version[apicid] = version;
2104 if (version != apic_version[boot_cpu_physical_apicid]) {
2105 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2106 apic_version[boot_cpu_physical_apicid], cpu, version);
2109 physid_set(apicid, phys_cpu_present_map);
2110 if (apicid > max_physical_apicid)
2111 max_physical_apicid = apicid;
2113 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2114 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2115 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2116 #endif
2117 #ifdef CONFIG_X86_32
2118 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2119 apic->x86_32_early_logical_apicid(cpu);
2120 #endif
2121 set_cpu_possible(cpu, true);
2122 set_cpu_present(cpu, true);
2124 return cpu;
2127 int hard_smp_processor_id(void)
2129 return read_apic_id();
2132 void default_init_apic_ldr(void)
2134 unsigned long val;
2136 apic_write(APIC_DFR, APIC_DFR_VALUE);
2137 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2138 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2139 apic_write(APIC_LDR, val);
2142 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2143 const struct cpumask *andmask,
2144 unsigned int *apicid)
2146 unsigned int cpu;
2148 for_each_cpu_and(cpu, cpumask, andmask) {
2149 if (cpumask_test_cpu(cpu, cpu_online_mask))
2150 break;
2153 if (likely(cpu < nr_cpu_ids)) {
2154 *apicid = per_cpu(x86_cpu_to_apicid, cpu);
2155 return 0;
2158 return -EINVAL;
2162 * Override the generic EOI implementation with an optimized version.
2163 * Only called during early boot when only one CPU is active and with
2164 * interrupts disabled, so we know this does not race with actual APIC driver
2165 * use.
2167 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2169 struct apic **drv;
2171 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2172 /* Should happen once for each apic */
2173 WARN_ON((*drv)->eoi_write == eoi_write);
2174 (*drv)->eoi_write = eoi_write;
2178 static void __init apic_bsp_up_setup(void)
2180 #ifdef CONFIG_X86_64
2181 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2182 #else
2184 * Hack: In case of kdump, after a crash, kernel might be booting
2185 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2186 * might be zero if read from MP tables. Get it from LAPIC.
2188 # ifdef CONFIG_CRASH_DUMP
2189 boot_cpu_physical_apicid = read_apic_id();
2190 # endif
2191 #endif
2192 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2196 * apic_bsp_setup - Setup function for local apic and io-apic
2197 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2199 * Returns:
2200 * apic_id of BSP APIC
2202 int __init apic_bsp_setup(bool upmode)
2204 int id;
2206 connect_bsp_APIC();
2207 if (upmode)
2208 apic_bsp_up_setup();
2209 setup_local_APIC();
2211 if (x2apic_mode)
2212 id = apic_read(APIC_LDR);
2213 else
2214 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2216 enable_IO_APIC();
2217 end_local_APIC_setup();
2218 irq_remap_enable_fault_handling();
2219 setup_IO_APIC();
2220 /* Setup local timer */
2221 x86_init.timers.setup_percpu_clockev();
2222 return id;
2226 * This initializes the IO-APIC and APIC hardware if this is
2227 * a UP kernel.
2229 int __init APIC_init_uniprocessor(void)
2231 if (disable_apic) {
2232 pr_info("Apic disabled\n");
2233 return -1;
2235 #ifdef CONFIG_X86_64
2236 if (!cpu_has_apic) {
2237 disable_apic = 1;
2238 pr_info("Apic disabled by BIOS\n");
2239 return -1;
2241 #else
2242 if (!smp_found_config && !cpu_has_apic)
2243 return -1;
2246 * Complain if the BIOS pretends there is one.
2248 if (!cpu_has_apic &&
2249 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
2250 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2251 boot_cpu_physical_apicid);
2252 return -1;
2254 #endif
2256 if (!smp_found_config)
2257 disable_ioapic_support();
2259 default_setup_apic_routing();
2260 apic_bsp_setup(true);
2261 return 0;
2264 #ifdef CONFIG_UP_LATE_INIT
2265 void __init up_late_init(void)
2267 APIC_init_uniprocessor();
2269 #endif
2272 * Power management
2274 #ifdef CONFIG_PM
2276 static struct {
2278 * 'active' is true if the local APIC was enabled by us and
2279 * not the BIOS; this signifies that we are also responsible
2280 * for disabling it before entering apm/acpi suspend
2282 int active;
2283 /* r/w apic fields */
2284 unsigned int apic_id;
2285 unsigned int apic_taskpri;
2286 unsigned int apic_ldr;
2287 unsigned int apic_dfr;
2288 unsigned int apic_spiv;
2289 unsigned int apic_lvtt;
2290 unsigned int apic_lvtpc;
2291 unsigned int apic_lvt0;
2292 unsigned int apic_lvt1;
2293 unsigned int apic_lvterr;
2294 unsigned int apic_tmict;
2295 unsigned int apic_tdcr;
2296 unsigned int apic_thmr;
2297 unsigned int apic_cmci;
2298 } apic_pm_state;
2300 static int lapic_suspend(void)
2302 unsigned long flags;
2303 int maxlvt;
2305 if (!apic_pm_state.active)
2306 return 0;
2308 maxlvt = lapic_get_maxlvt();
2310 apic_pm_state.apic_id = apic_read(APIC_ID);
2311 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2312 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2313 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2314 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2315 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2316 if (maxlvt >= 4)
2317 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2318 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2319 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2320 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2321 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2322 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2323 #ifdef CONFIG_X86_THERMAL_VECTOR
2324 if (maxlvt >= 5)
2325 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2326 #endif
2327 #ifdef CONFIG_X86_MCE_INTEL
2328 if (maxlvt >= 6)
2329 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2330 #endif
2332 local_irq_save(flags);
2333 disable_local_APIC();
2335 irq_remapping_disable();
2337 local_irq_restore(flags);
2338 return 0;
2341 static void lapic_resume(void)
2343 unsigned int l, h;
2344 unsigned long flags;
2345 int maxlvt;
2347 if (!apic_pm_state.active)
2348 return;
2350 local_irq_save(flags);
2353 * IO-APIC and PIC have their own resume routines.
2354 * We just mask them here to make sure the interrupt
2355 * subsystem is completely quiet while we enable x2apic
2356 * and interrupt-remapping.
2358 mask_ioapic_entries();
2359 legacy_pic->mask_all();
2361 if (x2apic_mode) {
2362 __x2apic_enable();
2363 } else {
2365 * Make sure the APICBASE points to the right address
2367 * FIXME! This will be wrong if we ever support suspend on
2368 * SMP! We'll need to do this as part of the CPU restore!
2370 if (boot_cpu_data.x86 >= 6) {
2371 rdmsr(MSR_IA32_APICBASE, l, h);
2372 l &= ~MSR_IA32_APICBASE_BASE;
2373 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2374 wrmsr(MSR_IA32_APICBASE, l, h);
2378 maxlvt = lapic_get_maxlvt();
2379 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2380 apic_write(APIC_ID, apic_pm_state.apic_id);
2381 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2382 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2383 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2384 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2385 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2386 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2387 #ifdef CONFIG_X86_THERMAL_VECTOR
2388 if (maxlvt >= 5)
2389 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2390 #endif
2391 #ifdef CONFIG_X86_MCE_INTEL
2392 if (maxlvt >= 6)
2393 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2394 #endif
2395 if (maxlvt >= 4)
2396 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2397 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2398 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2399 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2400 apic_write(APIC_ESR, 0);
2401 apic_read(APIC_ESR);
2402 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2403 apic_write(APIC_ESR, 0);
2404 apic_read(APIC_ESR);
2406 irq_remapping_reenable(x2apic_mode);
2408 local_irq_restore(flags);
2412 * This device has no shutdown method - fully functioning local APICs
2413 * are needed on every CPU up until machine_halt/restart/poweroff.
2416 static struct syscore_ops lapic_syscore_ops = {
2417 .resume = lapic_resume,
2418 .suspend = lapic_suspend,
2421 static void apic_pm_activate(void)
2423 apic_pm_state.active = 1;
2426 static int __init init_lapic_sysfs(void)
2428 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2429 if (cpu_has_apic)
2430 register_syscore_ops(&lapic_syscore_ops);
2432 return 0;
2435 /* local apic needs to resume before other devices access its registers. */
2436 core_initcall(init_lapic_sysfs);
2438 #else /* CONFIG_PM */
2440 static void apic_pm_activate(void) { }
2442 #endif /* CONFIG_PM */
2444 #ifdef CONFIG_X86_64
2446 static int multi_checked;
2447 static int multi;
2449 static int set_multi(const struct dmi_system_id *d)
2451 if (multi)
2452 return 0;
2453 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2454 multi = 1;
2455 return 0;
2458 static const struct dmi_system_id multi_dmi_table[] = {
2460 .callback = set_multi,
2461 .ident = "IBM System Summit2",
2462 .matches = {
2463 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2464 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2470 static void dmi_check_multi(void)
2472 if (multi_checked)
2473 return;
2475 dmi_check_system(multi_dmi_table);
2476 multi_checked = 1;
2480 * apic_is_clustered_box() -- Check if we can expect good TSC
2482 * Thus far, the major user of this is IBM's Summit2 series:
2483 * Clustered boxes may have unsynced TSC problems if they are
2484 * multi-chassis.
2485 * Use DMI to check them
2487 int apic_is_clustered_box(void)
2489 dmi_check_multi();
2490 return multi;
2492 #endif
2495 * APIC command line parameters
2497 static int __init setup_disableapic(char *arg)
2499 disable_apic = 1;
2500 setup_clear_cpu_cap(X86_FEATURE_APIC);
2501 return 0;
2503 early_param("disableapic", setup_disableapic);
2505 /* same as disableapic, for compatibility */
2506 static int __init setup_nolapic(char *arg)
2508 return setup_disableapic(arg);
2510 early_param("nolapic", setup_nolapic);
2512 static int __init parse_lapic_timer_c2_ok(char *arg)
2514 local_apic_timer_c2_ok = 1;
2515 return 0;
2517 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2519 static int __init parse_disable_apic_timer(char *arg)
2521 disable_apic_timer = 1;
2522 return 0;
2524 early_param("noapictimer", parse_disable_apic_timer);
2526 static int __init parse_nolapic_timer(char *arg)
2528 disable_apic_timer = 1;
2529 return 0;
2531 early_param("nolapic_timer", parse_nolapic_timer);
2533 static int __init apic_set_verbosity(char *arg)
2535 if (!arg) {
2536 #ifdef CONFIG_X86_64
2537 skip_ioapic_setup = 0;
2538 return 0;
2539 #endif
2540 return -EINVAL;
2543 if (strcmp("debug", arg) == 0)
2544 apic_verbosity = APIC_DEBUG;
2545 else if (strcmp("verbose", arg) == 0)
2546 apic_verbosity = APIC_VERBOSE;
2547 else {
2548 pr_warning("APIC Verbosity level %s not recognised"
2549 " use apic=verbose or apic=debug\n", arg);
2550 return -EINVAL;
2553 return 0;
2555 early_param("apic", apic_set_verbosity);
2557 static int __init lapic_insert_resource(void)
2559 if (!apic_phys)
2560 return -1;
2562 /* Put local APIC into the resource map. */
2563 lapic_resource.start = apic_phys;
2564 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2565 insert_resource(&iomem_resource, &lapic_resource);
2567 return 0;
2571 * need call insert after e820_reserve_resources()
2572 * that is using request_resource
2574 late_initcall(lapic_insert_resource);
2576 static int __init apic_set_disabled_cpu_apicid(char *arg)
2578 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2579 return -EINVAL;
2581 return 0;
2583 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2585 static int __init apic_set_extnmi(char *arg)
2587 if (!arg)
2588 return -EINVAL;
2590 if (!strncmp("all", arg, 3))
2591 apic_extnmi = APIC_EXTNMI_ALL;
2592 else if (!strncmp("none", arg, 4))
2593 apic_extnmi = APIC_EXTNMI_NONE;
2594 else if (!strncmp("bsp", arg, 3))
2595 apic_extnmi = APIC_EXTNMI_BSP;
2596 else {
2597 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2598 return -EINVAL;
2601 return 0;
2603 early_param("apic_extnmi", apic_set_extnmi);