1 #include <linux/linkage.h>
2 #include <linux/errno.h>
3 #include <linux/signal.h>
4 #include <linux/sched.h>
5 #include <linux/ioport.h>
6 #include <linux/interrupt.h>
7 #include <linux/timex.h>
8 #include <linux/random.h>
9 #include <linux/init.h>
10 #include <linux/kernel_stat.h>
11 #include <linux/syscore_ops.h>
12 #include <linux/bitops.h>
13 #include <linux/acpi.h>
15 #include <linux/delay.h>
17 #include <linux/atomic.h>
18 #include <asm/timer.h>
19 #include <asm/hw_irq.h>
20 #include <asm/pgtable.h>
23 #include <asm/i8259.h>
26 * This is the 'legacy' 8259A Programmable Interrupt Controller,
27 * present in the majority of PC/AT boxes.
28 * plus some generic x86 specific things if generic specifics makes
31 static void init_8259A(int auto_eoi
);
33 static int i8259A_auto_eoi
;
34 DEFINE_RAW_SPINLOCK(i8259A_lock
);
37 * 8259A PIC functions to handle ISA devices:
41 * This contains the irq mask for both 8259A irq controllers,
43 unsigned int cached_irq_mask
= 0xffff;
46 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
47 * boards the timer interrupt is not really connected to any IO-APIC pin,
48 * it's fed to the master 8259A's IR0 line only.
50 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
51 * this 'mixed mode' IRQ handling costs nothing because it's only used
54 unsigned long io_apic_irqs
;
56 static void mask_8259A_irq(unsigned int irq
)
58 unsigned int mask
= 1 << irq
;
61 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
62 cached_irq_mask
|= mask
;
64 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
66 outb(cached_master_mask
, PIC_MASTER_IMR
);
67 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
70 static void disable_8259A_irq(struct irq_data
*data
)
72 mask_8259A_irq(data
->irq
);
75 static void unmask_8259A_irq(unsigned int irq
)
77 unsigned int mask
= ~(1 << irq
);
80 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
81 cached_irq_mask
&= mask
;
83 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
85 outb(cached_master_mask
, PIC_MASTER_IMR
);
86 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
89 static void enable_8259A_irq(struct irq_data
*data
)
91 unmask_8259A_irq(data
->irq
);
94 static int i8259A_irq_pending(unsigned int irq
)
96 unsigned int mask
= 1<<irq
;
100 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
102 ret
= inb(PIC_MASTER_CMD
) & mask
;
104 ret
= inb(PIC_SLAVE_CMD
) & (mask
>> 8);
105 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
110 static void make_8259A_irq(unsigned int irq
)
112 disable_irq_nosync(irq
);
113 io_apic_irqs
&= ~(1<<irq
);
114 irq_set_chip_and_handler(irq
, &i8259A_chip
, handle_level_irq
);
119 * This function assumes to be called rarely. Switching between
120 * 8259A registers is slow.
121 * This has to be protected by the irq controller spinlock
122 * before being called.
124 static inline int i8259A_irq_real(unsigned int irq
)
127 int irqmask
= 1<<irq
;
130 outb(0x0B, PIC_MASTER_CMD
); /* ISR register */
131 value
= inb(PIC_MASTER_CMD
) & irqmask
;
132 outb(0x0A, PIC_MASTER_CMD
); /* back to the IRR register */
135 outb(0x0B, PIC_SLAVE_CMD
); /* ISR register */
136 value
= inb(PIC_SLAVE_CMD
) & (irqmask
>> 8);
137 outb(0x0A, PIC_SLAVE_CMD
); /* back to the IRR register */
142 * Careful! The 8259A is a fragile beast, it pretty
143 * much _has_ to be done exactly like this (mask it
144 * first, _then_ send the EOI, and the order of EOI
145 * to the two 8259s is important!
147 static void mask_and_ack_8259A(struct irq_data
*data
)
149 unsigned int irq
= data
->irq
;
150 unsigned int irqmask
= 1 << irq
;
153 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
155 * Lightweight spurious IRQ detection. We do not want
156 * to overdo spurious IRQ handling - it's usually a sign
157 * of hardware problems, so we only do the checks we can
158 * do without slowing down good hardware unnecessarily.
160 * Note that IRQ7 and IRQ15 (the two spurious IRQs
161 * usually resulting from the 8259A-1|2 PICs) occur
162 * even if the IRQ is masked in the 8259A. Thus we
163 * can check spurious 8259A IRQs without doing the
164 * quite slow i8259A_irq_real() call for every IRQ.
165 * This does not cover 100% of spurious interrupts,
166 * but should be enough to warn the user that there
167 * is something bad going on ...
169 if (cached_irq_mask
& irqmask
)
170 goto spurious_8259A_irq
;
171 cached_irq_mask
|= irqmask
;
175 inb(PIC_SLAVE_IMR
); /* DUMMY - (do we need this?) */
176 outb(cached_slave_mask
, PIC_SLAVE_IMR
);
177 /* 'Specific EOI' to slave */
178 outb(0x60+(irq
&7), PIC_SLAVE_CMD
);
179 /* 'Specific EOI' to master-IRQ2 */
180 outb(0x60+PIC_CASCADE_IR
, PIC_MASTER_CMD
);
182 inb(PIC_MASTER_IMR
); /* DUMMY - (do we need this?) */
183 outb(cached_master_mask
, PIC_MASTER_IMR
);
184 outb(0x60+irq
, PIC_MASTER_CMD
); /* 'Specific EOI to master */
186 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
191 * this is the slow path - should happen rarely.
193 if (i8259A_irq_real(irq
))
195 * oops, the IRQ _is_ in service according to the
196 * 8259A - not spurious, go handle it.
198 goto handle_real_irq
;
201 static int spurious_irq_mask
;
203 * At this point we can be sure the IRQ is spurious,
204 * lets ACK and report it. [once per IRQ]
206 if (!(spurious_irq_mask
& irqmask
)) {
208 "spurious 8259A interrupt: IRQ%d.\n", irq
);
209 spurious_irq_mask
|= irqmask
;
211 atomic_inc(&irq_err_count
);
213 * Theoretically we do not have to handle this IRQ,
214 * but in Linux this does not cause problems and is
217 goto handle_real_irq
;
221 struct irq_chip i8259A_chip
= {
223 .irq_mask
= disable_8259A_irq
,
224 .irq_disable
= disable_8259A_irq
,
225 .irq_unmask
= enable_8259A_irq
,
226 .irq_mask_ack
= mask_and_ack_8259A
,
229 static char irq_trigger
[2];
231 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
233 static void restore_ELCR(char *trigger
)
235 outb(trigger
[0], 0x4d0);
236 outb(trigger
[1], 0x4d1);
239 static void save_ELCR(char *trigger
)
241 /* IRQ 0,1,2,8,13 are marked as reserved */
242 trigger
[0] = inb(0x4d0) & 0xF8;
243 trigger
[1] = inb(0x4d1) & 0xDE;
246 static void i8259A_resume(void)
248 init_8259A(i8259A_auto_eoi
);
249 restore_ELCR(irq_trigger
);
252 static int i8259A_suspend(void)
254 save_ELCR(irq_trigger
);
258 static void i8259A_shutdown(void)
260 /* Put the i8259A into a quiescent state that
261 * the kernel initialization code can get it
264 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
265 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
268 static struct syscore_ops i8259_syscore_ops
= {
269 .suspend
= i8259A_suspend
,
270 .resume
= i8259A_resume
,
271 .shutdown
= i8259A_shutdown
,
274 static void mask_8259A(void)
278 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
280 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
281 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
283 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
286 static void unmask_8259A(void)
290 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
292 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
293 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
295 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
298 static int probe_8259A(void)
301 unsigned char probe_val
= ~(1 << PIC_CASCADE_IR
);
302 unsigned char new_val
;
304 * Check to see if we have a PIC.
305 * Mask all except the cascade and read
306 * back the value we just wrote. If we don't
307 * have a PIC, we will read 0xff as opposed to the
310 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
312 outb(0xff, PIC_SLAVE_IMR
); /* mask all of 8259A-2 */
313 outb(probe_val
, PIC_MASTER_IMR
);
314 new_val
= inb(PIC_MASTER_IMR
);
315 if (new_val
!= probe_val
) {
316 printk(KERN_INFO
"Using NULL legacy PIC\n");
317 legacy_pic
= &null_legacy_pic
;
320 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
321 return nr_legacy_irqs();
324 static void init_8259A(int auto_eoi
)
328 i8259A_auto_eoi
= auto_eoi
;
330 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
332 outb(0xff, PIC_MASTER_IMR
); /* mask all of 8259A-1 */
335 * outb_pic - this has to work on a wide range of PC hardware.
337 outb_pic(0x11, PIC_MASTER_CMD
); /* ICW1: select 8259A-1 init */
339 /* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
340 outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR
);
342 /* 8259A-1 (the master) has a slave on IR2 */
343 outb_pic(1U << PIC_CASCADE_IR
, PIC_MASTER_IMR
);
345 if (auto_eoi
) /* master does Auto EOI */
346 outb_pic(MASTER_ICW4_DEFAULT
| PIC_ICW4_AEOI
, PIC_MASTER_IMR
);
347 else /* master expects normal EOI */
348 outb_pic(MASTER_ICW4_DEFAULT
, PIC_MASTER_IMR
);
350 outb_pic(0x11, PIC_SLAVE_CMD
); /* ICW1: select 8259A-2 init */
352 /* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
353 outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR
);
354 /* 8259A-2 is a slave on master's IR2 */
355 outb_pic(PIC_CASCADE_IR
, PIC_SLAVE_IMR
);
356 /* (slave's support for AEOI in flat mode is to be investigated) */
357 outb_pic(SLAVE_ICW4_DEFAULT
, PIC_SLAVE_IMR
);
361 * In AEOI mode we just have to mask the interrupt
364 i8259A_chip
.irq_mask_ack
= disable_8259A_irq
;
366 i8259A_chip
.irq_mask_ack
= mask_and_ack_8259A
;
368 udelay(100); /* wait for 8259A to initialize */
370 outb(cached_master_mask
, PIC_MASTER_IMR
); /* restore master IRQ mask */
371 outb(cached_slave_mask
, PIC_SLAVE_IMR
); /* restore slave IRQ mask */
373 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
377 * make i8259 a driver so that we can select pic functions at run time. the goal
378 * is to make x86 binary compatible among pc compatible and non-pc compatible
379 * platforms, such as x86 MID.
382 static void legacy_pic_noop(void) { };
383 static void legacy_pic_uint_noop(unsigned int unused
) { };
384 static void legacy_pic_int_noop(int unused
) { };
385 static int legacy_pic_irq_pending_noop(unsigned int irq
)
389 static int legacy_pic_probe(void)
394 struct legacy_pic null_legacy_pic
= {
396 .chip
= &dummy_irq_chip
,
397 .mask
= legacy_pic_uint_noop
,
398 .unmask
= legacy_pic_uint_noop
,
399 .mask_all
= legacy_pic_noop
,
400 .restore_mask
= legacy_pic_noop
,
401 .init
= legacy_pic_int_noop
,
402 .probe
= legacy_pic_probe
,
403 .irq_pending
= legacy_pic_irq_pending_noop
,
404 .make_irq
= legacy_pic_uint_noop
,
407 struct legacy_pic default_legacy_pic
= {
408 .nr_legacy_irqs
= NR_IRQS_LEGACY
,
409 .chip
= &i8259A_chip
,
410 .mask
= mask_8259A_irq
,
411 .unmask
= unmask_8259A_irq
,
412 .mask_all
= mask_8259A
,
413 .restore_mask
= unmask_8259A
,
415 .probe
= probe_8259A
,
416 .irq_pending
= i8259A_irq_pending
,
417 .make_irq
= make_8259A_irq
,
420 struct legacy_pic
*legacy_pic
= &default_legacy_pic
;
422 static int __init
i8259A_init_ops(void)
424 if (legacy_pic
== &default_legacy_pic
)
425 register_syscore_ops(&i8259_syscore_ops
);
430 device_initcall(i8259A_init_ops
);