2 * Copyright (C) 1991, 1992 Linus Torvalds
3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
4 * Copyright (C) 2011 Don Zickus Red Hat, Inc.
6 * Pentium III FXSR, SSE support
7 * Gareth Hughes <gareth@valinux.com>, May 2000
11 * Handle hardware traps and faults.
13 #include <linux/spinlock.h>
14 #include <linux/kprobes.h>
15 #include <linux/kdebug.h>
16 #include <linux/nmi.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/hardirq.h>
20 #include <linux/slab.h>
21 #include <linux/export.h>
23 #if defined(CONFIG_EDAC)
24 #include <linux/edac.h>
27 #include <linux/atomic.h>
28 #include <asm/traps.h>
29 #include <asm/mach_traps.h>
31 #include <asm/x86_init.h>
32 #include <asm/reboot.h>
33 #include <asm/cache.h>
35 #define CREATE_TRACE_POINTS
36 #include <trace/events/nmi.h>
40 struct list_head head
;
43 static struct nmi_desc nmi_desc
[NMI_MAX
] =
46 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[0].lock
),
47 .head
= LIST_HEAD_INIT(nmi_desc
[0].head
),
50 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[1].lock
),
51 .head
= LIST_HEAD_INIT(nmi_desc
[1].head
),
54 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[2].lock
),
55 .head
= LIST_HEAD_INIT(nmi_desc
[2].head
),
58 .lock
= __SPIN_LOCK_UNLOCKED(&nmi_desc
[3].lock
),
59 .head
= LIST_HEAD_INIT(nmi_desc
[3].head
),
67 unsigned int external
;
71 static DEFINE_PER_CPU(struct nmi_stats
, nmi_stats
);
73 static int ignore_nmis __read_mostly
;
75 int unknown_nmi_panic
;
77 * Prevent NMI reason port (0x61) being accessed simultaneously, can
78 * only be used in NMI handler.
80 static DEFINE_RAW_SPINLOCK(nmi_reason_lock
);
82 static int __init
setup_unknown_nmi_panic(char *str
)
84 unknown_nmi_panic
= 1;
87 __setup("unknown_nmi_panic", setup_unknown_nmi_panic
);
89 #define nmi_to_desc(type) (&nmi_desc[type])
91 static u64 nmi_longest_ns
= 1 * NSEC_PER_MSEC
;
93 static int __init
nmi_warning_debugfs(void)
95 debugfs_create_u64("nmi_longest_ns", 0644,
96 arch_debugfs_dir
, &nmi_longest_ns
);
99 fs_initcall(nmi_warning_debugfs
);
101 static void nmi_max_handler(struct irq_work
*w
)
103 struct nmiaction
*a
= container_of(w
, struct nmiaction
, irq_work
);
104 int remainder_ns
, decimal_msecs
;
105 u64 whole_msecs
= ACCESS_ONCE(a
->max_duration
);
107 remainder_ns
= do_div(whole_msecs
, (1000 * 1000));
108 decimal_msecs
= remainder_ns
/ 1000;
110 printk_ratelimited(KERN_INFO
111 "INFO: NMI handler (%ps) took too long to run: %lld.%03d msecs\n",
112 a
->handler
, whole_msecs
, decimal_msecs
);
115 static int nmi_handle(unsigned int type
, struct pt_regs
*regs
)
117 struct nmi_desc
*desc
= nmi_to_desc(type
);
124 * NMIs are edge-triggered, which means if you have enough
125 * of them concurrently, you can lose some because only one
126 * can be latched at any given time. Walk the whole list
127 * to handle those situations.
129 list_for_each_entry_rcu(a
, &desc
->head
, list
) {
133 delta
= sched_clock();
134 thishandled
= a
->handler(type
, regs
);
135 handled
+= thishandled
;
136 delta
= sched_clock() - delta
;
137 trace_nmi_handler(a
->handler
, (int)delta
, thishandled
);
139 if (delta
< nmi_longest_ns
|| delta
< a
->max_duration
)
142 a
->max_duration
= delta
;
143 irq_work_queue(&a
->irq_work
);
148 /* return total number of NMI events handled */
151 NOKPROBE_SYMBOL(nmi_handle
);
153 int __register_nmi_handler(unsigned int type
, struct nmiaction
*action
)
155 struct nmi_desc
*desc
= nmi_to_desc(type
);
158 if (!action
->handler
)
161 init_irq_work(&action
->irq_work
, nmi_max_handler
);
163 spin_lock_irqsave(&desc
->lock
, flags
);
166 * most handlers of type NMI_UNKNOWN never return because
167 * they just assume the NMI is theirs. Just a sanity check
168 * to manage expectations
170 WARN_ON_ONCE(type
== NMI_UNKNOWN
&& !list_empty(&desc
->head
));
171 WARN_ON_ONCE(type
== NMI_SERR
&& !list_empty(&desc
->head
));
172 WARN_ON_ONCE(type
== NMI_IO_CHECK
&& !list_empty(&desc
->head
));
175 * some handlers need to be executed first otherwise a fake
176 * event confuses some handlers (kdump uses this flag)
178 if (action
->flags
& NMI_FLAG_FIRST
)
179 list_add_rcu(&action
->list
, &desc
->head
);
181 list_add_tail_rcu(&action
->list
, &desc
->head
);
183 spin_unlock_irqrestore(&desc
->lock
, flags
);
186 EXPORT_SYMBOL(__register_nmi_handler
);
188 void unregister_nmi_handler(unsigned int type
, const char *name
)
190 struct nmi_desc
*desc
= nmi_to_desc(type
);
194 spin_lock_irqsave(&desc
->lock
, flags
);
196 list_for_each_entry_rcu(n
, &desc
->head
, list
) {
198 * the name passed in to describe the nmi handler
199 * is used as the lookup key
201 if (!strcmp(n
->name
, name
)) {
203 "Trying to free NMI (%s) from NMI context!\n", n
->name
);
204 list_del_rcu(&n
->list
);
209 spin_unlock_irqrestore(&desc
->lock
, flags
);
212 EXPORT_SYMBOL_GPL(unregister_nmi_handler
);
215 pci_serr_error(unsigned char reason
, struct pt_regs
*regs
)
217 /* check to see if anyone registered against these types of errors */
218 if (nmi_handle(NMI_SERR
, regs
))
221 pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
222 reason
, smp_processor_id());
225 * On some machines, PCI SERR line is used to report memory
226 * errors. EDAC makes use of it.
228 #if defined(CONFIG_EDAC)
229 if (edac_handler_set()) {
230 edac_atomic_assert_error();
235 if (panic_on_unrecovered_nmi
)
236 nmi_panic(regs
, "NMI: Not continuing");
238 pr_emerg("Dazed and confused, but trying to continue\n");
240 /* Clear and disable the PCI SERR error line. */
241 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_SERR
;
242 outb(reason
, NMI_REASON_PORT
);
244 NOKPROBE_SYMBOL(pci_serr_error
);
247 io_check_error(unsigned char reason
, struct pt_regs
*regs
)
251 /* check to see if anyone registered against these types of errors */
252 if (nmi_handle(NMI_IO_CHECK
, regs
))
256 "NMI: IOCK error (debug interrupt?) for reason %02x on CPU %d.\n",
257 reason
, smp_processor_id());
260 if (panic_on_io_nmi
) {
261 nmi_panic(regs
, "NMI IOCK error: Not continuing");
264 * If we end up here, it means we have received an NMI while
265 * processing panic(). Simply return without delaying and
271 /* Re-enable the IOCK line, wait for a few seconds */
272 reason
= (reason
& NMI_REASON_CLEAR_MASK
) | NMI_REASON_CLEAR_IOCHK
;
273 outb(reason
, NMI_REASON_PORT
);
277 touch_nmi_watchdog();
281 reason
&= ~NMI_REASON_CLEAR_IOCHK
;
282 outb(reason
, NMI_REASON_PORT
);
284 NOKPROBE_SYMBOL(io_check_error
);
287 unknown_nmi_error(unsigned char reason
, struct pt_regs
*regs
)
292 * Use 'false' as back-to-back NMIs are dealt with one level up.
293 * Of course this makes having multiple 'unknown' handlers useless
294 * as only the first one is ever run (unless it can actually determine
295 * if it caused the NMI)
297 handled
= nmi_handle(NMI_UNKNOWN
, regs
);
299 __this_cpu_add(nmi_stats
.unknown
, handled
);
303 __this_cpu_add(nmi_stats
.unknown
, 1);
305 pr_emerg("Uhhuh. NMI received for unknown reason %02x on CPU %d.\n",
306 reason
, smp_processor_id());
308 pr_emerg("Do you have a strange power saving mode enabled?\n");
309 if (unknown_nmi_panic
|| panic_on_unrecovered_nmi
)
310 nmi_panic(regs
, "NMI: Not continuing");
312 pr_emerg("Dazed and confused, but trying to continue\n");
314 NOKPROBE_SYMBOL(unknown_nmi_error
);
316 static DEFINE_PER_CPU(bool, swallow_nmi
);
317 static DEFINE_PER_CPU(unsigned long, last_nmi_rip
);
319 static void default_do_nmi(struct pt_regs
*regs
)
321 unsigned char reason
= 0;
326 * CPU-specific NMI must be processed before non-CPU-specific
327 * NMI, otherwise we may lose it, because the CPU-specific
328 * NMI can not be detected/processed on other CPUs.
332 * Back-to-back NMIs are interesting because they can either
333 * be two NMI or more than two NMIs (any thing over two is dropped
334 * due to NMI being edge-triggered). If this is the second half
335 * of the back-to-back NMI, assume we dropped things and process
336 * more handlers. Otherwise reset the 'swallow' NMI behaviour
338 if (regs
->ip
== __this_cpu_read(last_nmi_rip
))
341 __this_cpu_write(swallow_nmi
, false);
343 __this_cpu_write(last_nmi_rip
, regs
->ip
);
345 handled
= nmi_handle(NMI_LOCAL
, regs
);
346 __this_cpu_add(nmi_stats
.normal
, handled
);
349 * There are cases when a NMI handler handles multiple
350 * events in the current NMI. One of these events may
351 * be queued for in the next NMI. Because the event is
352 * already handled, the next NMI will result in an unknown
353 * NMI. Instead lets flag this for a potential NMI to
357 __this_cpu_write(swallow_nmi
, true);
362 * Non-CPU-specific NMI: NMI sources can be processed on any CPU.
364 * Another CPU may be processing panic routines while holding
365 * nmi_reason_lock. Check if the CPU issued the IPI for crash dumping,
366 * and if so, call its callback directly. If there is no CPU preparing
367 * crash dump, we simply loop here.
369 while (!raw_spin_trylock(&nmi_reason_lock
)) {
370 run_crash_ipi_callback(regs
);
374 reason
= x86_platform
.get_nmi_reason();
376 if (reason
& NMI_REASON_MASK
) {
377 if (reason
& NMI_REASON_SERR
)
378 pci_serr_error(reason
, regs
);
379 else if (reason
& NMI_REASON_IOCHK
)
380 io_check_error(reason
, regs
);
383 * Reassert NMI in case it became active
384 * meanwhile as it's edge-triggered:
388 __this_cpu_add(nmi_stats
.external
, 1);
389 raw_spin_unlock(&nmi_reason_lock
);
392 raw_spin_unlock(&nmi_reason_lock
);
395 * Only one NMI can be latched at a time. To handle
396 * this we may process multiple nmi handlers at once to
397 * cover the case where an NMI is dropped. The downside
398 * to this approach is we may process an NMI prematurely,
399 * while its real NMI is sitting latched. This will cause
400 * an unknown NMI on the next run of the NMI processing.
402 * We tried to flag that condition above, by setting the
403 * swallow_nmi flag when we process more than one event.
404 * This condition is also only present on the second half
405 * of a back-to-back NMI, so we flag that condition too.
407 * If both are true, we assume we already processed this
408 * NMI previously and we swallow it. Otherwise we reset
411 * There are scenarios where we may accidentally swallow
412 * a 'real' unknown NMI. For example, while processing
413 * a perf NMI another perf NMI comes in along with a
414 * 'real' unknown NMI. These two NMIs get combined into
415 * one (as descibed above). When the next NMI gets
416 * processed, it will be flagged by perf as handled, but
417 * noone will know that there was a 'real' unknown NMI sent
418 * also. As a result it gets swallowed. Or if the first
419 * perf NMI returns two events handled then the second
420 * NMI will get eaten by the logic below, again losing a
421 * 'real' unknown NMI. But this is the best we can do
424 if (b2b
&& __this_cpu_read(swallow_nmi
))
425 __this_cpu_add(nmi_stats
.swallow
, 1);
427 unknown_nmi_error(reason
, regs
);
429 NOKPROBE_SYMBOL(default_do_nmi
);
432 * NMIs can page fault or hit breakpoints which will cause it to lose
433 * its NMI context with the CPU when the breakpoint or page fault does an IRET.
435 * As a result, NMIs can nest if NMIs get unmasked due an IRET during
436 * NMI processing. On x86_64, the asm glue protects us from nested NMIs
437 * if the outer NMI came from kernel mode, but we can still nest if the
438 * outer NMI came from user mode.
440 * To handle these nested NMIs, we have three states:
446 * When no NMI is in progress, it is in the "not running" state.
447 * When an NMI comes in, it goes into the "executing" state.
448 * Normally, if another NMI is triggered, it does not interrupt
449 * the running NMI and the HW will simply latch it so that when
450 * the first NMI finishes, it will restart the second NMI.
451 * (Note, the latch is binary, thus multiple NMIs triggering,
452 * when one is running, are ignored. Only one NMI is restarted.)
454 * If an NMI executes an iret, another NMI can preempt it. We do not
455 * want to allow this new NMI to run, but we want to execute it when the
456 * first one finishes. We set the state to "latched", and the exit of
457 * the first NMI will perform a dec_return, if the result is zero
458 * (NOT_RUNNING), then it will simply exit the NMI handler. If not, the
459 * dec_return would have set the state to NMI_EXECUTING (what we want it
460 * to be when we are running). In this case, we simply jump back to
461 * rerun the NMI handler again, and restart the 'latched' NMI.
463 * No trap (breakpoint or page fault) should be hit before nmi_restart,
464 * thus there is no race between the first check of state for NOT_RUNNING
465 * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
468 * In case the NMI takes a page fault, we need to save off the CR2
469 * because the NMI could have preempted another page fault and corrupt
470 * the CR2 that is about to be read. As nested NMIs must be restarted
471 * and they can not take breakpoints or page faults, the update of the
472 * CR2 must be done before converting the nmi state back to NOT_RUNNING.
473 * Otherwise, there would be a race of another nested NMI coming in
474 * after setting state to NOT_RUNNING but before updating the nmi_cr2.
481 static DEFINE_PER_CPU(enum nmi_states
, nmi_state
);
482 static DEFINE_PER_CPU(unsigned long, nmi_cr2
);
486 * In x86_64, we need to handle breakpoint -> NMI -> breakpoint. Without
487 * some care, the inner breakpoint will clobber the outer breakpoint's
490 * If a breakpoint is being processed, and the debug stack is being
491 * used, if an NMI comes in and also hits a breakpoint, the stack
492 * pointer will be set to the same fixed address as the breakpoint that
493 * was interrupted, causing that stack to be corrupted. To handle this
494 * case, check if the stack that was interrupted is the debug stack, and
495 * if so, change the IDT so that new breakpoints will use the current
496 * stack and not switch to the fixed address. On return of the NMI,
497 * switch back to the original IDT.
499 static DEFINE_PER_CPU(int, update_debug_stack
);
502 dotraplinkage notrace
void
503 do_nmi(struct pt_regs
*regs
, long error_code
)
505 if (this_cpu_read(nmi_state
) != NMI_NOT_RUNNING
) {
506 this_cpu_write(nmi_state
, NMI_LATCHED
);
509 this_cpu_write(nmi_state
, NMI_EXECUTING
);
510 this_cpu_write(nmi_cr2
, read_cr2());
515 * If we interrupted a breakpoint, it is possible that
516 * the nmi handler will have breakpoints too. We need to
517 * change the IDT such that breakpoints that happen here
518 * continue to use the NMI stack.
520 if (unlikely(is_debug_stack(regs
->sp
))) {
521 debug_stack_set_zero();
522 this_cpu_write(update_debug_stack
, 1);
528 inc_irq_stat(__nmi_count
);
531 default_do_nmi(regs
);
536 if (unlikely(this_cpu_read(update_debug_stack
))) {
538 this_cpu_write(update_debug_stack
, 0);
542 if (unlikely(this_cpu_read(nmi_cr2
) != read_cr2()))
543 write_cr2(this_cpu_read(nmi_cr2
));
544 if (this_cpu_dec_return(nmi_state
))
547 NOKPROBE_SYMBOL(do_nmi
);
554 void restart_nmi(void)
559 /* reset the back-to-back NMI logic */
560 void local_touch_nmi(void)
562 __this_cpu_write(last_nmi_rip
, 0);
564 EXPORT_SYMBOL_GPL(local_touch_nmi
);