drivers/media/i2c/adv748x/adv748x.h

   1 /*
   2  * Driver for Analog Devices ADV748X video decoder and HDMI receiver
   3  *
   4  * Copyright (C) 2017 Renesas Electronics Corp.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Authors:
  12  *      Koji Matsuoka <koji.matsuoka.xm@renesas.com>
  13  *      Niklas Söderlund <niklas.soderlund@ragnatech.se>
  14  *      Kieran Bingham <kieran.bingham@ideasonboard.com>
  15  *
  16  * The ADV748x range of receivers have the following configurations:
  17  *
  18  *                  Analog   HDMI  MHL  4-Lane  1-Lane
  19  *                    In      In         CSI     CSI
  20  *       ADV7480               X    X     X
  21  *       ADV7481      X        X    X     X       X
  22  *       ADV7482      X        X          X       X
  23  */
  24
  25 #include <linux/i2c.h>
  26
  27 #ifndef _ADV748X_H_
  28 #define _ADV748X_H_
  29
  30 /* I2C slave addresses */
  31 #define ADV748X_I2C_IO                  0x70    /* IO Map */
  32 #define ADV748X_I2C_DPLL                0x26    /* DPLL Map */
  33 #define ADV748X_I2C_CP                  0x22    /* CP Map */
  34 #define ADV748X_I2C_HDMI                0x34    /* HDMI Map */
  35 #define ADV748X_I2C_EDID                0x36    /* EDID Map */
  36 #define ADV748X_I2C_REPEATER            0x32    /* HDMI RX Repeater Map */
  37 #define ADV748X_I2C_INFOFRAME           0x31    /* HDMI RX InfoFrame Map */
  38 #define ADV748X_I2C_CEC                 0x41    /* CEC Map */
  39 #define ADV748X_I2C_SDP                 0x79    /* SDP Map */
  40 #define ADV748X_I2C_TXB                 0x48    /* CSI-TXB Map */
  41 #define ADV748X_I2C_TXA                 0x4a    /* CSI-TXA Map */
  42
  43 enum adv748x_page {
  44         ADV748X_PAGE_IO,
  45         ADV748X_PAGE_DPLL,
  46         ADV748X_PAGE_CP,
  47         ADV748X_PAGE_HDMI,
  48         ADV748X_PAGE_EDID,
  49         ADV748X_PAGE_REPEATER,
  50         ADV748X_PAGE_INFOFRAME,
  51         ADV748X_PAGE_CEC,
  52         ADV748X_PAGE_SDP,
  53         ADV748X_PAGE_TXB,
  54         ADV748X_PAGE_TXA,
  55         ADV748X_PAGE_MAX,
  56
  57         /* Fake pages for register sequences */
  58         ADV748X_PAGE_WAIT,              /* Wait x msec */
  59         ADV748X_PAGE_EOR,               /* End Mark */
  60 };
  61
  62 /**
  63  * enum adv748x_ports - Device tree port number definitions
  64  *
  65  * The ADV748X ports define the mapping between subdevices
  66  * and the device tree specification
  67  */
  68 enum adv748x_ports {
  69         ADV748X_PORT_AIN0 = 0,
  70         ADV748X_PORT_AIN1 = 1,
  71         ADV748X_PORT_AIN2 = 2,
  72         ADV748X_PORT_AIN3 = 3,
  73         ADV748X_PORT_AIN4 = 4,
  74         ADV748X_PORT_AIN5 = 5,
  75         ADV748X_PORT_AIN6 = 6,
  76         ADV748X_PORT_AIN7 = 7,
  77         ADV748X_PORT_HDMI = 8,
  78         ADV748X_PORT_TTL = 9,
  79         ADV748X_PORT_TXA = 10,
  80         ADV748X_PORT_TXB = 11,
  81         ADV748X_PORT_MAX = 12,
  82 };
  83
  84 enum adv748x_csi2_pads {
  85         ADV748X_CSI2_SINK,
  86         ADV748X_CSI2_SOURCE,
  87         ADV748X_CSI2_NR_PADS,
  88 };
  89
  90 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
  91 #define ADV748X_CSI2_MAX_SUBDEVS 2
  92
  93 struct adv748x_csi2 {
  94         struct adv748x_state *state;
  95         struct v4l2_mbus_framefmt format;
  96         unsigned int page;
  97
  98         struct media_pad pads[ADV748X_CSI2_NR_PADS];
  99         struct v4l2_ctrl_handler ctrl_hdl;
 100         struct v4l2_ctrl *pixel_rate;
 101         struct v4l2_subdev sd;
 102 };
 103
 104 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
 105 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
 106
 107 enum adv748x_hdmi_pads {
 108         ADV748X_HDMI_SINK,
 109         ADV748X_HDMI_SOURCE,
 110         ADV748X_HDMI_NR_PADS,
 111 };
 112
 113 struct adv748x_hdmi {
 114         struct media_pad pads[ADV748X_HDMI_NR_PADS];
 115         struct v4l2_ctrl_handler ctrl_hdl;
 116         struct v4l2_subdev sd;
 117         struct v4l2_mbus_framefmt format;
 118
 119         struct v4l2_dv_timings timings;
 120         struct v4l2_fract aspect_ratio;
 121
 122         struct {
 123                 u8 edid[512];
 124                 u32 present;
 125                 unsigned int blocks;
 126         } edid;
 127 };
 128
 129 #define adv748x_ctrl_to_hdmi(ctrl) \
 130         container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
 131 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
 132
 133 enum adv748x_afe_pads {
 134         ADV748X_AFE_SINK_AIN0,
 135         ADV748X_AFE_SINK_AIN1,
 136         ADV748X_AFE_SINK_AIN2,
 137         ADV748X_AFE_SINK_AIN3,
 138         ADV748X_AFE_SINK_AIN4,
 139         ADV748X_AFE_SINK_AIN5,
 140         ADV748X_AFE_SINK_AIN6,
 141         ADV748X_AFE_SINK_AIN7,
 142         ADV748X_AFE_SOURCE,
 143         ADV748X_AFE_NR_PADS,
 144 };
 145
 146 struct adv748x_afe {
 147         struct media_pad pads[ADV748X_AFE_NR_PADS];
 148         struct v4l2_ctrl_handler ctrl_hdl;
 149         struct v4l2_subdev sd;
 150         struct v4l2_mbus_framefmt format;
 151
 152         bool streaming;
 153         v4l2_std_id curr_norm;
 154         unsigned int input;
 155 };
 156
 157 #define adv748x_ctrl_to_afe(ctrl) \
 158         container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
 159 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
 160
 161 /**
 162  * struct adv748x_state - State of ADV748X
 163  * @dev:                (OF) device
 164  * @client:             I2C client
 165  * @mutex:              protect global state
 166  *
 167  * @endpoints:          parsed device node endpoints for each port
 168  *
 169  * @i2c_addresses       I2C Page addresses
 170  * @i2c_clients         I2C clients for the page accesses
 171  * @regmap              regmap configuration pages.
 172  *
 173  * @hdmi:               state of HDMI receiver context
 174  * @afe:                state of AFE receiver context
 175  * @txa:                state of TXA transmitter context
 176  * @txb:                state of TXB transmitter context
 177  */
 178 struct adv748x_state {
 179         struct device *dev;
 180         struct i2c_client *client;
 181         struct mutex mutex;
 182
 183         struct device_node *endpoints[ADV748X_PORT_MAX];
 184
 185         struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
 186         struct regmap *regmap[ADV748X_PAGE_MAX];
 187
 188         struct adv748x_hdmi hdmi;
 189         struct adv748x_afe afe;
 190         struct adv748x_csi2 txa;
 191         struct adv748x_csi2 txb;
 192 };
 193
 194 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
 195 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
 196
 197 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
 198 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
 199 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
 200
 201 /* Register Mappings */
 202
 203 /* IO Map */
 204 #define ADV748X_IO_PD                   0x00    /* power down controls */
 205 #define ADV748X_IO_PD_RX_EN             BIT(6)
 206
 207 #define ADV748X_IO_REG_04               0x04
 208 #define ADV748X_IO_REG_04_FORCE_FR      BIT(0)  /* Force CP free-run */
 209
 210 #define ADV748X_IO_DATAPATH             0x03    /* datapath cntrl */
 211 #define ADV748X_IO_DATAPATH_VFREQ_M     0x70
 212 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
 213
 214 #define ADV748X_IO_VID_STD              0x05
 215
 216 #define ADV748X_IO_10                   0x10    /* io_reg_10 */
 217 #define ADV748X_IO_10_CSI4_EN           BIT(7)
 218 #define ADV748X_IO_10_CSI1_EN           BIT(6)
 219 #define ADV748X_IO_10_PIX_OUT_EN        BIT(5)
 220
 221 #define ADV748X_IO_CHIP_REV_ID_1        0xdf
 222 #define ADV748X_IO_CHIP_REV_ID_2        0xe0
 223
 224 #define ADV748X_IO_SLAVE_ADDR_BASE      0xf2
 225
 226 /* HDMI RX Map */
 227 #define ADV748X_HDMI_LW1                0x07    /* line width_1 */
 228 #define ADV748X_HDMI_LW1_VERT_FILTER    BIT(7)
 229 #define ADV748X_HDMI_LW1_DE_REGEN       BIT(5)
 230 #define ADV748X_HDMI_LW1_WIDTH_MASK     0x1fff
 231
 232 #define ADV748X_HDMI_F0H1               0x09    /* field0 height_1 */
 233 #define ADV748X_HDMI_F0H1_HEIGHT_MASK   0x1fff
 234
 235 #define ADV748X_HDMI_F1H1               0x0b    /* field1 height_1 */
 236 #define ADV748X_HDMI_F1H1_INTERLACED    BIT(5)
 237
 238 #define ADV748X_HDMI_HFRONT_PORCH       0x20    /* hsync_front_porch_1 */
 239 #define ADV748X_HDMI_HFRONT_PORCH_MASK  0x1fff
 240
 241 #define ADV748X_HDMI_HSYNC_WIDTH        0x22    /* hsync_pulse_width_1 */
 242 #define ADV748X_HDMI_HSYNC_WIDTH_MASK   0x1fff
 243
 244 #define ADV748X_HDMI_HBACK_PORCH        0x24    /* hsync_back_porch_1 */
 245 #define ADV748X_HDMI_HBACK_PORCH_MASK   0x1fff
 246
 247 #define ADV748X_HDMI_VFRONT_PORCH       0x2a    /* field0_vs_front_porch_1 */
 248 #define ADV748X_HDMI_VFRONT_PORCH_MASK  0x3fff
 249
 250 #define ADV748X_HDMI_VSYNC_WIDTH        0x2e    /* field0_vs_pulse_width_1 */
 251 #define ADV748X_HDMI_VSYNC_WIDTH_MASK   0x3fff
 252
 253 #define ADV748X_HDMI_VBACK_PORCH        0x32    /* field0_vs_back_porch_1 */
 254 #define ADV748X_HDMI_VBACK_PORCH_MASK   0x3fff
 255
 256 #define ADV748X_HDMI_TMDS_1             0x51    /* hdmi_reg_51 */
 257 #define ADV748X_HDMI_TMDS_2             0x52    /* hdmi_reg_52 */
 258
 259 /* HDMI RX Repeater Map */
 260 #define ADV748X_REPEATER_EDID_SZ        0x70    /* primary_edid_size */
 261 #define ADV748X_REPEATER_EDID_SZ_SHIFT  4
 262
 263 #define ADV748X_REPEATER_EDID_CTL       0x74    /* hdcp edid controls */
 264 #define ADV748X_REPEATER_EDID_CTL_EN    BIT(0)  /* man_edid_a_enable */
 265
 266 /* SDP Main Map */
 267 #define ADV748X_SDP_INSEL               0x00    /* user_map_rw_reg_00 */
 268
 269 #define ADV748X_SDP_VID_SEL             0x02    /* user_map_rw_reg_02 */
 270 #define ADV748X_SDP_VID_SEL_MASK        0xf0
 271 #define ADV748X_SDP_VID_SEL_SHIFT       4
 272
 273 /* Contrast - Unsigned*/
 274 #define ADV748X_SDP_CON                 0x08    /* user_map_rw_reg_08 */
 275 #define ADV748X_SDP_CON_MIN             0
 276 #define ADV748X_SDP_CON_DEF             128
 277 #define ADV748X_SDP_CON_MAX             255
 278
 279 /* Brightness - Signed */
 280 #define ADV748X_SDP_BRI                 0x0a    /* user_map_rw_reg_0a */
 281 #define ADV748X_SDP_BRI_MIN             -128
 282 #define ADV748X_SDP_BRI_DEF             0
 283 #define ADV748X_SDP_BRI_MAX             127
 284
 285 /* Hue - Signed, inverted*/
 286 #define ADV748X_SDP_HUE                 0x0b    /* user_map_rw_reg_0b */
 287 #define ADV748X_SDP_HUE_MIN             -127
 288 #define ADV748X_SDP_HUE_DEF             0
 289 #define ADV748X_SDP_HUE_MAX             128
 290
 291 /* Test Patterns / Default Values */
 292 #define ADV748X_SDP_DEF                 0x0c    /* user_map_rw_reg_0c */
 293 #define ADV748X_SDP_DEF_VAL_EN          BIT(0)  /* Force free run mode */
 294 #define ADV748X_SDP_DEF_VAL_AUTO_EN     BIT(1)  /* Free run when no signal */
 295
 296 #define ADV748X_SDP_MAP_SEL             0x0e    /* user_map_rw_reg_0e */
 297 #define ADV748X_SDP_MAP_SEL_RO_MAIN     1
 298
 299 /* Free run pattern select */
 300 #define ADV748X_SDP_FRP                 0x14
 301 #define ADV748X_SDP_FRP_MASK            GENMASK(3, 1)
 302
 303 /* Saturation */
 304 #define ADV748X_SDP_SD_SAT_U            0xe3    /* user_map_rw_reg_e3 */
 305 #define ADV748X_SDP_SD_SAT_V            0xe4    /* user_map_rw_reg_e4 */
 306 #define ADV748X_SDP_SAT_MIN             0
 307 #define ADV748X_SDP_SAT_DEF             128
 308 #define ADV748X_SDP_SAT_MAX             255
 309
 310 /* SDP RO Main Map */
 311 #define ADV748X_SDP_RO_10               0x10
 312 #define ADV748X_SDP_RO_10_IN_LOCK       BIT(0)
 313
 314 /* CP Map */
 315 #define ADV748X_CP_PAT_GEN              0x37    /* int_pat_gen_1 */
 316 #define ADV748X_CP_PAT_GEN_EN           BIT(7)
 317
 318 /* Contrast Control - Unsigned */
 319 #define ADV748X_CP_CON                  0x3a    /* contrast_cntrl */
 320 #define ADV748X_CP_CON_MIN              0       /* Minimum contrast */
 321 #define ADV748X_CP_CON_DEF              128     /* Default */
 322 #define ADV748X_CP_CON_MAX              255     /* Maximum contrast */
 323
 324 /* Saturation Control - Unsigned */
 325 #define ADV748X_CP_SAT                  0x3b    /* saturation_cntrl */
 326 #define ADV748X_CP_SAT_MIN              0       /* Minimum saturation */
 327 #define ADV748X_CP_SAT_DEF              128     /* Default */
 328 #define ADV748X_CP_SAT_MAX              255     /* Maximum saturation */
 329
 330 /* Brightness Control - Signed */
 331 #define ADV748X_CP_BRI                  0x3c    /* brightness_cntrl */
 332 #define ADV748X_CP_BRI_MIN              -128    /* Luma is -512d */
 333 #define ADV748X_CP_BRI_DEF              0       /* Luma is 0 */
 334 #define ADV748X_CP_BRI_MAX              127     /* Luma is 508d */
 335
 336 /* Hue Control */
 337 #define ADV748X_CP_HUE                  0x3d    /* hue_cntrl */
 338 #define ADV748X_CP_HUE_MIN              0       /* -90 degree */
 339 #define ADV748X_CP_HUE_DEF              0       /* -90 degree */
 340 #define ADV748X_CP_HUE_MAX              255     /* +90 degree */
 341
 342 #define ADV748X_CP_VID_ADJ              0x3e    /* vid_adj_0 */
 343 #define ADV748X_CP_VID_ADJ_ENABLE       BIT(7)  /* Enable colour controls */
 344
 345 #define ADV748X_CP_DE_POS_HIGH          0x8b    /* de_pos_adj_6 */
 346 #define ADV748X_CP_DE_POS_HIGH_SET      BIT(6)
 347 #define ADV748X_CP_DE_POS_END_LOW       0x8c    /* de_pos_adj_7 */
 348 #define ADV748X_CP_DE_POS_START_LOW     0x8d    /* de_pos_adj_8 */
 349
 350 #define ADV748X_CP_VID_ADJ_2                    0x91
 351 #define ADV748X_CP_VID_ADJ_2_INTERLACED         BIT(6)
 352 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D      BIT(4)
 353
 354 #define ADV748X_CP_CLMP_POS             0xc9    /* clmp_pos_cntrl_4 */
 355 #define ADV748X_CP_CLMP_POS_DIS_AUTO    BIT(0)  /* dis_auto_param_buff */
 356
 357 /* CSI : TXA/TXB Maps */
 358 #define ADV748X_CSI_VC_REF              0x0d    /* csi_tx_top_reg_0d */
 359 #define ADV748X_CSI_VC_REF_SHIFT        6
 360
 361 #define ADV748X_CSI_FS_AS_LS            0x1e    /* csi_tx_top_reg_1e */
 362 #define ADV748X_CSI_FS_AS_LS_UNKNOWN    BIT(6)  /* Undocumented bit */
 363
 364 /* Register handling */
 365
 366 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
 367 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
 368 int adv748x_write_block(struct adv748x_state *state, int client_page,
 369                         unsigned int init_reg, const void *val,
 370                         size_t val_len);
 371
 372 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
 373 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
 374 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~m) | v)
 375
 376 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
 377 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, r+1)) & m)
 378 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
 379
 380 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
 381 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
 382
 383 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
 384 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
 385 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~m) | v)
 386
 387 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
 388 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
 389 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~m) | v)
 390
 391 #define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
 392 #define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)
 393
 394 #define tx_read(t, r) adv748x_read(t->state, t->page, r)
 395 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
 396
 397 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
 398 {
 399         pad = media_entity_remote_pad(pad);
 400         if (!pad)
 401                 return NULL;
 402
 403         return media_entity_to_v4l2_subdev(pad->entity);
 404 }
 405
 406 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
 407                          const struct v4l2_subdev_ops *ops, u32 function,
 408                          const char *ident);
 409
 410 int adv748x_register_subdevs(struct adv748x_state *state,
 411                              struct v4l2_device *v4l2_dev);
 412
 413 int adv748x_txa_power(struct adv748x_state *state, bool on);
 414 int adv748x_txb_power(struct adv748x_state *state, bool on);
 415
 416 int adv748x_afe_init(struct adv748x_afe *afe);
 417 void adv748x_afe_cleanup(struct adv748x_afe *afe);
 418
 419 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
 420 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
 421 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
 422
 423 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
 424 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
 425
 426 #endif /* _ADV748X_H_ */