arch/s390/include/asm/ptrace.h

   1 /*
   2  *  include/asm-s390/ptrace.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
   7  */
   8
   9 #ifndef _S390_PTRACE_H
  10 #define _S390_PTRACE_H
  11
  12 /*
  13  * Offsets in the user_regs_struct. They are used for the ptrace
  14  * system call and in entry.S
  15  */
  16 #ifndef __s390x__
  17
  18 #define PT_PSWMASK  0x00
  19 #define PT_PSWADDR  0x04
  20 #define PT_GPR0     0x08
  21 #define PT_GPR1     0x0C
  22 #define PT_GPR2     0x10
  23 #define PT_GPR3     0x14
  24 #define PT_GPR4     0x18
  25 #define PT_GPR5     0x1C
  26 #define PT_GPR6     0x20
  27 #define PT_GPR7     0x24
  28 #define PT_GPR8     0x28
  29 #define PT_GPR9     0x2C
  30 #define PT_GPR10    0x30
  31 #define PT_GPR11    0x34
  32 #define PT_GPR12    0x38
  33 #define PT_GPR13    0x3C
  34 #define PT_GPR14    0x40
  35 #define PT_GPR15    0x44
  36 #define PT_ACR0     0x48
  37 #define PT_ACR1     0x4C
  38 #define PT_ACR2     0x50
  39 #define PT_ACR3     0x54
  40 #define PT_ACR4     0x58
  41 #define PT_ACR5     0x5C
  42 #define PT_ACR6     0x60
  43 #define PT_ACR7     0x64
  44 #define PT_ACR8     0x68
  45 #define PT_ACR9     0x6C
  46 #define PT_ACR10    0x70
  47 #define PT_ACR11    0x74
  48 #define PT_ACR12    0x78
  49 #define PT_ACR13    0x7C
  50 #define PT_ACR14    0x80
  51 #define PT_ACR15    0x84
  52 #define PT_ORIGGPR2 0x88
  53 #define PT_FPC      0x90
  54 /*
  55  * A nasty fact of life that the ptrace api
  56  * only supports passing of longs.
  57  */
  58 #define PT_FPR0_HI  0x98
  59 #define PT_FPR0_LO  0x9C
  60 #define PT_FPR1_HI  0xA0
  61 #define PT_FPR1_LO  0xA4
  62 #define PT_FPR2_HI  0xA8
  63 #define PT_FPR2_LO  0xAC
  64 #define PT_FPR3_HI  0xB0
  65 #define PT_FPR3_LO  0xB4
  66 #define PT_FPR4_HI  0xB8
  67 #define PT_FPR4_LO  0xBC
  68 #define PT_FPR5_HI  0xC0
  69 #define PT_FPR5_LO  0xC4
  70 #define PT_FPR6_HI  0xC8
  71 #define PT_FPR6_LO  0xCC
  72 #define PT_FPR7_HI  0xD0
  73 #define PT_FPR7_LO  0xD4
  74 #define PT_FPR8_HI  0xD8
  75 #define PT_FPR8_LO  0XDC
  76 #define PT_FPR9_HI  0xE0
  77 #define PT_FPR9_LO  0xE4
  78 #define PT_FPR10_HI 0xE8
  79 #define PT_FPR10_LO 0xEC
  80 #define PT_FPR11_HI 0xF0
  81 #define PT_FPR11_LO 0xF4
  82 #define PT_FPR12_HI 0xF8
  83 #define PT_FPR12_LO 0xFC
  84 #define PT_FPR13_HI 0x100
  85 #define PT_FPR13_LO 0x104
  86 #define PT_FPR14_HI 0x108
  87 #define PT_FPR14_LO 0x10C
  88 #define PT_FPR15_HI 0x110
  89 #define PT_FPR15_LO 0x114
  90 #define PT_CR_9     0x118
  91 #define PT_CR_10    0x11C
  92 #define PT_CR_11    0x120
  93 #define PT_IEEE_IP  0x13C
  94 #define PT_LASTOFF  PT_IEEE_IP
  95 #define PT_ENDREGS  0x140-1
  96
  97 #define GPR_SIZE        4
  98 #define CR_SIZE         4
  99
 100 #define STACK_FRAME_OVERHEAD    96      /* size of minimum stack frame */
 101
 102 #else /* __s390x__ */
 103
 104 #define PT_PSWMASK  0x00
 105 #define PT_PSWADDR  0x08
 106 #define PT_GPR0     0x10
 107 #define PT_GPR1     0x18
 108 #define PT_GPR2     0x20
 109 #define PT_GPR3     0x28
 110 #define PT_GPR4     0x30
 111 #define PT_GPR5     0x38
 112 #define PT_GPR6     0x40
 113 #define PT_GPR7     0x48
 114 #define PT_GPR8     0x50
 115 #define PT_GPR9     0x58
 116 #define PT_GPR10    0x60
 117 #define PT_GPR11    0x68
 118 #define PT_GPR12    0x70
 119 #define PT_GPR13    0x78
 120 #define PT_GPR14    0x80
 121 #define PT_GPR15    0x88
 122 #define PT_ACR0     0x90
 123 #define PT_ACR1     0x94
 124 #define PT_ACR2     0x98
 125 #define PT_ACR3     0x9C
 126 #define PT_ACR4     0xA0
 127 #define PT_ACR5     0xA4
 128 #define PT_ACR6     0xA8
 129 #define PT_ACR7     0xAC
 130 #define PT_ACR8     0xB0
 131 #define PT_ACR9     0xB4
 132 #define PT_ACR10    0xB8
 133 #define PT_ACR11    0xBC
 134 #define PT_ACR12    0xC0
 135 #define PT_ACR13    0xC4
 136 #define PT_ACR14    0xC8
 137 #define PT_ACR15    0xCC
 138 #define PT_ORIGGPR2 0xD0
 139 #define PT_FPC      0xD8
 140 #define PT_FPR0     0xE0
 141 #define PT_FPR1     0xE8
 142 #define PT_FPR2     0xF0
 143 #define PT_FPR3     0xF8
 144 #define PT_FPR4     0x100
 145 #define PT_FPR5     0x108
 146 #define PT_FPR6     0x110
 147 #define PT_FPR7     0x118
 148 #define PT_FPR8     0x120
 149 #define PT_FPR9     0x128
 150 #define PT_FPR10    0x130
 151 #define PT_FPR11    0x138
 152 #define PT_FPR12    0x140
 153 #define PT_FPR13    0x148
 154 #define PT_FPR14    0x150
 155 #define PT_FPR15    0x158
 156 #define PT_CR_9     0x160
 157 #define PT_CR_10    0x168
 158 #define PT_CR_11    0x170
 159 #define PT_IEEE_IP  0x1A8
 160 #define PT_LASTOFF  PT_IEEE_IP
 161 #define PT_ENDREGS  0x1B0-1
 162
 163 #define GPR_SIZE        8
 164 #define CR_SIZE         8
 165
 166 #define STACK_FRAME_OVERHEAD    160      /* size of minimum stack frame */
 167
 168 #endif /* __s390x__ */
 169
 170 #define NUM_GPRS        16
 171 #define NUM_FPRS        16
 172 #define NUM_CRS         16
 173 #define NUM_ACRS        16
 174
 175 #define NUM_CR_WORDS    3
 176
 177 #define FPR_SIZE        8
 178 #define FPC_SIZE        4
 179 #define FPC_PAD_SIZE    4 /* gcc insists on aligning the fpregs */
 180 #define ACR_SIZE        4
 181
 182
 183 #define PTRACE_OLDSETOPTIONS         21
 184
 185 #ifndef __ASSEMBLY__
 186 #include <linux/stddef.h>
 187 #include <linux/types.h>
 188
 189 typedef union
 190 {
 191         float   f;
 192         double  d;
 193         __u64   ui;
 194         struct
 195         {
 196                 __u32 hi;
 197                 __u32 lo;
 198         } fp;
 199 } freg_t;
 200
 201 typedef struct
 202 {
 203         __u32   fpc;
 204         freg_t  fprs[NUM_FPRS];
 205 } s390_fp_regs;
 206
 207 #define FPC_EXCEPTION_MASK      0xF8000000
 208 #define FPC_FLAGS_MASK          0x00F80000
 209 #define FPC_DXC_MASK            0x0000FF00
 210 #define FPC_RM_MASK             0x00000003
 211 #define FPC_VALID_MASK          0xF8F8FF03
 212
 213 /* this typedef defines how a Program Status Word looks like */
 214 typedef struct
 215 {
 216         unsigned long mask;
 217         unsigned long addr;
 218 } __attribute__ ((aligned(8))) psw_t;
 219
 220 typedef struct
 221 {
 222         __u32   mask;
 223         __u32   addr;
 224 } __attribute__ ((aligned(8))) psw_compat_t;
 225
 226 #ifndef __s390x__
 227
 228 #define PSW_MASK_PER            0x40000000UL
 229 #define PSW_MASK_DAT            0x04000000UL
 230 #define PSW_MASK_IO             0x02000000UL
 231 #define PSW_MASK_EXT            0x01000000UL
 232 #define PSW_MASK_KEY            0x00F00000UL
 233 #define PSW_MASK_MCHECK         0x00040000UL
 234 #define PSW_MASK_WAIT           0x00020000UL
 235 #define PSW_MASK_PSTATE         0x00010000UL
 236 #define PSW_MASK_ASC            0x0000C000UL
 237 #define PSW_MASK_CC             0x00003000UL
 238 #define PSW_MASK_PM             0x00000F00UL
 239
 240 #define PSW_ADDR_AMODE          0x80000000UL
 241 #define PSW_ADDR_INSN           0x7FFFFFFFUL
 242
 243 #define PSW_BASE_BITS           0x00080000UL
 244 #define PSW_DEFAULT_KEY         (((unsigned long) PAGE_DEFAULT_ACC) << 20)
 245
 246 #define PSW_ASC_PRIMARY         0x00000000UL
 247 #define PSW_ASC_ACCREG          0x00004000UL
 248 #define PSW_ASC_SECONDARY       0x00008000UL
 249 #define PSW_ASC_HOME            0x0000C000UL
 250
 251 #else /* __s390x__ */
 252
 253 #define PSW_MASK_PER            0x4000000000000000UL
 254 #define PSW_MASK_DAT            0x0400000000000000UL
 255 #define PSW_MASK_IO             0x0200000000000000UL
 256 #define PSW_MASK_EXT            0x0100000000000000UL
 257 #define PSW_MASK_KEY            0x00F0000000000000UL
 258 #define PSW_MASK_MCHECK         0x0004000000000000UL
 259 #define PSW_MASK_WAIT           0x0002000000000000UL
 260 #define PSW_MASK_PSTATE         0x0001000000000000UL
 261 #define PSW_MASK_ASC            0x0000C00000000000UL
 262 #define PSW_MASK_CC             0x0000300000000000UL
 263 #define PSW_MASK_PM             0x00000F0000000000UL
 264
 265 #define PSW_ADDR_AMODE          0x0000000000000000UL
 266 #define PSW_ADDR_INSN           0xFFFFFFFFFFFFFFFFUL
 267
 268 #define PSW_BASE_BITS           0x0000000180000000UL
 269 #define PSW_BASE32_BITS         0x0000000080000000UL
 270 #define PSW_DEFAULT_KEY         (((unsigned long) PAGE_DEFAULT_ACC) << 52)
 271
 272 #define PSW_ASC_PRIMARY         0x0000000000000000UL
 273 #define PSW_ASC_ACCREG          0x0000400000000000UL
 274 #define PSW_ASC_SECONDARY       0x0000800000000000UL
 275 #define PSW_ASC_HOME            0x0000C00000000000UL
 276
 277 #endif /* __s390x__ */
 278
 279 #ifdef __KERNEL__
 280 extern long psw_kernel_bits;
 281 extern long psw_user_bits;
 282 #ifdef CONFIG_64BIT
 283 extern long psw_user32_bits;
 284 #endif
 285 #endif
 286
 287 /* This macro merges a NEW PSW mask specified by the user into
 288    the currently active PSW mask CURRENT, modifying only those
 289    bits in CURRENT that the user may be allowed to change: this
 290    is the condition code and the program mask bits.  */
 291 #define PSW_MASK_MERGE(CURRENT,NEW) \
 292         (((CURRENT) & ~(PSW_MASK_CC|PSW_MASK_PM)) | \
 293          ((NEW) & (PSW_MASK_CC|PSW_MASK_PM)))
 294
 295 /*
 296  * The s390_regs structure is used to define the elf_gregset_t.
 297  */
 298 typedef struct
 299 {
 300         psw_t psw;
 301         unsigned long gprs[NUM_GPRS];
 302         unsigned int  acrs[NUM_ACRS];
 303         unsigned long orig_gpr2;
 304 } s390_regs;
 305
 306 typedef struct
 307 {
 308         psw_compat_t    psw;
 309         __u32           gprs[NUM_GPRS];
 310         __u32           acrs[NUM_ACRS];
 311         __u32           orig_gpr2;
 312 } s390_compat_regs;
 313
 314 typedef struct
 315 {
 316         __u32           gprs_high[NUM_GPRS];
 317 } s390_compat_regs_high;
 318
 319 #ifdef __KERNEL__
 320
 321 /*
 322  * The pt_regs struct defines the way the registers are stored on
 323  * the stack during a system call.
 324  */
 325 struct pt_regs
 326 {
 327         unsigned long args[1];
 328         psw_t psw;
 329         unsigned long gprs[NUM_GPRS];
 330         unsigned long orig_gpr2;
 331         unsigned short svcnr;
 332         unsigned short ilc;
 333 };
 334 #endif
 335
 336 /*
 337  * Now for the program event recording (trace) definitions.
 338  */
 339 typedef struct
 340 {
 341         unsigned long cr[NUM_CR_WORDS];
 342 } per_cr_words;
 343
 344 #define PER_EM_MASK 0xE8000000UL
 345
 346 typedef struct
 347 {
 348 #ifdef __s390x__
 349         unsigned                       : 32;
 350 #endif /* __s390x__ */
 351         unsigned em_branching          : 1;
 352         unsigned em_instruction_fetch  : 1;
 353         /*
 354          * Switching on storage alteration automatically fixes
 355          * the storage alteration event bit in the users std.
 356          */
 357         unsigned em_storage_alteration : 1;
 358         unsigned em_gpr_alt_unused     : 1;
 359         unsigned em_store_real_address : 1;
 360         unsigned                       : 3;
 361         unsigned branch_addr_ctl       : 1;
 362         unsigned                       : 1;
 363         unsigned storage_alt_space_ctl : 1;
 364         unsigned                       : 21;
 365         unsigned long starting_addr;
 366         unsigned long ending_addr;
 367 } per_cr_bits;
 368
 369 typedef struct
 370 {
 371         unsigned short perc_atmid;
 372         unsigned long address;
 373         unsigned char access_id;
 374 } per_lowcore_words;
 375
 376 typedef struct
 377 {
 378         unsigned perc_branching          : 1;
 379         unsigned perc_instruction_fetch  : 1;
 380         unsigned perc_storage_alteration : 1;
 381         unsigned perc_gpr_alt_unused     : 1;
 382         unsigned perc_store_real_address : 1;
 383         unsigned                         : 3;
 384         unsigned atmid_psw_bit_31        : 1;
 385         unsigned atmid_validity_bit      : 1;
 386         unsigned atmid_psw_bit_32        : 1;
 387         unsigned atmid_psw_bit_5         : 1;
 388         unsigned atmid_psw_bit_16        : 1;
 389         unsigned atmid_psw_bit_17        : 1;
 390         unsigned si                      : 2;
 391         unsigned long address;
 392         unsigned                         : 4;
 393         unsigned access_id               : 4;
 394 } per_lowcore_bits;
 395
 396 typedef struct
 397 {
 398         union {
 399                 per_cr_words   words;
 400                 per_cr_bits    bits;
 401         } control_regs;
 402         /*
 403          * Use these flags instead of setting em_instruction_fetch
 404          * directly they are used so that single stepping can be
 405          * switched on & off while not affecting other tracing
 406          */
 407         unsigned  single_step       : 1;
 408         unsigned  instruction_fetch : 1;
 409         unsigned                    : 30;
 410         /*
 411          * These addresses are copied into cr10 & cr11 if single
 412          * stepping is switched off
 413          */
 414         unsigned long starting_addr;
 415         unsigned long ending_addr;
 416         union {
 417                 per_lowcore_words words;
 418                 per_lowcore_bits  bits;
 419         } lowcore;
 420 } per_struct;
 421
 422 typedef struct
 423 {
 424         unsigned int  len;
 425         unsigned long kernel_addr;
 426         unsigned long process_addr;
 427 } ptrace_area;
 428
 429 /*
 430  * S/390 specific non posix ptrace requests. I chose unusual values so
 431  * they are unlikely to clash with future ptrace definitions.
 432  */
 433 #define PTRACE_PEEKUSR_AREA           0x5000
 434 #define PTRACE_POKEUSR_AREA           0x5001
 435 #define PTRACE_PEEKTEXT_AREA          0x5002
 436 #define PTRACE_PEEKDATA_AREA          0x5003
 437 #define PTRACE_POKETEXT_AREA          0x5004
 438 #define PTRACE_POKEDATA_AREA          0x5005
 439
 440 /*
 441  * PT_PROT definition is loosely based on hppa bsd definition in
 442  * gdb/hppab-nat.c
 443  */
 444 #define PTRACE_PROT                       21
 445
 446 typedef enum
 447 {
 448         ptprot_set_access_watchpoint,
 449         ptprot_set_write_watchpoint,
 450         ptprot_disable_watchpoint
 451 } ptprot_flags;
 452
 453 typedef struct
 454 {
 455         unsigned long lowaddr;
 456         unsigned long hiaddr;
 457         ptprot_flags prot;
 458 } ptprot_area;
 459
 460 /* Sequence of bytes for breakpoint illegal instruction.  */
 461 #define S390_BREAKPOINT     {0x0,0x1}
 462 #define S390_BREAKPOINT_U16 ((__u16)0x0001)
 463 #define S390_SYSCALL_OPCODE ((__u16)0x0a00)
 464 #define S390_SYSCALL_SIZE   2
 465
 466 /*
 467  * The user_regs_struct defines the way the user registers are
 468  * store on the stack for signal handling.
 469  */
 470 struct user_regs_struct
 471 {
 472         psw_t psw;
 473         unsigned long gprs[NUM_GPRS];
 474         unsigned int  acrs[NUM_ACRS];
 475         unsigned long orig_gpr2;
 476         s390_fp_regs fp_regs;
 477         /*
 478          * These per registers are in here so that gdb can modify them
 479          * itself as there is no "official" ptrace interface for hardware
 480          * watchpoints. This is the way intel does it.
 481          */
 482         per_struct per_info;
 483         unsigned long ieee_instruction_pointer;
 484         /* Used to give failing instruction back to user for ieee exceptions */
 485 };
 486
 487 #ifdef __KERNEL__
 488 /*
 489  * These are defined as per linux/ptrace.h, which see.
 490  */
 491 #define arch_has_single_step()  (1)
 492 struct task_struct;
 493 extern void user_enable_single_step(struct task_struct *);
 494 extern void user_disable_single_step(struct task_struct *);
 495
 496 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
 497 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
 498 #define user_stack_pointer(regs)((regs)->gprs[15])
 499 #define regs_return_value(regs)((regs)->gprs[2])
 500 #define profile_pc(regs) instruction_pointer(regs)
 501 extern void show_regs(struct pt_regs * regs);
 502 #endif /* __KERNEL__ */
 503 #endif /* __ASSEMBLY__ */
 504
 505 #endif /* _S390_PTRACE_H */