?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
blob72ed3396b721e36d528f3d6191034493447c33ae
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <net/net_namespace.h>
41
42 #include "cxio_resource.h"
43 #include "cxio_hal.h"
44 #include "cxgb3_offload.h"
45 #include "sge_defs.h"
46
47 static LIST_HEAD(rdev_list);
48 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
49
50 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
51 {
52 struct cxio_rdev *rdev;
53
54 list_for_each_entry(rdev, &rdev_list, entry)
55 if (!strcmp(rdev->dev_name, dev_name))
56 return rdev;
57 return NULL;
58 }
59
60 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
61 {
62 struct cxio_rdev *rdev;
63
64 list_for_each_entry(rdev, &rdev_list, entry)
65 if (rdev->t3cdev_p == tdev)
66 return rdev;
67 return NULL;
68 }
69
70 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
71 enum t3_cq_opcode op, u32 credit)
72 {
73 int ret;
74 struct t3_cqe *cqe;
75 u32 rptr;
76
77 struct rdma_cq_op setup;
78 setup.id = cq->cqid;
79 setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
80 setup.op = op;
81 ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
82
83 if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
84 return ret;
85
86 /*
87 * If the rearm returned an index other than our current index,
88 * then there might be CQE's in flight (being DMA'd). We must wait
89 * here for them to complete or the consumer can miss a notification.
90 */
91 if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
92 int i=0;
93
94 rptr = cq->rptr;
95
96 /*
97 * Keep the generation correct by bumping rptr until it
98 * matches the index returned by the rearm - 1.
99 */
100 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
101 rptr++;
102
103 /*
104 * Now rptr is the index for the (last) cqe that was
105 * in-flight at the time the HW rearmed the CQ. We
106 * spin until that CQE is valid.
107 */
108 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
109 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
110 udelay(1);
111 if (i++ > 1000000) {
112 BUG_ON(1);
113 printk(KERN_ERR "%s: stalled rnic\n",
114 rdev_p->dev_name);
115 return -EIO;
116 }
117 }
118
119 return 1;
120 }
121
122 return 0;
123 }
124
125 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
126 {
127 struct rdma_cq_setup setup;
128 setup.id = cqid;
129 setup.base_addr = 0; /* NULL address */
130 setup.size = 0; /* disaable the CQ */
131 setup.credits = 0;
132 setup.credit_thres = 0;
133 setup.ovfl_mode = 0;
134 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
135 }
136
137 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
138 {
139 u64 sge_cmd;
140 struct t3_modify_qp_wr *wqe;
141 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
142 if (!skb) {
143 PDBG("%s alloc_skb failed\n", __func__);
144 return -ENOMEM;
145 }
146 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
147 memset(wqe, 0, sizeof(*wqe));
148 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
149 T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
150 T3_SOPEOP);
151 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
152 sge_cmd = qpid << 8 | 3;
153 wqe->sge_cmd = cpu_to_be64(sge_cmd);
154 skb->priority = CPL_PRIORITY_CONTROL;
155 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
156 }
157
158 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
159 {
160 struct rdma_cq_setup setup;
161 int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
162
163 cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
164 if (!cq->cqid)
165 return -ENOMEM;
166 cq->sw_queue = kzalloc(size, GFP_KERNEL);
167 if (!cq->sw_queue)
168 return -ENOMEM;
169 cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
170 (1UL << (cq->size_log2)) *
171 sizeof(struct t3_cqe),
172 &(cq->dma_addr), GFP_KERNEL);
173 if (!cq->queue) {
174 kfree(cq->sw_queue);
175 return -ENOMEM;
176 }
177 pci_unmap_addr_set(cq, mapping, cq->dma_addr);
178 memset(cq->queue, 0, size);
179 setup.id = cq->cqid;
180 setup.base_addr = (u64) (cq->dma_addr);
181 setup.size = 1UL << cq->size_log2;
182 setup.credits = 65535;
183 setup.credit_thres = 1;
184 if (rdev_p->t3cdev_p->type != T3A)
185 setup.ovfl_mode = 0;
186 else
187 setup.ovfl_mode = 1;
188 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
189 }
190
191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
192 {
193 struct rdma_cq_setup setup;
194 setup.id = cq->cqid;
195 setup.base_addr = (u64) (cq->dma_addr);
196 setup.size = 1UL << cq->size_log2;
197 setup.credits = setup.size;
198 setup.credit_thres = setup.size; /* TBD: overflow recovery */
199 setup.ovfl_mode = 1;
200 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
201 }
202
203 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
204 {
205 struct cxio_qpid_list *entry;
206 u32 qpid;
207 int i;
208
209 mutex_lock(&uctx->lock);
210 if (!list_empty(&uctx->qpids)) {
211 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
212 entry);
213 list_del(&entry->entry);
214 qpid = entry->qpid;
215 kfree(entry);
216 } else {
217 qpid = cxio_hal_get_qpid(rdev_p->rscp);
218 if (!qpid)
219 goto out;
220 for (i = qpid+1; i & rdev_p->qpmask; i++) {
221 entry = kmalloc(sizeof *entry, GFP_KERNEL);
222 if (!entry)
223 break;
224 entry->qpid = i;
225 list_add_tail(&entry->entry, &uctx->qpids);
226 }
227 }
228 out:
229 mutex_unlock(&uctx->lock);
230 PDBG("%s qpid 0x%x\n", __func__, qpid);
231 return qpid;
232 }
233
234 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
235 struct cxio_ucontext *uctx)
236 {
237 struct cxio_qpid_list *entry;
238
239 entry = kmalloc(sizeof *entry, GFP_KERNEL);
240 if (!entry)
241 return;
242 PDBG("%s qpid 0x%x\n", __func__, qpid);
243 entry->qpid = qpid;
244 mutex_lock(&uctx->lock);
245 list_add_tail(&entry->entry, &uctx->qpids);
246 mutex_unlock(&uctx->lock);
247 }
248
249 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
250 {
251 struct list_head *pos, *nxt;
252 struct cxio_qpid_list *entry;
253
254 mutex_lock(&uctx->lock);
255 list_for_each_safe(pos, nxt, &uctx->qpids) {
256 entry = list_entry(pos, struct cxio_qpid_list, entry);
257 list_del_init(&entry->entry);
258 if (!(entry->qpid & rdev_p->qpmask))
259 cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
260 kfree(entry);
261 }
262 mutex_unlock(&uctx->lock);
263 }
264
265 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
266 {
267 INIT_LIST_HEAD(&uctx->qpids);
268 mutex_init(&uctx->lock);
269 }
270
271 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
272 struct t3_wq *wq, struct cxio_ucontext *uctx)
273 {
274 int depth = 1UL << wq->size_log2;
275 int rqsize = 1UL << wq->rq_size_log2;
276
277 wq->qpid = get_qpid(rdev_p, uctx);
278 if (!wq->qpid)
279 return -ENOMEM;
280
281 wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
282 if (!wq->rq)
283 goto err1;
284
285 wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
286 if (!wq->rq_addr)
287 goto err2;
288
289 wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
290 if (!wq->sq)
291 goto err3;
292
293 wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
294 depth * sizeof(union t3_wr),
295 &(wq->dma_addr), GFP_KERNEL);
296 if (!wq->queue)
297 goto err4;
298
299 memset(wq->queue, 0, depth * sizeof(union t3_wr));
300 pci_unmap_addr_set(wq, mapping, wq->dma_addr);
301 wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
302 if (!kernel_domain)
303 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
304 (wq->qpid << rdev_p->qpshift);
305 wq->rdev = rdev_p;
306 PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__,
307 wq->qpid, wq->doorbell, (unsigned long long) wq->udb);
308 return 0;
309 err4:
310 kfree(wq->sq);
311 err3:
312 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
313 err2:
314 kfree(wq->rq);
315 err1:
316 put_qpid(rdev_p, wq->qpid, uctx);
317 return -ENOMEM;
318 }
319
320 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
321 {
322 int err;
323 err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
324 kfree(cq->sw_queue);
325 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
326 (1UL << (cq->size_log2))
327 * sizeof(struct t3_cqe), cq->queue,
328 pci_unmap_addr(cq, mapping));
329 cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
330 return err;
331 }
332
333 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
334 struct cxio_ucontext *uctx)
335 {
336 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
337 (1UL << (wq->size_log2))
338 * sizeof(union t3_wr), wq->queue,
339 pci_unmap_addr(wq, mapping));
340 kfree(wq->sq);
341 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
342 kfree(wq->rq);
343 put_qpid(rdev_p, wq->qpid, uctx);
344 return 0;
345 }
346
347 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
348 {
349 struct t3_cqe cqe;
350
351 PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
352 wq, cq, cq->sw_rptr, cq->sw_wptr);
353 memset(&cqe, 0, sizeof(cqe));
354 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
355 V_CQE_OPCODE(T3_SEND) |
356 V_CQE_TYPE(0) |
357 V_CQE_SWCQE(1) |
358 V_CQE_QPID(wq->qpid) |
359 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
360 cq->size_log2)));
361 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
362 cq->sw_wptr++;
363 }
364
365 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
366 {
367 u32 ptr;
368 int flushed = 0;
369
370 PDBG("%s wq %p cq %p\n", __func__, wq, cq);
371
372 /* flush RQ */
373 PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
374 wq->rq_rptr, wq->rq_wptr, count);
375 ptr = wq->rq_rptr + count;
376 while (ptr++ != wq->rq_wptr) {
377 insert_recv_cqe(wq, cq);
378 flushed++;
379 }
380 return flushed;
381 }
382
383 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
384 struct t3_swsq *sqp)
385 {
386 struct t3_cqe cqe;
387
388 PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
389 wq, cq, cq->sw_rptr, cq->sw_wptr);
390 memset(&cqe, 0, sizeof(cqe));
391 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
392 V_CQE_OPCODE(sqp->opcode) |
393 V_CQE_TYPE(1) |
394 V_CQE_SWCQE(1) |
395 V_CQE_QPID(wq->qpid) |
396 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
397 cq->size_log2)));
398 cqe.u.scqe.wrid_hi = sqp->sq_wptr;
399
400 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
401 cq->sw_wptr++;
402 }
403
404 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
405 {
406 __u32 ptr;
407 int flushed = 0;
408 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
409
410 ptr = wq->sq_rptr + count;
411 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
412 while (ptr != wq->sq_wptr) {
413 sqp->signaled = 0;
414 insert_sq_cqe(wq, cq, sqp);
415 ptr++;
416 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
417 flushed++;
418 }
419 return flushed;
420 }
421
422 /*
423 * Move all CQEs from the HWCQ into the SWCQ.
424 */
425 void cxio_flush_hw_cq(struct t3_cq *cq)
426 {
427 struct t3_cqe *cqe, *swcqe;
428
429 PDBG("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
430 cqe = cxio_next_hw_cqe(cq);
431 while (cqe) {
432 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
433 __func__, cq->rptr, cq->sw_wptr);
434 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
435 *swcqe = *cqe;
436 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
437 cq->sw_wptr++;
438 cq->rptr++;
439 cqe = cxio_next_hw_cqe(cq);
440 }
441 }
442
443 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
444 {
445 if (CQE_OPCODE(*cqe) == T3_TERMINATE)
446 return 0;
447
448 if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
449 return 0;
450
451 if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
452 return 0;
453
454 if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
455 Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
456 return 0;
457
458 return 1;
459 }
460
461 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
462 {
463 struct t3_cqe *cqe;
464 u32 ptr;
465
466 *count = 0;
467 ptr = cq->sw_rptr;
468 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
469 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
470 if ((SQ_TYPE(*cqe) ||
471 ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
472 (CQE_QPID(*cqe) == wq->qpid))
473 (*count)++;
474 ptr++;
475 }
476 PDBG("%s cq %p count %d\n", __func__, cq, *count);
477 }
478
479 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
480 {
481 struct t3_cqe *cqe;
482 u32 ptr;
483
484 *count = 0;
485 PDBG("%s count zero %d\n", __func__, *count);
486 ptr = cq->sw_rptr;
487 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
488 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
489 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
490 (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
491 (*count)++;
492 ptr++;
493 }
494 PDBG("%s cq %p count %d\n", __func__, cq, *count);
495 }
496
497 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
498 {
499 struct rdma_cq_setup setup;
500 setup.id = 0;
501 setup.base_addr = 0; /* NULL address */
502 setup.size = 1; /* enable the CQ */
503 setup.credits = 0;
504
505 /* force SGE to redirect to RspQ and interrupt */
506 setup.credit_thres = 0;
507 setup.ovfl_mode = 1;
508 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
509 }
510
511 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
512 {
513 int err;
514 u64 sge_cmd, ctx0, ctx1;
515 u64 base_addr;
516 struct t3_modify_qp_wr *wqe;
517 struct sk_buff *skb;
518
519 skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
520 if (!skb) {
521 PDBG("%s alloc_skb failed\n", __func__);
522 return -ENOMEM;
523 }
524 err = cxio_hal_init_ctrl_cq(rdev_p);
525 if (err) {
526 PDBG("%s err %d initializing ctrl_cq\n", __func__, err);
527 goto err;
528 }
529 rdev_p->ctrl_qp.workq = dma_alloc_coherent(
530 &(rdev_p->rnic_info.pdev->dev),
531 (1 << T3_CTRL_QP_SIZE_LOG2) *
532 sizeof(union t3_wr),
533 &(rdev_p->ctrl_qp.dma_addr),
534 GFP_KERNEL);
535 if (!rdev_p->ctrl_qp.workq) {
536 PDBG("%s dma_alloc_coherent failed\n", __func__);
537 err = -ENOMEM;
538 goto err;
539 }
540 pci_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
541 rdev_p->ctrl_qp.dma_addr);
542 rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
543 memset(rdev_p->ctrl_qp.workq, 0,
544 (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
545
546 mutex_init(&rdev_p->ctrl_qp.lock);
547 init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
548
549 /* update HW Ctrl QP context */
550 base_addr = rdev_p->ctrl_qp.dma_addr;
551 base_addr >>= 12;
552 ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
553 V_EC_BASE_LO((u32) base_addr & 0xffff));
554 ctx0 <<= 32;
555 ctx0 |= V_EC_CREDITS(FW_WR_NUM);
556 base_addr >>= 16;
557 ctx1 = (u32) base_addr;
558 base_addr >>= 32;
559 ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
560 V_EC_TYPE(0) | V_EC_GEN(1) |
561 V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
562 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
563 memset(wqe, 0, sizeof(*wqe));
564 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
565 T3_CTL_QP_TID, 7, T3_SOPEOP);
566 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
567 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
568 wqe->sge_cmd = cpu_to_be64(sge_cmd);
569 wqe->ctx1 = cpu_to_be64(ctx1);
570 wqe->ctx0 = cpu_to_be64(ctx0);
571 PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
572 (unsigned long long) rdev_p->ctrl_qp.dma_addr,
573 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
574 skb->priority = CPL_PRIORITY_CONTROL;
575 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
576 err:
577 kfree_skb(skb);
578 return err;
579 }
580
581 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
582 {
583 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
584 (1UL << T3_CTRL_QP_SIZE_LOG2)
585 * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
586 pci_unmap_addr(&rdev_p->ctrl_qp, mapping));
587 return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
588 }
589
590 /* write len bytes of data into addr (32B aligned address)
591 * If data is NULL, clear len byte of memory to zero.
592 * caller aquires the ctrl_qp lock before the call
593 */
594 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
595 u32 len, void *data)
596 {
597 u32 i, nr_wqe, copy_len;
598 u8 *copy_data;
599 u8 wr_len, utx_len; /* length in 8 byte flit */
600 enum t3_wr_flags flag;
601 __be64 *wqe;
602 u64 utx_cmd;
603 addr &= 0x7FFFFFF;
604 nr_wqe = len % 96 ? len / 96 + 1 : len / 96; /* 96B max per WQE */
605 PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
606 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
607 nr_wqe, data, addr);
608 utx_len = 3; /* in 32B unit */
609 for (i = 0; i < nr_wqe; i++) {
610 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
611 T3_CTRL_QP_SIZE_LOG2)) {
612 PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
613 "wait for more space i %d\n", __func__,
614 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
615 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
616 !Q_FULL(rdev_p->ctrl_qp.rptr,
617 rdev_p->ctrl_qp.wptr,
618 T3_CTRL_QP_SIZE_LOG2))) {
619 PDBG("%s ctrl_qp workq interrupted\n",
620 __func__);
621 return -ERESTARTSYS;
622 }
623 PDBG("%s ctrl_qp wakeup, continue posting work request "
624 "i %d\n", __func__, i);
625 }
626 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
627 (1 << T3_CTRL_QP_SIZE_LOG2)));
628 flag = 0;
629 if (i == (nr_wqe - 1)) {
630 /* last WQE */
631 flag = T3_COMPLETION_FLAG;
632 if (len % 32)
633 utx_len = len / 32 + 1;
634 else
635 utx_len = len / 32;
636 }
637
638 /*
639 * Force a CQE to return the credit to the workq in case
640 * we posted more than half the max QP size of WRs
641 */
642 if ((i != 0) &&
643 (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
644 flag = T3_COMPLETION_FLAG;
645 PDBG("%s force completion at i %d\n", __func__, i);
646 }
647
648 /* build the utx mem command */
649 wqe += (sizeof(struct t3_bypass_wr) >> 3);
650 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
651 utx_cmd <<= 32;
652 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
653 *wqe = cpu_to_be64(utx_cmd);
654 wqe++;
655 copy_data = (u8 *) data + i * 96;
656 copy_len = len > 96 ? 96 : len;
657
658 /* clear memory content if data is NULL */
659 if (data)
660 memcpy(wqe, copy_data, copy_len);
661 else
662 memset(wqe, 0, copy_len);
663 if (copy_len % 32)
664 memset(((u8 *) wqe) + copy_len, 0,
665 32 - (copy_len % 32));
666 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
667 (utx_len << 2);
668 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
669 (1 << T3_CTRL_QP_SIZE_LOG2)));
670
671 /* wptr in the WRID[31:0] */
672 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
673
674 /*
675 * This must be the last write with a memory barrier
676 * for the genbit
677 */
678 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
679 Q_GENBIT(rdev_p->ctrl_qp.wptr,
680 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
681 wr_len, T3_SOPEOP);
682 if (flag == T3_COMPLETION_FLAG)
683 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
684 len -= 96;
685 rdev_p->ctrl_qp.wptr++;
686 }
687 return 0;
688 }
689
690 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
691 * OUT: stag index
692 * TBD: shared memory region support
693 */
694 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
695 u32 *stag, u8 stag_state, u32 pdid,
696 enum tpt_mem_type type, enum tpt_mem_perm perm,
697 u32 zbva, u64 to, u32 len, u8 page_size,
698 u32 pbl_size, u32 pbl_addr)
699 {
700 int err;
701 struct tpt_entry tpt;
702 u32 stag_idx;
703 u32 wptr;
704
705 if (cxio_fatal_error(rdev_p))
706 return -EIO;
707
708 stag_state = stag_state > 0;
709 stag_idx = (*stag) >> 8;
710
711 if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
712 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
713 if (!stag_idx)
714 return -ENOMEM;
715 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
716 }
717 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
718 __func__, stag_state, type, pdid, stag_idx);
719
720 mutex_lock(&rdev_p->ctrl_qp.lock);
721
722 /* write TPT entry */
723 if (reset_tpt_entry)
724 memset(&tpt, 0, sizeof(tpt));
725 else {
726 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
727 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
728 V_TPT_STAG_STATE(stag_state) |
729 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
730 BUG_ON(page_size >= 28);
731 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
732 ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
733 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
734 V_TPT_PAGE_SIZE(page_size));
735 tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 :
736 cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
737 tpt.len = cpu_to_be32(len);
738 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
739 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
740 tpt.rsvd_bind_cnt_or_pstag = 0;
741 tpt.rsvd_pbl_size = reset_tpt_entry ? 0 :
742 cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
743 }
744 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
745 stag_idx +
746 (rdev_p->rnic_info.tpt_base >> 5),
747 sizeof(tpt), &tpt);
748
749 /* release the stag index to free pool */
750 if (reset_tpt_entry)
751 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
752
753 wptr = rdev_p->ctrl_qp.wptr;
754 mutex_unlock(&rdev_p->ctrl_qp.lock);
755 if (!err)
756 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
757 SEQ32_GE(rdev_p->ctrl_qp.rptr,
758 wptr)))
759 return -ERESTARTSYS;
760 return err;
761 }
762
763 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
764 u32 pbl_addr, u32 pbl_size)
765 {
766 u32 wptr;
767 int err;
768
769 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
770 __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
771 pbl_size);
772
773 mutex_lock(&rdev_p->ctrl_qp.lock);
774 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
775 pbl);
776 wptr = rdev_p->ctrl_qp.wptr;
777 mutex_unlock(&rdev_p->ctrl_qp.lock);
778 if (err)
779 return err;
780
781 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
782 SEQ32_GE(rdev_p->ctrl_qp.rptr,
783 wptr)))
784 return -ERESTARTSYS;
785
786 return 0;
787 }
788
789 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
790 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
791 u8 page_size, u32 pbl_size, u32 pbl_addr)
792 {
793 *stag = T3_STAG_UNSET;
794 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
795 zbva, to, len, page_size, pbl_size, pbl_addr);
796 }
797
798 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
799 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
800 u8 page_size, u32 pbl_size, u32 pbl_addr)
801 {
802 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
803 zbva, to, len, page_size, pbl_size, pbl_addr);
804 }
805
806 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
807 u32 pbl_addr)
808 {
809 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
810 pbl_size, pbl_addr);
811 }
812
813 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
814 {
815 *stag = T3_STAG_UNSET;
816 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
817 0, 0);
818 }
819
820 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
821 {
822 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
823 0, 0);
824 }
825
826 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
827 {
828 *stag = T3_STAG_UNSET;
829 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
830 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
831 }
832
833 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
834 {
835 struct t3_rdma_init_wr *wqe;
836 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
837 if (!skb)
838 return -ENOMEM;
839 PDBG("%s rdev_p %p\n", __func__, rdev_p);
840 wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
841 wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
842 wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
843 V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
844 wqe->wrid.id1 = 0;
845 wqe->qpid = cpu_to_be32(attr->qpid);
846 wqe->pdid = cpu_to_be32(attr->pdid);
847 wqe->scqid = cpu_to_be32(attr->scqid);
848 wqe->rcqid = cpu_to_be32(attr->rcqid);
849 wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
850 wqe->rq_size = cpu_to_be32(attr->rq_size);
851 wqe->mpaattrs = attr->mpaattrs;
852 wqe->qpcaps = attr->qpcaps;
853 wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
854 wqe->rqe_count = cpu_to_be16(attr->rqe_count);
855 wqe->flags_rtr_type = cpu_to_be16(attr->flags |
856 V_RTR_TYPE(attr->rtr_type) |
857 V_CHAN(attr->chan));
858 wqe->ord = cpu_to_be32(attr->ord);
859 wqe->ird = cpu_to_be32(attr->ird);
860 wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
861 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
862 wqe->irs = cpu_to_be32(attr->irs);
863 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
864 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
865 }
866
867 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
868 {
869 cxio_ev_cb = ev_cb;
870 }
871
872 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
873 {
874 cxio_ev_cb = NULL;
875 }
876
877 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
878 {
879 static int cnt;
880 struct cxio_rdev *rdev_p = NULL;
881 struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
882 PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
883 " se %0x notify %0x cqbranch %0x creditth %0x\n",
884 cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
885 RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
886 RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
887 RSPQ_CREDIT_THRESH(rsp_msg));
888 PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
889 "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
890 CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
891 CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
892 CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
893 CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
894 rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
895 if (!rdev_p) {
896 PDBG("%s called by t3cdev %p with null ulp\n", __func__,
897 t3cdev_p);
898 return 0;
899 }
900 if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
901 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
902 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
903 dev_kfree_skb_irq(skb);
904 } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
905 dev_kfree_skb_irq(skb);
906 else if (cxio_ev_cb)
907 (*cxio_ev_cb) (rdev_p, skb);
908 else
909 dev_kfree_skb_irq(skb);
910 cnt++;
911 return 0;
912 }
913
914 /* Caller takes care of locking if needed */
915 int cxio_rdev_open(struct cxio_rdev *rdev_p)
916 {
917 struct net_device *netdev_p = NULL;
918 int err = 0;
919 if (strlen(rdev_p->dev_name)) {
920 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
921 return -EBUSY;
922 }
923 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
924 if (!netdev_p) {
925 return -EINVAL;
926 }
927 dev_put(netdev_p);
928 } else if (rdev_p->t3cdev_p) {
929 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
930 return -EBUSY;
931 }
932 netdev_p = rdev_p->t3cdev_p->lldev;
933 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
934 T3_MAX_DEV_NAME_LEN);
935 } else {
936 PDBG("%s t3cdev_p or dev_name must be set\n", __func__);
937 return -EINVAL;
938 }
939
940 list_add_tail(&rdev_p->entry, &rdev_list);
941
942 PDBG("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
943 memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
944 if (!rdev_p->t3cdev_p)
945 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
946 rdev_p->t3cdev_p->ulp = (void *) rdev_p;
947
948 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
949 &(rdev_p->fw_info));
950 if (err) {
951 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
952 __func__, rdev_p->t3cdev_p, err);
953 goto err1;
954 }
955 if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
956 printk(KERN_ERR MOD "fatal firmware version mismatch: "
957 "need version %u but adapter has version %u\n",
958 CXIO_FW_MAJ,
959 G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
960 err = -EINVAL;
961 goto err1;
962 }
963
964 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
965 &(rdev_p->rnic_info));
966 if (err) {
967 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
968 __func__, rdev_p->t3cdev_p, err);
969 goto err1;
970 }
971 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
972 &(rdev_p->port_info));
973 if (err) {
974 printk(KERN_ERR "%s t3cdev_p(%p)->ctl returned error %d.\n",
975 __func__, rdev_p->t3cdev_p, err);
976 goto err1;
977 }
978
979 /*
980 * qpshift is the number of bits to shift the qpid left in order
981 * to get the correct address of the doorbell for that qp.
982 */
983 cxio_init_ucontext(rdev_p, &rdev_p->uctx);
984 rdev_p->qpshift = PAGE_SHIFT -
985 ilog2(65536 >>
986 ilog2(rdev_p->rnic_info.udbell_len >>
987 PAGE_SHIFT));
988 rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
989 rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
990 PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
991 "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
992 __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
993 rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
994 rdev_p->rnic_info.pbl_base,
995 rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
996 rdev_p->rnic_info.rqt_top);
997 PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
998 "qpnr %d qpmask 0x%x\n",
999 rdev_p->rnic_info.udbell_len,
1000 rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
1001 rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
1002
1003 err = cxio_hal_init_ctrl_qp(rdev_p);
1004 if (err) {
1005 printk(KERN_ERR "%s error %d initializing ctrl_qp.\n",
1006 __func__, err);
1007 goto err1;
1008 }
1009 err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1010 0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1011 T3_MAX_NUM_PD);
1012 if (err) {
1013 printk(KERN_ERR "%s error %d initializing hal resources.\n",
1014 __func__, err);
1015 goto err2;
1016 }
1017 err = cxio_hal_pblpool_create(rdev_p);
1018 if (err) {
1019 printk(KERN_ERR "%s error %d initializing pbl mem pool.\n",
1020 __func__, err);
1021 goto err3;
1022 }
1023 err = cxio_hal_rqtpool_create(rdev_p);
1024 if (err) {
1025 printk(KERN_ERR "%s error %d initializing rqt mem pool.\n",
1026 __func__, err);
1027 goto err4;
1028 }
1029 return 0;
1030 err4:
1031 cxio_hal_pblpool_destroy(rdev_p);
1032 err3:
1033 cxio_hal_destroy_resource(rdev_p->rscp);
1034 err2:
1035 cxio_hal_destroy_ctrl_qp(rdev_p);
1036 err1:
1037 rdev_p->t3cdev_p->ulp = NULL;
1038 list_del(&rdev_p->entry);
1039 return err;
1040 }
1041
1042 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1043 {
1044 if (rdev_p) {
1045 cxio_hal_pblpool_destroy(rdev_p);
1046 cxio_hal_rqtpool_destroy(rdev_p);
1047 list_del(&rdev_p->entry);
1048 cxio_hal_destroy_ctrl_qp(rdev_p);
1049 cxio_hal_destroy_resource(rdev_p->rscp);
1050 rdev_p->t3cdev_p->ulp = NULL;
1051 }
1052 }
1053
1054 int __init cxio_hal_init(void)
1055 {
1056 if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1057 return -ENOMEM;
1058 t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1059 return 0;
1060 }
1061
1062 void __exit cxio_hal_exit(void)
1063 {
1064 struct cxio_rdev *rdev, *tmp;
1065
1066 t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1067 list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1068 cxio_rdev_close(rdev);
1069 cxio_hal_destroy_rhdl_resource();
1070 }
1071
1072 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1073 {
1074 struct t3_swsq *sqp;
1075 __u32 ptr = wq->sq_rptr;
1076 int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1077
1078 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1079 while (count--)
1080 if (!sqp->signaled) {
1081 ptr++;
1082 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1083 } else if (sqp->complete) {
1084
1085 /*
1086 * Insert this completed cqe into the swcq.
1087 */
1088 PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1089 __func__, Q_PTR2IDX(ptr, wq->sq_size_log2),
1090 Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1091 sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1092 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1093 = sqp->cqe;
1094 cq->sw_wptr++;
1095 sqp->signaled = 0;
1096 break;
1097 } else
1098 break;
1099 }
1100
1101 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1102 struct t3_cqe *read_cqe)
1103 {
1104 read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1105 read_cqe->len = wq->oldest_read->read_len;
1106 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1107 V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1108 V_CQE_OPCODE(T3_READ_REQ) |
1109 V_CQE_TYPE(1));
1110 }
1111
1112 /*
1113 * Return a ptr to the next read wr in the SWSQ or NULL.
1114 */
1115 static void advance_oldest_read(struct t3_wq *wq)
1116 {
1117
1118 u32 rptr = wq->oldest_read - wq->sq + 1;
1119 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1120
1121 while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1122 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1123
1124 if (wq->oldest_read->opcode == T3_READ_REQ)
1125 return;
1126 rptr++;
1127 }
1128 wq->oldest_read = NULL;
1129 }
1130
1131 /*
1132 * cxio_poll_cq
1133 *
1134 * Caller must:
1135 * check the validity of the first CQE,
1136 * supply the wq assicated with the qpid.
1137 *
1138 * credit: cq credit to return to sge.
1139 * cqe_flushed: 1 iff the CQE is flushed.
1140 * cqe: copy of the polled CQE.
1141 *
1142 * return value:
1143 * 0 CQE returned,
1144 * -1 CQE skipped, try again.
1145 */
1146 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1147 u8 *cqe_flushed, u64 *cookie, u32 *credit)
1148 {
1149 int ret = 0;
1150 struct t3_cqe *hw_cqe, read_cqe;
1151
1152 *cqe_flushed = 0;
1153 *credit = 0;
1154 hw_cqe = cxio_next_cqe(cq);
1155
1156 PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1157 " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1158 __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1159 CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1160 CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1161 CQE_WRID_LOW(*hw_cqe));
1162
1163 /*
1164 * skip cqe's not affiliated with a QP.
1165 */
1166 if (wq == NULL) {
1167 ret = -1;
1168 goto skip_cqe;
1169 }
1170
1171 /*
1172 * Gotta tweak READ completions:
1173 * 1) the cqe doesn't contain the sq_wptr from the wr.
1174 * 2) opcode not reflected from the wr.
1175 * 3) read_len not reflected from the wr.
1176 * 4) cq_type is RQ_TYPE not SQ_TYPE.
1177 */
1178 if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1179
1180 /*
1181 * If this is an unsolicited read response, then the read
1182 * was generated by the kernel driver as part of peer-2-peer
1183 * connection setup. So ignore the completion.
1184 */
1185 if (!wq->oldest_read) {
1186 if (CQE_STATUS(*hw_cqe))
1187 wq->error = 1;
1188 ret = -1;
1189 goto skip_cqe;
1190 }
1191
1192 /*
1193 * Don't write to the HWCQ, so create a new read req CQE
1194 * in local memory.
1195 */
1196 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1197 hw_cqe = &read_cqe;
1198 advance_oldest_read(wq);
1199 }
1200
1201 /*
1202 * T3A: Discard TERMINATE CQEs.
1203 */
1204 if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1205 ret = -1;
1206 wq->error = 1;
1207 goto skip_cqe;
1208 }
1209
1210 if (CQE_STATUS(*hw_cqe) || wq->error) {
1211 *cqe_flushed = wq->error;
1212 wq->error = 1;
1213
1214 /*
1215 * T3A inserts errors into the CQE. We cannot return
1216 * these as work completions.
1217 */
1218 /* incoming write failures */
1219 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1220 && RQ_TYPE(*hw_cqe)) {
1221 ret = -1;
1222 goto skip_cqe;
1223 }
1224 /* incoming read request failures */
1225 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1226 ret = -1;
1227 goto skip_cqe;
1228 }
1229
1230 /* incoming SEND with no receive posted failures */
1231 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1232 Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1233 ret = -1;
1234 goto skip_cqe;
1235 }
1236 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1237 goto proc_cqe;
1238 }
1239
1240 /*
1241 * RECV completion.
1242 */
1243 if (RQ_TYPE(*hw_cqe)) {
1244
1245 /*
1246 * HW only validates 4 bits of MSN. So we must validate that
1247 * the MSN in the SEND is the next expected MSN. If its not,
1248 * then we complete this with TPT_ERR_MSN and mark the wq in
1249 * error.
1250 */
1251
1252 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1253 wq->error = 1;
1254 ret = -1;
1255 goto skip_cqe;
1256 }
1257
1258 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1259 wq->error = 1;
1260 hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1261 goto proc_cqe;
1262 }
1263 goto proc_cqe;
1264 }
1265
1266 /*
1267 * If we get here its a send completion.
1268 *
1269 * Handle out of order completion. These get stuffed
1270 * in the SW SQ. Then the SW SQ is walked to move any
1271 * now in-order completions into the SW CQ. This handles
1272 * 2 cases:
1273 * 1) reaping unsignaled WRs when the first subsequent
1274 * signaled WR is completed.
1275 * 2) out of order read completions.
1276 */
1277 if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1278 struct t3_swsq *sqp;
1279
1280 PDBG("%s out of order completion going in swsq at idx %ld\n",
1281 __func__,
1282 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2));
1283 sqp = wq->sq +
1284 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1285 sqp->cqe = *hw_cqe;
1286 sqp->complete = 1;
1287 ret = -1;
1288 goto flush_wq;
1289 }
1290
1291 proc_cqe:
1292 *cqe = *hw_cqe;
1293
1294 /*
1295 * Reap the associated WR(s) that are freed up with this
1296 * completion.
1297 */
1298 if (SQ_TYPE(*hw_cqe)) {
1299 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1300 PDBG("%s completing sq idx %ld\n", __func__,
1301 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1302 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1303 wq->sq_rptr++;
1304 } else {
1305 PDBG("%s completing rq idx %ld\n", __func__,
1306 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1307 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1308 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1309 cxio_hal_pblpool_free(wq->rdev,
1310 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1311 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1312 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1313 wq->rq_rptr++;
1314 }
1315
1316 flush_wq:
1317 /*
1318 * Flush any completed cqes that are now in-order.
1319 */
1320 flush_completed_wrs(wq, cq);
1321
1322 skip_cqe:
1323 if (SW_CQE(*hw_cqe)) {
1324 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1325 __func__, cq, cq->cqid, cq->sw_rptr);
1326 ++cq->sw_rptr;
1327 } else {
1328 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1329 __func__, cq, cq->cqid, cq->rptr);
1330 ++cq->rptr;
1331
1332 /*
1333 * T3A: compute credits.
1334 */
1335 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1336 || ((cq->rptr - cq->wptr) >= 128)) {
1337 *credit = cq->rptr - cq->wptr;
1338 cq->wptr = cq->rptr;
1339 }
1340 }
1341 return ret;
1342 }
Linux with added FPC-III support