x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / drivers / infiniband / hw / cxgb3 / iwch_mem.c
blobe1ec65ebb016e4c7cfbfe81ca1e2095ba614ce08
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
32 #include <asm/byteorder.h>
34 #include <rdma/iw_cm.h>
35 #include <rdma/ib_verbs.h>
37 #include "cxio_hal.h"
38 #include "cxio_resource.h"
39 #include "iwch.h"
40 #include "iwch_provider.h"
42 static int iwch_finish_mem_reg(struct iwch_mr *mhp, u32 stag)
44 u32 mmid;
46 mhp->attr.state = 1;
47 mhp->attr.stag = stag;
48 mmid = stag >> 8;
49 mhp->ibmr.rkey = mhp->ibmr.lkey = stag;
50 PDBG("%s mmid 0x%x mhp %p\n", __func__, mmid, mhp);
51 return insert_handle(mhp->rhp, &mhp->rhp->mmidr, mhp, mmid);
54 int iwch_register_mem(struct iwch_dev *rhp, struct iwch_pd *php,
55 struct iwch_mr *mhp, int shift)
57 u32 stag;
58 int ret;
60 if (cxio_register_phys_mem(&rhp->rdev,
61 &stag, mhp->attr.pdid,
62 mhp->attr.perms,
63 mhp->attr.zbva,
64 mhp->attr.va_fbo,
65 mhp->attr.len,
66 shift - 12,
67 mhp->attr.pbl_size, mhp->attr.pbl_addr))
68 return -ENOMEM;
70 ret = iwch_finish_mem_reg(mhp, stag);
71 if (ret)
72 cxio_dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
73 mhp->attr.pbl_addr);
74 return ret;
77 int iwch_reregister_mem(struct iwch_dev *rhp, struct iwch_pd *php,
78 struct iwch_mr *mhp,
79 int shift,
80 int npages)
82 u32 stag;
83 int ret;
85 /* We could support this... */
86 if (npages > mhp->attr.pbl_size)
87 return -ENOMEM;
89 stag = mhp->attr.stag;
90 if (cxio_reregister_phys_mem(&rhp->rdev,
91 &stag, mhp->attr.pdid,
92 mhp->attr.perms,
93 mhp->attr.zbva,
94 mhp->attr.va_fbo,
95 mhp->attr.len,
96 shift - 12,
97 mhp->attr.pbl_size, mhp->attr.pbl_addr))
98 return -ENOMEM;
100 ret = iwch_finish_mem_reg(mhp, stag);
101 if (ret)
102 cxio_dereg_mem(&rhp->rdev, mhp->attr.stag, mhp->attr.pbl_size,
103 mhp->attr.pbl_addr);
105 return ret;
108 int iwch_alloc_pbl(struct iwch_mr *mhp, int npages)
110 mhp->attr.pbl_addr = cxio_hal_pblpool_alloc(&mhp->rhp->rdev,
111 npages << 3);
113 if (!mhp->attr.pbl_addr)
114 return -ENOMEM;
116 mhp->attr.pbl_size = npages;
118 return 0;
121 void iwch_free_pbl(struct iwch_mr *mhp)
123 cxio_hal_pblpool_free(&mhp->rhp->rdev, mhp->attr.pbl_addr,
124 mhp->attr.pbl_size << 3);
127 int iwch_write_pbl(struct iwch_mr *mhp, __be64 *pages, int npages, int offset)
129 return cxio_write_pbl(&mhp->rhp->rdev, pages,
130 mhp->attr.pbl_addr + (offset << 3), npages);
133 int build_phys_page_list(struct ib_phys_buf *buffer_list,
134 int num_phys_buf,
135 u64 *iova_start,
136 u64 *total_size,
137 int *npages,
138 int *shift,
139 __be64 **page_list)
141 u64 mask;
142 int i, j, n;
144 mask = 0;
145 *total_size = 0;
146 for (i = 0; i < num_phys_buf; ++i) {
147 if (i != 0 && buffer_list[i].addr & ~PAGE_MASK)
148 return -EINVAL;
149 if (i != 0 && i != num_phys_buf - 1 &&
150 (buffer_list[i].size & ~PAGE_MASK))
151 return -EINVAL;
152 *total_size += buffer_list[i].size;
153 if (i > 0)
154 mask |= buffer_list[i].addr;
155 else
156 mask |= buffer_list[i].addr & PAGE_MASK;
157 if (i != num_phys_buf - 1)
158 mask |= buffer_list[i].addr + buffer_list[i].size;
159 else
160 mask |= (buffer_list[i].addr + buffer_list[i].size +
161 PAGE_SIZE - 1) & PAGE_MASK;
164 if (*total_size > 0xFFFFFFFFULL)
165 return -ENOMEM;
167 /* Find largest page shift we can use to cover buffers */
168 for (*shift = PAGE_SHIFT; *shift < 27; ++(*shift))
169 if ((1ULL << *shift) & mask)
170 break;
172 buffer_list[0].size += buffer_list[0].addr & ((1ULL << *shift) - 1);
173 buffer_list[0].addr &= ~0ull << *shift;
175 *npages = 0;
176 for (i = 0; i < num_phys_buf; ++i)
177 *npages += (buffer_list[i].size +
178 (1ULL << *shift) - 1) >> *shift;
180 if (!*npages)
181 return -EINVAL;
183 *page_list = kmalloc(sizeof(u64) * *npages, GFP_KERNEL);
184 if (!*page_list)
185 return -ENOMEM;
187 n = 0;
188 for (i = 0; i < num_phys_buf; ++i)
189 for (j = 0;
190 j < (buffer_list[i].size + (1ULL << *shift) - 1) >> *shift;
191 ++j)
192 (*page_list)[n++] = cpu_to_be64(buffer_list[i].addr +
193 ((u64) j << *shift));
195 PDBG("%s va 0x%llx mask 0x%llx shift %d len %lld pbl_size %d\n",
196 __func__, (unsigned long long) *iova_start,
197 (unsigned long long) mask, *shift, (unsigned long long) *total_size,
198 *npages);
200 return 0;