drivers/isdn/hardware/eicon/mi_pc.h

   1
   2 /*
   3  *
   4   Copyright (c) Eicon Networks, 2002.
   5  *
   6   This source file is supplied for the use with
   7   Eicon Networks range of DIVA Server Adapters.
   8  *
   9   Eicon File Revision :    2.1
  10  *
  11   This program is free software; you can redistribute it and/or modify
  12   it under the terms of the GNU General Public License as published by
  13   the Free Software Foundation; either version 2, or (at your option)
  14   any later version.
  15  *
  16   This program is distributed in the hope that it will be useful,
  17   but WITHOUT ANY WARRANTY OF ANY KIND WHATSOEVER INCLUDING ANY
  18   implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  19   See the GNU General Public License for more details.
  20  *
  21   You should have received a copy of the GNU General Public License
  22   along with this program; if not, write to the Free Software
  23   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  *
  25  */
  26 /*----------------------------------------------------------------------------
  27 // MAESTRA ISA PnP */
  28 #define BRI_MEMORY_BASE                 0x1f700000
  29 #define BRI_MEMORY_SIZE                 0x00100000  /* 1MB on the BRI                         */
  30 #define BRI_SHARED_RAM_SIZE             0x00010000  /* 64k shared RAM                         */
  31 #define BRI_RAY_TAYLOR_DSP_CODE_SIZE    0x00020000  /* max 128k DSP-Code (Ray Taylor's code)  */
  32 #define BRI_ORG_MAX_DSP_CODE_SIZE       0x00050000  /* max 320k DSP-Code (Telindus)           */
  33 #define BRI_V90D_MAX_DSP_CODE_SIZE      0x00060000  /* max 384k DSP-Code if V.90D included    */
  34 #define BRI_CACHED_ADDR(x)              (((x) & 0x1fffffffL) | 0x80000000L)
  35 #define BRI_UNCACHED_ADDR(x)            (((x) & 0x1fffffffL) | 0xa0000000L)
  36 #define ADDR  4
  37 #define ADDRH 6
  38 #define DATA  0
  39 #define RESET 7
  40 #define DEFAULT_ADDRESS 0x240
  41 #define DEFAULT_IRQ     3
  42 #define M_PCI_ADDR   0x04  /* MAESTRA BRI PCI */
  43 #define M_PCI_ADDRH  0x0c  /* MAESTRA BRI PCI */
  44 #define M_PCI_DATA   0x00  /* MAESTRA BRI PCI */
  45 #define M_PCI_RESET  0x10  /* MAESTRA BRI PCI */
  46 /*----------------------------------------------------------------------------
  47 // MAESTRA PRI PCI */
  48 #define MP_IRQ_RESET                    0xc18       /* offset of isr in the CONFIG memory bar */
  49 #define MP_IRQ_RESET_VAL                0xfe        /* value to clear an interrupt            */
  50 #define MP_MEMORY_SIZE                  0x00400000  /* 4MB on standard PRI                    */
  51 #define MP2_MEMORY_SIZE                 0x00800000  /* 8MB on PRI Rev. 2                      */
  52 #define MP_SHARED_RAM_OFFSET            0x00001000  /* offset of shared RAM base in the DRAM memory bar */
  53 #define MP_SHARED_RAM_SIZE              0x00010000  /* 64k shared RAM                         */
  54 #define MP_PROTOCOL_OFFSET              (MP_SHARED_RAM_OFFSET + MP_SHARED_RAM_SIZE)
  55 #define MP_RAY_TAYLOR_DSP_CODE_SIZE     0x00040000  /* max 256k DSP-Code (Ray Taylor's code)  */
  56 #define MP_ORG_MAX_DSP_CODE_SIZE        0x00060000  /* max 384k DSP-Code (Telindus)           */
  57 #define MP_V90D_MAX_DSP_CODE_SIZE       0x00070000  /* max 448k DSP-Code if V.90D included)   */
  58 #define MP_VOIP_MAX_DSP_CODE_SIZE       0x00090000  /* max 576k DSP-Code if voice over IP included */
  59 #define MP_CACHED_ADDR(x)               (((x) & 0x1fffffffL) | 0x80000000L)
  60 #define MP_UNCACHED_ADDR(x)             (((x) & 0x1fffffffL) | 0xa0000000L)
  61 #define MP_RESET         0x20        /* offset of RESET register in the DEVICES memory bar */
  62 /* RESET register bits */
  63 #define _MP_S2M_RESET    0x10        /* active lo   */
  64 #define _MP_LED2         0x08        /* 1 = on      */
  65 #define _MP_LED1         0x04        /* 1 = on      */
  66 #define _MP_DSP_RESET    0x02        /* active lo   */
  67 #define _MP_RISC_RESET   0x81        /* active hi, bit 7 for compatibility with old boards */
  68 /* CPU exception context structure in MP shared ram after trap */
  69 typedef struct mp_xcptcontext_s MP_XCPTC;
  70 struct mp_xcptcontext_s {
  71     dword       sr;
  72     dword       cr;
  73     dword       epc;
  74     dword       vaddr;
  75     dword       regs[32];
  76     dword       mdlo;
  77     dword       mdhi;
  78     dword       reseverd;
  79     dword       xclass;
  80 };
  81 /* boot interface structure for PRI */
  82 struct mp_load {
  83   dword     volatile cmd;
  84   dword     volatile addr;
  85   dword     volatile len;
  86   dword     volatile err;
  87   dword     volatile live;
  88   dword     volatile res1[0x1b];
  89   dword     volatile TrapId;    /* has value 0x999999XX on a CPU trap */
  90   dword     volatile res2[0x03];
  91   MP_XCPTC  volatile xcpt;      /* contains register dump */
  92   dword     volatile rest[((0x1020>>2)-6) - 0x1b - 1 - 0x03 - (sizeof(MP_XCPTC)>>2)];
  93   dword     volatile signature;
  94   dword data[60000]; /* real interface description */
  95 };
  96 /*----------------------------------------------------------------------------*/
  97 /* SERVER 4BRI (Quattro PCI)                                                  */
  98 #define MQ_BOARD_REG_OFFSET             0x800000    /* PC relative On board registers offset  */
  99 #define MQ_BREG_RISC                    0x1200      /* RISC Reset ect                         */
 100 #define MQ_RISC_COLD_RESET_MASK         0x0001      /* RISC Cold reset                        */
 101 #define MQ_RISC_WARM_RESET_MASK         0x0002      /* RISC Warm reset                        */
 102 #define MQ_BREG_IRQ_TEST                0x0608      /* Interrupt request, no CPU interaction  */
 103 #define MQ_IRQ_REQ_ON                   0x1
 104 #define MQ_IRQ_REQ_OFF                  0x0
 105 #define MQ_BOARD_DSP_OFFSET             0xa00000    /* PC relative On board DSP regs offset   */
 106 #define MQ_DSP1_ADDR_OFFSET             0x0008      /* Addr register offset DSP 1 subboard 1  */
 107 #define MQ_DSP2_ADDR_OFFSET             0x0208      /* Addr register offset DSP 2 subboard 1  */
 108 #define MQ_DSP1_DATA_OFFSET             0x0000      /* Data register offset DSP 1 subboard 1  */
 109 #define MQ_DSP2_DATA_OFFSET             0x0200      /* Data register offset DSP 2 subboard 1  */
 110 #define MQ_DSP_JUNK_OFFSET              0x0400      /* DSP Data/Addr regs subboard offset     */
 111 #define MQ_ISAC_DSP_RESET               0x0028      /* ISAC and DSP reset address offset      */
 112 #define MQ_BOARD_ISAC_DSP_RESET         0x800028    /* ISAC and DSP reset address offset      */
 113 #define MQ_INSTANCE_COUNT               4           /* 4BRI consists of four instances        */
 114 #define MQ_MEMORY_SIZE                  0x00400000  /* 4MB on standard 4BRI                   */
 115 #define MQ_CTRL_SIZE                    0x00002000  /* 8K memory mapped registers             */
 116 #define MQ_SHARED_RAM_SIZE              0x00010000  /* 64k shared RAM                         */
 117 #define MQ_ORG_MAX_DSP_CODE_SIZE        0x00050000  /* max 320k DSP-Code (Telindus) */
 118 #define MQ_V90D_MAX_DSP_CODE_SIZE       0x00060000  /* max 384K DSP-Code if V.90D included */
 119 #define MQ_VOIP_MAX_DSP_CODE_SIZE       0x00028000  /* max 4*160k = 640K DSP-Code if voice over IP included */
 120 #define MQ_CACHED_ADDR(x)               (((x) & 0x1fffffffL) | 0x80000000L)
 121 #define MQ_UNCACHED_ADDR(x)             (((x) & 0x1fffffffL) | 0xa0000000L)
 122 /*--------------------------------------------------------------------------------------------*/
 123 /* Additional definitions reflecting the different address map of the  SERVER 4BRI V2          */
 124 #define MQ2_BREG_RISC                   0x0200      /* RISC Reset ect                         */
 125 #define MQ2_BREG_IRQ_TEST               0x0400      /* Interrupt request, no CPU interaction  */
 126 #define MQ2_BOARD_DSP_OFFSET            0x800000    /* PC relative On board DSP regs offset   */
 127 #define MQ2_DSP1_DATA_OFFSET            0x1800      /* Data register offset DSP 1 subboard 1  */
 128 #define MQ2_DSP1_ADDR_OFFSET            0x1808      /* Addr register offset DSP 1 subboard 1  */
 129 #define MQ2_DSP2_DATA_OFFSET            0x1810      /* Data register offset DSP 2 subboard 1  */
 130 #define MQ2_DSP2_ADDR_OFFSET            0x1818      /* Addr register offset DSP 2 subboard 1  */
 131 #define MQ2_DSP_JUNK_OFFSET             0x1000      /* DSP Data/Addr regs subboard offset     */
 132 #define MQ2_ISAC_DSP_RESET              0x0000      /* ISAC and DSP reset address offset      */
 133 #define MQ2_BOARD_ISAC_DSP_RESET        0x800000    /* ISAC and DSP reset address offset      */
 134 #define MQ2_IPACX_CONFIG                0x0300      /* IPACX Configuration TE(0)/NT(1)        */
 135 #define MQ2_BOARD_IPACX_CONFIG          0x800300    /*     ""                                 */
 136 #define MQ2_MEMORY_SIZE                 0x01000000  /* 16MB code/data memory                  */
 137 #define MQ2_CTRL_SIZE                   0x00008000  /* 32K memory mapped registers            */
 138 /*----------------------------------------------------------------------------*/
 139 /* SERVER BRI 2M/2F as derived from 4BRI V2                                   */
 140 #define BRI2_MEMORY_SIZE                0x00800000  /* 8MB code/data memory                   */
 141 #define BRI2_PROTOCOL_MEMORY_SIZE       (MQ2_MEMORY_SIZE >> 2) /*  same as one 4BRI Rev.2 task */
 142 #define BRI2_CTRL_SIZE                  0x00008000  /* 32K memory mapped registers            */
 143 #define M_INSTANCE_COUNT                1           /*  BRI consists of one instance          */
 144 /*
 145  * Some useful constants for proper initialization of the GT6401x
 146  */
 147 #define ID_REG        0x0000      /*Pci reg-contain the Dev&Ven ID of the card*/
 148 #define RAS0_BASEREG  0x0010      /*Ras0 register - contain the base addr Ras0*/
 149 #define RAS2_BASEREG  0x0014
 150 #define CS_BASEREG    0x0018
 151 #define BOOT_BASEREG  0x001c
 152 #define GTREGS_BASEREG 0x0024   /*GTRegsBase reg-contain the base addr where*/
 153                                 /*the GT64010 internal regs where mapped    */
 154 /*
 155  *  GT64010 internal registers
 156  */
 157         /* DRAM device coding  */
 158 #define LOW_RAS0_DREG 0x0400    /*Ras0 low decode address*/
 159 #define HI_RAS0_DREG  0x0404    /*Ras0 high decode address*/
 160 #define LOW_RAS1_DREG 0x0408    /*Ras1 low decode address*/
 161 #define HI_RAS1_DREG  0x040c    /*Ras1 high decode address*/
 162 #define LOW_RAS2_DREG 0x0410    /*Ras2 low decode address*/
 163 #define HI_RAS2_DREG  0x0414    /*Ras2 high decode address*/
 164 #define LOW_RAS3_DREG 0x0418    /*Ras3 low decode address*/
 165 #define HI_RAS3_DREG  0x041c    /*Ras3 high decode address*/
 166         /* I/O CS device coding  */
 167 #define LOW_CS0_DREG  0x0420 /* CS0* low decode register */
 168 #define HI_CS0_DREG   0x0424 /* CS0* high decode register */
 169 #define LOW_CS1_DREG  0x0428 /* CS1* low decode register */
 170 #define HI_CS1_DREG   0x042c /* CS1* high decode register */
 171 #define LOW_CS2_DREG  0x0430 /* CS2* low decode register */
 172 #define HI_CS2_DREG   0x0434 /* CS2* high decode register */
 173 #define LOW_CS3_DREG  0x0438 /* CS3* low decode register */
 174 #define HI_CS3_DREG   0x043c /* CS3* high decode register */
 175         /* Boot PROM device coding */
 176 #define LOW_BOOTCS_DREG 0x0440 /* Boot CS low decode register */
 177 #define HI_BOOTCS_DREG 0x0444 /* Boot CS High decode register */
 178         /* DRAM group coding (for CPU)  */
 179 #define LO_RAS10_GREG 0x0008    /*Ras1..0 group low decode address*/
 180 #define HI_RAS10_GREG 0x0010    /*Ras1..0 group high decode address*/
 181 #define LO_RAS32_GREG 0x0018    /*Ras3..2 group low decode address  */
 182 #define HI_RAS32_GREG 0x0020    /*Ras3..2 group high decode address  */
 183         /* I/O CS group coding for (CPU)  */
 184 #define LO_CS20_GREG  0x0028 /* CS2..0 group low decode register */
 185 #define HI_CS20_GREG  0x0030 /* CS2..0 group high decode register */
 186 #define LO_CS3B_GREG  0x0038 /* CS3 & PROM group low decode register */
 187 #define HI_CS3B_GREG  0x0040 /* CS3 & PROM group high decode register */
 188         /* Galileo specific PCI config. */
 189 #define PCI_TIMEOUT_RET 0x0c04 /* Time Out and retry register */
 190 #define RAS10_BANKSIZE 0x0c08 /* RAS 1..0 group PCI bank size */
 191 #define RAS32_BANKSIZE 0x0c0c /* RAS 3..2 group PCI bank size */
 192 #define CS20_BANKSIZE 0x0c10 /* CS 2..0 group PCI bank size */
 193 #define CS3B_BANKSIZE 0x0c14 /* CS 3 & Boot group PCI bank size */
 194 #define DRAM_SIZE     0x0001      /*Dram size in mega bytes*/
 195 #define PROM_SIZE     0x08000     /*Prom size in bytes*/
 196 /*--------------------------------------------------------------------------*/
 197 #define OFFS_DIVA_INIT_TASK_COUNT 0x68
 198 #define OFFS_DSP_CODE_BASE_ADDR   0x6c
 199 #define OFFS_XLOG_BUF_ADDR        0x70
 200 #define OFFS_XLOG_COUNT_ADDR      0x74
 201 #define OFFS_XLOG_OUT_ADDR        0x78
 202 #define OFFS_PROTOCOL_END_ADDR    0x7c
 203 #define OFFS_PROTOCOL_ID_STRING   0x80
 204 /*--------------------------------------------------------------------------*/