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x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / drivers / media / video / pxa_camera.c
blob51b683c63b70b54bafad3c9f43e583b76b686a49
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/sched.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
35
36 #include <linux/videodev2.h>
37
38 #include <mach/dma.h>
39 #include <mach/camera.h>
40
41 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
42 #define PXA_CAM_DRV_NAME "pxa27x-camera"
43
44 /* Camera Interface */
45 #define CICR0 0x0000
46 #define CICR1 0x0004
47 #define CICR2 0x0008
48 #define CICR3 0x000C
49 #define CICR4 0x0010
50 #define CISR 0x0014
51 #define CIFR 0x0018
52 #define CITOR 0x001C
53 #define CIBR0 0x0028
54 #define CIBR1 0x0030
55 #define CIBR2 0x0038
56
57 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
58 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
59 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
60 #define CICR0_ENB (1 << 28) /* Camera interface enable */
61 #define CICR0_DIS (1 << 27) /* Camera interface disable */
62 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
63 #define CICR0_TOM (1 << 9) /* Time-out mask */
64 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
65 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
66 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
67 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
68 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
69 #define CICR0_CDM (1 << 3) /* Disable-done mask */
70 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
71 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
72 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
73
74 #define CICR1_TBIT (1 << 31) /* Transparency bit */
75 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
76 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
77 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
78 #define CICR1_RGB_F (1 << 11) /* RGB format */
79 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
80 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
81 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
82 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
83 #define CICR1_DW (0x7 << 0) /* Data width mask */
84
85 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
86 wait count mask */
87 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
88 wait count mask */
89 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
90 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
91 wait count mask */
92 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
93 wait count mask */
94
95 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
96 wait count mask */
97 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
98 wait count mask */
99 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
100 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
101 wait count mask */
102 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
103
104 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
105 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
106 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
107 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
108 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
109 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
110 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
111 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
112
113 #define CISR_FTO (1 << 15) /* FIFO time-out */
114 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
115 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
116 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
117 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
118 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
119 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
120 #define CISR_EOL (1 << 8) /* End of line */
121 #define CISR_PAR_ERR (1 << 7) /* Parity error */
122 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
123 #define CISR_CDD (1 << 5) /* Camera interface disable done */
124 #define CISR_SOF (1 << 4) /* Start of frame */
125 #define CISR_EOF (1 << 3) /* End of frame */
126 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
127 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
128 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
129
130 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
131 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
132 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
133 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
134 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
135 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
136 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
137 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
138
139 #define CICR0_SIM_MP (0 << 24)
140 #define CICR0_SIM_SP (1 << 24)
141 #define CICR0_SIM_MS (2 << 24)
142 #define CICR0_SIM_EP (3 << 24)
143 #define CICR0_SIM_ES (4 << 24)
144
145 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
146 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
147 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
148 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
149 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
150
151 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
152 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
153 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
154 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
155 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
156
157 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
158 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
159 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
160 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
161
162 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
163 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
164 CICR0_EOFM | CICR0_FOM)
165
166 /*
167 * Structures
168 */
169 enum pxa_camera_active_dma {
170 DMA_Y = 0x1,
171 DMA_U = 0x2,
172 DMA_V = 0x4,
173 };
174
175 /* descriptor needed for the PXA DMA engine */
176 struct pxa_cam_dma {
177 dma_addr_t sg_dma;
178 struct pxa_dma_desc *sg_cpu;
179 size_t sg_size;
180 int sglen;
181 };
182
183 /* buffer for one video frame */
184 struct pxa_buffer {
185 /* common v4l buffer stuff -- must be first */
186 struct videobuf_buffer vb;
187
188 const struct soc_camera_data_format *fmt;
189
190 /* our descriptor lists for Y, U and V channels */
191 struct pxa_cam_dma dmas[3];
192
193 int inwork;
194
195 enum pxa_camera_active_dma active_dma;
196 };
197
198 struct pxa_camera_dev {
199 struct soc_camera_host soc_host;
200 /* PXA27x is only supposed to handle one camera on its Quick Capture
201 * interface. If anyone ever builds hardware to enable more than
202 * one camera, they will have to modify this driver too */
203 struct soc_camera_device *icd;
204 struct clk *clk;
205
206 unsigned int irq;
207 void __iomem *base;
208
209 int channels;
210 unsigned int dma_chans[3];
211
212 struct pxacamera_platform_data *pdata;
213 struct resource *res;
214 unsigned long platform_flags;
215 unsigned long ciclk;
216 unsigned long mclk;
217 u32 mclk_divisor;
218
219 struct list_head capture;
220
221 spinlock_t lock;
222
223 struct pxa_buffer *active;
224 struct pxa_dma_desc *sg_tail[3];
225
226 u32 save_cicr[5];
227 };
228
229 struct pxa_cam {
230 unsigned long flags;
231 };
232
233 static const char *pxa_cam_driver_description = "PXA_Camera";
234
235 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
236
237 /*
238 * Videobuf operations
239 */
240 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
241 unsigned int *size)
242 {
243 struct soc_camera_device *icd = vq->priv_data;
244
245 dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
246
247 *size = roundup(icd->user_width * icd->user_height *
248 ((icd->current_fmt->depth + 7) >> 3), 8);
249
250 if (0 == *count)
251 *count = 32;
252 while (*size * *count > vid_limit * 1024 * 1024)
253 (*count)--;
254
255 return 0;
256 }
257
258 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
259 {
260 struct soc_camera_device *icd = vq->priv_data;
261 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
262 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
263 int i;
264
265 BUG_ON(in_interrupt());
266
267 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
268 &buf->vb, buf->vb.baddr, buf->vb.bsize);
269
270 /* This waits until this buffer is out of danger, i.e., until it is no
271 * longer in STATE_QUEUED or STATE_ACTIVE */
272 videobuf_waiton(&buf->vb, 0, 0);
273 videobuf_dma_unmap(vq, dma);
274 videobuf_dma_free(dma);
275
276 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
277 if (buf->dmas[i].sg_cpu)
278 dma_free_coherent(ici->v4l2_dev.dev,
279 buf->dmas[i].sg_size,
280 buf->dmas[i].sg_cpu,
281 buf->dmas[i].sg_dma);
282 buf->dmas[i].sg_cpu = NULL;
283 }
284
285 buf->vb.state = VIDEOBUF_NEEDS_INIT;
286 }
287
288 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
289 int sg_first_ofs, int size)
290 {
291 int i, offset, dma_len, xfer_len;
292 struct scatterlist *sg;
293
294 offset = sg_first_ofs;
295 for_each_sg(sglist, sg, sglen, i) {
296 dma_len = sg_dma_len(sg);
297
298 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
299 xfer_len = roundup(min(dma_len - offset, size), 8);
300
301 size = max(0, size - xfer_len);
302 offset = 0;
303 if (size == 0)
304 break;
305 }
306
307 BUG_ON(size != 0);
308 return i + 1;
309 }
310
311 /**
312 * pxa_init_dma_channel - init dma descriptors
313 * @pcdev: pxa camera device
314 * @buf: pxa buffer to find pxa dma channel
315 * @dma: dma video buffer
316 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
317 * @cibr: camera Receive Buffer Register
318 * @size: bytes to transfer
319 * @sg_first: first element of sg_list
320 * @sg_first_ofs: offset in first element of sg_list
321 *
322 * Prepares the pxa dma descriptors to transfer one camera channel.
323 * Beware sg_first and sg_first_ofs are both input and output parameters.
324 *
325 * Returns 0 or -ENOMEM if no coherent memory is available
326 */
327 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
328 struct pxa_buffer *buf,
329 struct videobuf_dmabuf *dma, int channel,
330 int cibr, int size,
331 struct scatterlist **sg_first, int *sg_first_ofs)
332 {
333 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
334 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
335 struct scatterlist *sg;
336 int i, offset, sglen;
337 int dma_len = 0, xfer_len = 0;
338
339 if (pxa_dma->sg_cpu)
340 dma_free_coherent(dev, pxa_dma->sg_size,
341 pxa_dma->sg_cpu, pxa_dma->sg_dma);
342
343 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
344 *sg_first_ofs, size);
345
346 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
347 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
348 &pxa_dma->sg_dma, GFP_KERNEL);
349 if (!pxa_dma->sg_cpu)
350 return -ENOMEM;
351
352 pxa_dma->sglen = sglen;
353 offset = *sg_first_ofs;
354
355 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
356 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
357
358
359 for_each_sg(*sg_first, sg, sglen, i) {
360 dma_len = sg_dma_len(sg);
361
362 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
363 xfer_len = roundup(min(dma_len - offset, size), 8);
364
365 size = max(0, size - xfer_len);
366
367 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
368 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
369 pxa_dma->sg_cpu[i].dcmd =
370 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
371 #ifdef DEBUG
372 if (!i)
373 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
374 #endif
375 pxa_dma->sg_cpu[i].ddadr =
376 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
377
378 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
379 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
380 sg_dma_address(sg) + offset, xfer_len);
381 offset = 0;
382
383 if (size == 0)
384 break;
385 }
386
387 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
388 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
389
390 /*
391 * Handle 1 special case :
392 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
393 * to dma_len (end on PAGE boundary). In this case, the sg element
394 * for next plane should be the next after the last used to store the
395 * last scatter gather RAM page
396 */
397 if (xfer_len >= dma_len) {
398 *sg_first_ofs = xfer_len - dma_len;
399 *sg_first = sg_next(sg);
400 } else {
401 *sg_first_ofs = xfer_len;
402 *sg_first = sg;
403 }
404
405 return 0;
406 }
407
408 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
409 struct pxa_buffer *buf)
410 {
411 buf->active_dma = DMA_Y;
412 if (pcdev->channels == 3)
413 buf->active_dma |= DMA_U | DMA_V;
414 }
415
416 /*
417 * Please check the DMA prepared buffer structure in :
418 * Documentation/video4linux/pxa_camera.txt
419 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
420 * modification while DMA chain is running will work anyway.
421 */
422 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
423 struct videobuf_buffer *vb, enum v4l2_field field)
424 {
425 struct soc_camera_device *icd = vq->priv_data;
426 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
427 struct pxa_camera_dev *pcdev = ici->priv;
428 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
429 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
430 int ret;
431 int size_y, size_u = 0, size_v = 0;
432
433 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
434 vb, vb->baddr, vb->bsize);
435
436 /* Added list head initialization on alloc */
437 WARN_ON(!list_empty(&vb->queue));
438
439 #ifdef DEBUG
440 /* This can be useful if you want to see if we actually fill
441 * the buffer with something */
442 memset((void *)vb->baddr, 0xaa, vb->bsize);
443 #endif
444
445 BUG_ON(NULL == icd->current_fmt);
446
447 /* I think, in buf_prepare you only have to protect global data,
448 * the actual buffer is yours */
449 buf->inwork = 1;
450
451 if (buf->fmt != icd->current_fmt ||
452 vb->width != icd->user_width ||
453 vb->height != icd->user_height ||
454 vb->field != field) {
455 buf->fmt = icd->current_fmt;
456 vb->width = icd->user_width;
457 vb->height = icd->user_height;
458 vb->field = field;
459 vb->state = VIDEOBUF_NEEDS_INIT;
460 }
461
462 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
463 if (0 != vb->baddr && vb->bsize < vb->size) {
464 ret = -EINVAL;
465 goto out;
466 }
467
468 if (vb->state == VIDEOBUF_NEEDS_INIT) {
469 int size = vb->size;
470 int next_ofs = 0;
471 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
472 struct scatterlist *sg;
473
474 ret = videobuf_iolock(vq, vb, NULL);
475 if (ret)
476 goto fail;
477
478 if (pcdev->channels == 3) {
479 size_y = size / 2;
480 size_u = size_v = size / 4;
481 } else {
482 size_y = size;
483 }
484
485 sg = dma->sglist;
486
487 /* init DMA for Y channel */
488 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
489 &sg, &next_ofs);
490 if (ret) {
491 dev_err(dev, "DMA initialization for Y/RGB failed\n");
492 goto fail;
493 }
494
495 /* init DMA for U channel */
496 if (size_u)
497 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
498 size_u, &sg, &next_ofs);
499 if (ret) {
500 dev_err(dev, "DMA initialization for U failed\n");
501 goto fail_u;
502 }
503
504 /* init DMA for V channel */
505 if (size_v)
506 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
507 size_v, &sg, &next_ofs);
508 if (ret) {
509 dev_err(dev, "DMA initialization for V failed\n");
510 goto fail_v;
511 }
512
513 vb->state = VIDEOBUF_PREPARED;
514 }
515
516 buf->inwork = 0;
517 pxa_videobuf_set_actdma(pcdev, buf);
518
519 return 0;
520
521 fail_v:
522 dma_free_coherent(dev, buf->dmas[1].sg_size,
523 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
524 fail_u:
525 dma_free_coherent(dev, buf->dmas[0].sg_size,
526 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
527 fail:
528 free_buffer(vq, buf);
529 out:
530 buf->inwork = 0;
531 return ret;
532 }
533
534 /**
535 * pxa_dma_start_channels - start DMA channel for active buffer
536 * @pcdev: pxa camera device
537 *
538 * Initialize DMA channels to the beginning of the active video buffer, and
539 * start these channels.
540 */
541 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
542 {
543 int i;
544 struct pxa_buffer *active;
545
546 active = pcdev->active;
547
548 for (i = 0; i < pcdev->channels; i++) {
549 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
550 "%s (channel=%d) ddadr=%08x\n", __func__,
551 i, active->dmas[i].sg_dma);
552 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
553 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
554 }
555 }
556
557 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
558 {
559 int i;
560
561 for (i = 0; i < pcdev->channels; i++) {
562 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
563 "%s (channel=%d)\n", __func__, i);
564 DCSR(pcdev->dma_chans[i]) = 0;
565 }
566 }
567
568 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
569 struct pxa_buffer *buf)
570 {
571 int i;
572 struct pxa_dma_desc *buf_last_desc;
573
574 for (i = 0; i < pcdev->channels; i++) {
575 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
576 buf_last_desc->ddadr = DDADR_STOP;
577
578 if (pcdev->sg_tail[i])
579 /* Link the new buffer to the old tail */
580 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
581
582 /* Update the channel tail */
583 pcdev->sg_tail[i] = buf_last_desc;
584 }
585 }
586
587 /**
588 * pxa_camera_start_capture - start video capturing
589 * @pcdev: camera device
590 *
591 * Launch capturing. DMA channels should not be active yet. They should get
592 * activated at the end of frame interrupt, to capture only whole frames, and
593 * never begin the capture of a partial frame.
594 */
595 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
596 {
597 unsigned long cicr0, cifr;
598
599 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
600 /* Reset the FIFOs */
601 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
602 __raw_writel(cifr, pcdev->base + CIFR);
603 /* Enable End-Of-Frame Interrupt */
604 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
605 cicr0 &= ~CICR0_EOFM;
606 __raw_writel(cicr0, pcdev->base + CICR0);
607 }
608
609 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
610 {
611 unsigned long cicr0;
612
613 pxa_dma_stop_channels(pcdev);
614
615 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
616 __raw_writel(cicr0, pcdev->base + CICR0);
617
618 pcdev->active = NULL;
619 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
620 }
621
622 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
623 static void pxa_videobuf_queue(struct videobuf_queue *vq,
624 struct videobuf_buffer *vb)
625 {
626 struct soc_camera_device *icd = vq->priv_data;
627 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
628 struct pxa_camera_dev *pcdev = ici->priv;
629 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
630
631 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
632 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
633
634 list_add_tail(&vb->queue, &pcdev->capture);
635
636 vb->state = VIDEOBUF_ACTIVE;
637 pxa_dma_add_tail_buf(pcdev, buf);
638
639 if (!pcdev->active)
640 pxa_camera_start_capture(pcdev);
641 }
642
643 static void pxa_videobuf_release(struct videobuf_queue *vq,
644 struct videobuf_buffer *vb)
645 {
646 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
647 #ifdef DEBUG
648 struct soc_camera_device *icd = vq->priv_data;
649 struct device *dev = icd->dev.parent;
650
651 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
652 vb, vb->baddr, vb->bsize);
653
654 switch (vb->state) {
655 case VIDEOBUF_ACTIVE:
656 dev_dbg(dev, "%s (active)\n", __func__);
657 break;
658 case VIDEOBUF_QUEUED:
659 dev_dbg(dev, "%s (queued)\n", __func__);
660 break;
661 case VIDEOBUF_PREPARED:
662 dev_dbg(dev, "%s (prepared)\n", __func__);
663 break;
664 default:
665 dev_dbg(dev, "%s (unknown)\n", __func__);
666 break;
667 }
668 #endif
669
670 free_buffer(vq, buf);
671 }
672
673 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
674 struct videobuf_buffer *vb,
675 struct pxa_buffer *buf)
676 {
677 int i;
678
679 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
680 list_del_init(&vb->queue);
681 vb->state = VIDEOBUF_DONE;
682 do_gettimeofday(&vb->ts);
683 vb->field_count++;
684 wake_up(&vb->done);
685 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
686 __func__, vb);
687
688 if (list_empty(&pcdev->capture)) {
689 pxa_camera_stop_capture(pcdev);
690 for (i = 0; i < pcdev->channels; i++)
691 pcdev->sg_tail[i] = NULL;
692 return;
693 }
694
695 pcdev->active = list_entry(pcdev->capture.next,
696 struct pxa_buffer, vb.queue);
697 }
698
699 /**
700 * pxa_camera_check_link_miss - check missed DMA linking
701 * @pcdev: camera device
702 *
703 * The DMA chaining is done with DMA running. This means a tiny temporal window
704 * remains, where a buffer is queued on the chain, while the chain is already
705 * stopped. This means the tailed buffer would never be transfered by DMA.
706 * This function restarts the capture for this corner case, where :
707 * - DADR() == DADDR_STOP
708 * - a videobuffer is queued on the pcdev->capture list
709 *
710 * Please check the "DMA hot chaining timeslice issue" in
711 * Documentation/video4linux/pxa_camera.txt
712 *
713 * Context: should only be called within the dma irq handler
714 */
715 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
716 {
717 int i, is_dma_stopped = 1;
718
719 for (i = 0; i < pcdev->channels; i++)
720 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
721 is_dma_stopped = 0;
722 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
723 "%s : top queued buffer=%p, dma_stopped=%d\n",
724 __func__, pcdev->active, is_dma_stopped);
725 if (pcdev->active && is_dma_stopped)
726 pxa_camera_start_capture(pcdev);
727 }
728
729 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
730 enum pxa_camera_active_dma act_dma)
731 {
732 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
733 struct pxa_buffer *buf;
734 unsigned long flags;
735 u32 status, camera_status, overrun;
736 struct videobuf_buffer *vb;
737
738 spin_lock_irqsave(&pcdev->lock, flags);
739
740 status = DCSR(channel);
741 DCSR(channel) = status;
742
743 camera_status = __raw_readl(pcdev->base + CISR);
744 overrun = CISR_IFO_0;
745 if (pcdev->channels == 3)
746 overrun |= CISR_IFO_1 | CISR_IFO_2;
747
748 if (status & DCSR_BUSERR) {
749 dev_err(dev, "DMA Bus Error IRQ!\n");
750 goto out;
751 }
752
753 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
754 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
755 status);
756 goto out;
757 }
758
759 /*
760 * pcdev->active should not be NULL in DMA irq handler.
761 *
762 * But there is one corner case : if capture was stopped due to an
763 * overrun of channel 1, and at that same channel 2 was completed.
764 *
765 * When handling the overrun in DMA irq for channel 1, we'll stop the
766 * capture and restart it (and thus set pcdev->active to NULL). But the
767 * DMA irq handler will already be pending for channel 2. So on entering
768 * the DMA irq handler for channel 2 there will be no active buffer, yet
769 * that is normal.
770 */
771 if (!pcdev->active)
772 goto out;
773
774 vb = &pcdev->active->vb;
775 buf = container_of(vb, struct pxa_buffer, vb);
776 WARN_ON(buf->inwork || list_empty(&vb->queue));
777
778 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
779 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
780 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
781
782 if (status & DCSR_ENDINTR) {
783 /*
784 * It's normal if the last frame creates an overrun, as there
785 * are no more DMA descriptors to fetch from QCI fifos
786 */
787 if (camera_status & overrun &&
788 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
789 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
790 camera_status);
791 pxa_camera_stop_capture(pcdev);
792 pxa_camera_start_capture(pcdev);
793 goto out;
794 }
795 buf->active_dma &= ~act_dma;
796 if (!buf->active_dma) {
797 pxa_camera_wakeup(pcdev, vb, buf);
798 pxa_camera_check_link_miss(pcdev);
799 }
800 }
801
802 out:
803 spin_unlock_irqrestore(&pcdev->lock, flags);
804 }
805
806 static void pxa_camera_dma_irq_y(int channel, void *data)
807 {
808 struct pxa_camera_dev *pcdev = data;
809 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
810 }
811
812 static void pxa_camera_dma_irq_u(int channel, void *data)
813 {
814 struct pxa_camera_dev *pcdev = data;
815 pxa_camera_dma_irq(channel, pcdev, DMA_U);
816 }
817
818 static void pxa_camera_dma_irq_v(int channel, void *data)
819 {
820 struct pxa_camera_dev *pcdev = data;
821 pxa_camera_dma_irq(channel, pcdev, DMA_V);
822 }
823
824 static struct videobuf_queue_ops pxa_videobuf_ops = {
825 .buf_setup = pxa_videobuf_setup,
826 .buf_prepare = pxa_videobuf_prepare,
827 .buf_queue = pxa_videobuf_queue,
828 .buf_release = pxa_videobuf_release,
829 };
830
831 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
832 struct soc_camera_device *icd)
833 {
834 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
835 struct pxa_camera_dev *pcdev = ici->priv;
836
837 /* We must pass NULL as dev pointer, then all pci_* dma operations
838 * transform to normal dma_* ones. */
839 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
840 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
841 sizeof(struct pxa_buffer), icd);
842 }
843
844 static u32 mclk_get_divisor(struct platform_device *pdev,
845 struct pxa_camera_dev *pcdev)
846 {
847 unsigned long mclk = pcdev->mclk;
848 struct device *dev = &pdev->dev;
849 u32 div;
850 unsigned long lcdclk;
851
852 lcdclk = clk_get_rate(pcdev->clk);
853 pcdev->ciclk = lcdclk;
854
855 /* mclk <= ciclk / 4 (27.4.2) */
856 if (mclk > lcdclk / 4) {
857 mclk = lcdclk / 4;
858 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
859 }
860
861 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
862 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
863
864 /* If we're not supplying MCLK, leave it at 0 */
865 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
866 pcdev->mclk = lcdclk / (2 * (div + 1));
867
868 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
869 lcdclk, mclk, div);
870
871 return div;
872 }
873
874 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
875 unsigned long pclk)
876 {
877 /* We want a timeout > 1 pixel time, not ">=" */
878 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
879
880 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
881 }
882
883 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
884 {
885 struct pxacamera_platform_data *pdata = pcdev->pdata;
886 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
887 u32 cicr4 = 0;
888
889 dev_dbg(dev, "Registered platform device at %p data %p\n",
890 pcdev, pdata);
891
892 if (pdata && pdata->init) {
893 dev_dbg(dev, "%s: Init gpios\n", __func__);
894 pdata->init(dev);
895 }
896
897 /* disable all interrupts */
898 __raw_writel(0x3ff, pcdev->base + CICR0);
899
900 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
901 cicr4 |= CICR4_PCLK_EN;
902 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
903 cicr4 |= CICR4_MCLK_EN;
904 if (pcdev->platform_flags & PXA_CAMERA_PCP)
905 cicr4 |= CICR4_PCP;
906 if (pcdev->platform_flags & PXA_CAMERA_HSP)
907 cicr4 |= CICR4_HSP;
908 if (pcdev->platform_flags & PXA_CAMERA_VSP)
909 cicr4 |= CICR4_VSP;
910
911 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
912
913 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
914 /* Initialise the timeout under the assumption pclk = mclk */
915 recalculate_fifo_timeout(pcdev, pcdev->mclk);
916 else
917 /* "Safe default" - 13MHz */
918 recalculate_fifo_timeout(pcdev, 13000000);
919
920 clk_enable(pcdev->clk);
921 }
922
923 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
924 {
925 clk_disable(pcdev->clk);
926 }
927
928 static irqreturn_t pxa_camera_irq(int irq, void *data)
929 {
930 struct pxa_camera_dev *pcdev = data;
931 unsigned long status, cicr0;
932 struct pxa_buffer *buf;
933 struct videobuf_buffer *vb;
934
935 status = __raw_readl(pcdev->base + CISR);
936 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
937 "Camera interrupt status 0x%lx\n", status);
938
939 if (!status)
940 return IRQ_NONE;
941
942 __raw_writel(status, pcdev->base + CISR);
943
944 if (status & CISR_EOF) {
945 pcdev->active = list_first_entry(&pcdev->capture,
946 struct pxa_buffer, vb.queue);
947 vb = &pcdev->active->vb;
948 buf = container_of(vb, struct pxa_buffer, vb);
949 pxa_videobuf_set_actdma(pcdev, buf);
950
951 pxa_dma_start_channels(pcdev);
952
953 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
954 __raw_writel(cicr0, pcdev->base + CICR0);
955 }
956
957 return IRQ_HANDLED;
958 }
959
960 /*
961 * The following two functions absolutely depend on the fact, that
962 * there can be only one camera on PXA quick capture interface
963 * Called with .video_lock held
964 */
965 static int pxa_camera_add_device(struct soc_camera_device *icd)
966 {
967 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
968 struct pxa_camera_dev *pcdev = ici->priv;
969
970 if (pcdev->icd)
971 return -EBUSY;
972
973 pxa_camera_activate(pcdev);
974
975 pcdev->icd = icd;
976
977 dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
978 icd->devnum);
979
980 return 0;
981 }
982
983 /* Called with .video_lock held */
984 static void pxa_camera_remove_device(struct soc_camera_device *icd)
985 {
986 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
987 struct pxa_camera_dev *pcdev = ici->priv;
988
989 BUG_ON(icd != pcdev->icd);
990
991 dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
992 icd->devnum);
993
994 /* disable capture, disable interrupts */
995 __raw_writel(0x3ff, pcdev->base + CICR0);
996
997 /* Stop DMA engine */
998 DCSR(pcdev->dma_chans[0]) = 0;
999 DCSR(pcdev->dma_chans[1]) = 0;
1000 DCSR(pcdev->dma_chans[2]) = 0;
1001
1002 pxa_camera_deactivate(pcdev);
1003
1004 pcdev->icd = NULL;
1005 }
1006
1007 static int test_platform_param(struct pxa_camera_dev *pcdev,
1008 unsigned char buswidth, unsigned long *flags)
1009 {
1010 /*
1011 * Platform specified synchronization and pixel clock polarities are
1012 * only a recommendation and are only used during probing. The PXA270
1013 * quick capture interface supports both.
1014 */
1015 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1016 SOCAM_MASTER : SOCAM_SLAVE) |
1017 SOCAM_HSYNC_ACTIVE_HIGH |
1018 SOCAM_HSYNC_ACTIVE_LOW |
1019 SOCAM_VSYNC_ACTIVE_HIGH |
1020 SOCAM_VSYNC_ACTIVE_LOW |
1021 SOCAM_DATA_ACTIVE_HIGH |
1022 SOCAM_PCLK_SAMPLE_RISING |
1023 SOCAM_PCLK_SAMPLE_FALLING;
1024
1025 /* If requested data width is supported by the platform, use it */
1026 switch (buswidth) {
1027 case 10:
1028 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1029 return -EINVAL;
1030 *flags |= SOCAM_DATAWIDTH_10;
1031 break;
1032 case 9:
1033 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1034 return -EINVAL;
1035 *flags |= SOCAM_DATAWIDTH_9;
1036 break;
1037 case 8:
1038 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1039 return -EINVAL;
1040 *flags |= SOCAM_DATAWIDTH_8;
1041 break;
1042 default:
1043 return -EINVAL;
1044 }
1045
1046 return 0;
1047 }
1048
1049 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1050 unsigned long flags, __u32 pixfmt)
1051 {
1052 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1053 struct pxa_camera_dev *pcdev = ici->priv;
1054 unsigned long dw, bpp;
1055 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
1056
1057 /* Datawidth is now guaranteed to be equal to one of the three values.
1058 * We fix bit-per-pixel equal to data-width... */
1059 switch (flags & SOCAM_DATAWIDTH_MASK) {
1060 case SOCAM_DATAWIDTH_10:
1061 dw = 4;
1062 bpp = 0x40;
1063 break;
1064 case SOCAM_DATAWIDTH_9:
1065 dw = 3;
1066 bpp = 0x20;
1067 break;
1068 default:
1069 /* Actually it can only be 8 now,
1070 * default is just to silence compiler warnings */
1071 case SOCAM_DATAWIDTH_8:
1072 dw = 2;
1073 bpp = 0;
1074 }
1075
1076 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1077 cicr4 |= CICR4_PCLK_EN;
1078 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1079 cicr4 |= CICR4_MCLK_EN;
1080 if (flags & SOCAM_PCLK_SAMPLE_FALLING)
1081 cicr4 |= CICR4_PCP;
1082 if (flags & SOCAM_HSYNC_ACTIVE_LOW)
1083 cicr4 |= CICR4_HSP;
1084 if (flags & SOCAM_VSYNC_ACTIVE_LOW)
1085 cicr4 |= CICR4_VSP;
1086
1087 cicr0 = __raw_readl(pcdev->base + CICR0);
1088 if (cicr0 & CICR0_ENB)
1089 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1090
1091 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1092
1093 switch (pixfmt) {
1094 case V4L2_PIX_FMT_YUV422P:
1095 pcdev->channels = 3;
1096 cicr1 |= CICR1_YCBCR_F;
1097 /*
1098 * Normally, pxa bus wants as input UYVY format. We allow all
1099 * reorderings of the YUV422 format, as no processing is done,
1100 * and the YUV stream is just passed through without any
1101 * transformation. Note that UYVY is the only format that
1102 * should be used if pxa framebuffer Overlay2 is used.
1103 */
1104 case V4L2_PIX_FMT_UYVY:
1105 case V4L2_PIX_FMT_VYUY:
1106 case V4L2_PIX_FMT_YUYV:
1107 case V4L2_PIX_FMT_YVYU:
1108 cicr1 |= CICR1_COLOR_SP_VAL(2);
1109 break;
1110 case V4L2_PIX_FMT_RGB555:
1111 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1112 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1113 break;
1114 case V4L2_PIX_FMT_RGB565:
1115 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1116 break;
1117 }
1118
1119 cicr2 = 0;
1120 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1121 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1122 cicr4 |= pcdev->mclk_divisor;
1123
1124 __raw_writel(cicr1, pcdev->base + CICR1);
1125 __raw_writel(cicr2, pcdev->base + CICR2);
1126 __raw_writel(cicr3, pcdev->base + CICR3);
1127 __raw_writel(cicr4, pcdev->base + CICR4);
1128
1129 /* CIF interrupts are not used, only DMA */
1130 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1131 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1132 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1133 __raw_writel(cicr0, pcdev->base + CICR0);
1134 }
1135
1136 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1137 {
1138 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1139 struct pxa_camera_dev *pcdev = ici->priv;
1140 unsigned long bus_flags, camera_flags, common_flags;
1141 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
1142 struct pxa_cam *cam = icd->host_priv;
1143
1144 if (ret < 0)
1145 return ret;
1146
1147 camera_flags = icd->ops->query_bus_param(icd);
1148
1149 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1150 if (!common_flags)
1151 return -EINVAL;
1152
1153 pcdev->channels = 1;
1154
1155 /* Make choises, based on platform preferences */
1156 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1157 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1158 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1159 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1160 else
1161 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1162 }
1163
1164 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1165 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1166 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1167 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1168 else
1169 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1170 }
1171
1172 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1173 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1174 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1175 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1176 else
1177 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1178 }
1179
1180 cam->flags = common_flags;
1181
1182 ret = icd->ops->set_bus_param(icd, common_flags);
1183 if (ret < 0)
1184 return ret;
1185
1186 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1187
1188 return 0;
1189 }
1190
1191 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1192 unsigned char buswidth)
1193 {
1194 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1195 struct pxa_camera_dev *pcdev = ici->priv;
1196 unsigned long bus_flags, camera_flags;
1197 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1198
1199 if (ret < 0)
1200 return ret;
1201
1202 camera_flags = icd->ops->query_bus_param(icd);
1203
1204 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1205 }
1206
1207 static const struct soc_camera_data_format pxa_camera_formats[] = {
1208 {
1209 .name = "Planar YUV422 16 bit",
1210 .depth = 16,
1211 .fourcc = V4L2_PIX_FMT_YUV422P,
1212 .colorspace = V4L2_COLORSPACE_JPEG,
1213 },
1214 };
1215
1216 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1217 {
1218 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1219 struct pxa_camera_dev *pcdev = ici->priv;
1220
1221 switch (depth) {
1222 case 8:
1223 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1224 case 9:
1225 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1226 case 10:
1227 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1228 }
1229 return false;
1230 }
1231
1232 static int required_buswidth(const struct soc_camera_data_format *fmt)
1233 {
1234 switch (fmt->fourcc) {
1235 case V4L2_PIX_FMT_UYVY:
1236 case V4L2_PIX_FMT_VYUY:
1237 case V4L2_PIX_FMT_YUYV:
1238 case V4L2_PIX_FMT_YVYU:
1239 case V4L2_PIX_FMT_RGB565:
1240 case V4L2_PIX_FMT_RGB555:
1241 return 8;
1242 default:
1243 return fmt->depth;
1244 }
1245 }
1246
1247 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1248 struct soc_camera_format_xlate *xlate)
1249 {
1250 struct device *dev = icd->dev.parent;
1251 int formats = 0, buswidth, ret;
1252 struct pxa_cam *cam;
1253
1254 buswidth = required_buswidth(icd->formats + idx);
1255
1256 if (!buswidth_supported(icd, buswidth))
1257 return 0;
1258
1259 ret = pxa_camera_try_bus_param(icd, buswidth);
1260 if (ret < 0)
1261 return 0;
1262
1263 if (!icd->host_priv) {
1264 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1265 if (!cam)
1266 return -ENOMEM;
1267
1268 icd->host_priv = cam;
1269 } else {
1270 cam = icd->host_priv;
1271 }
1272
1273 switch (icd->formats[idx].fourcc) {
1274 case V4L2_PIX_FMT_UYVY:
1275 formats++;
1276 if (xlate) {
1277 xlate->host_fmt = &pxa_camera_formats[0];
1278 xlate->cam_fmt = icd->formats + idx;
1279 xlate->buswidth = buswidth;
1280 xlate++;
1281 dev_dbg(dev, "Providing format %s using %s\n",
1282 pxa_camera_formats[0].name,
1283 icd->formats[idx].name);
1284 }
1285 case V4L2_PIX_FMT_VYUY:
1286 case V4L2_PIX_FMT_YUYV:
1287 case V4L2_PIX_FMT_YVYU:
1288 case V4L2_PIX_FMT_RGB565:
1289 case V4L2_PIX_FMT_RGB555:
1290 formats++;
1291 if (xlate) {
1292 xlate->host_fmt = icd->formats + idx;
1293 xlate->cam_fmt = icd->formats + idx;
1294 xlate->buswidth = buswidth;
1295 xlate++;
1296 dev_dbg(dev, "Providing format %s packed\n",
1297 icd->formats[idx].name);
1298 }
1299 break;
1300 default:
1301 /* Generic pass-through */
1302 formats++;
1303 if (xlate) {
1304 xlate->host_fmt = icd->formats + idx;
1305 xlate->cam_fmt = icd->formats + idx;
1306 xlate->buswidth = icd->formats[idx].depth;
1307 xlate++;
1308 dev_dbg(dev,
1309 "Providing format %s in pass-through mode\n",
1310 icd->formats[idx].name);
1311 }
1312 }
1313
1314 return formats;
1315 }
1316
1317 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1318 {
1319 kfree(icd->host_priv);
1320 icd->host_priv = NULL;
1321 }
1322
1323 static int pxa_camera_check_frame(struct v4l2_pix_format *pix)
1324 {
1325 /* limit to pxa hardware capabilities */
1326 return pix->height < 32 || pix->height > 2048 || pix->width < 48 ||
1327 pix->width > 2048 || (pix->width & 0x01);
1328 }
1329
1330 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1331 struct v4l2_crop *a)
1332 {
1333 struct v4l2_rect *rect = &a->c;
1334 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1335 struct pxa_camera_dev *pcdev = ici->priv;
1336 struct device *dev = icd->dev.parent;
1337 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1338 struct soc_camera_sense sense = {
1339 .master_clock = pcdev->mclk,
1340 .pixel_clock_max = pcdev->ciclk / 4,
1341 };
1342 struct v4l2_format f;
1343 struct v4l2_pix_format *pix = &f.fmt.pix, pix_tmp;
1344 struct pxa_cam *cam = icd->host_priv;
1345 int ret;
1346
1347 /* If PCLK is used to latch data from the sensor, check sense */
1348 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1349 icd->sense = &sense;
1350
1351 ret = v4l2_subdev_call(sd, video, s_crop, a);
1352
1353 icd->sense = NULL;
1354
1355 if (ret < 0) {
1356 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1357 rect->width, rect->height, rect->left, rect->top);
1358 return ret;
1359 }
1360
1361 f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1362
1363 ret = v4l2_subdev_call(sd, video, g_fmt, &f);
1364 if (ret < 0)
1365 return ret;
1366
1367 pix_tmp = *pix;
1368 if (pxa_camera_check_frame(pix)) {
1369 /*
1370 * Camera cropping produced a frame beyond our capabilities.
1371 * FIXME: just extract a subframe, that we can process.
1372 */
1373 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1374 &pix->height, 32, 2048, 0,
1375 icd->current_fmt->fourcc == V4L2_PIX_FMT_YUV422P ?
1376 4 : 0);
1377 ret = v4l2_subdev_call(sd, video, s_fmt, &f);
1378 if (ret < 0)
1379 return ret;
1380
1381 if (pxa_camera_check_frame(pix)) {
1382 dev_warn(icd->dev.parent,
1383 "Inconsistent state. Use S_FMT to repair\n");
1384 return -EINVAL;
1385 }
1386 }
1387
1388 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1389 if (sense.pixel_clock > sense.pixel_clock_max) {
1390 dev_err(dev,
1391 "pixel clock %lu set by the camera too high!",
1392 sense.pixel_clock);
1393 return -EIO;
1394 }
1395 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1396 }
1397
1398 icd->user_width = pix->width;
1399 icd->user_height = pix->height;
1400
1401 pxa_camera_setup_cicr(icd, cam->flags, icd->current_fmt->fourcc);
1402
1403 return ret;
1404 }
1405
1406 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1407 struct v4l2_format *f)
1408 {
1409 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1410 struct pxa_camera_dev *pcdev = ici->priv;
1411 struct device *dev = icd->dev.parent;
1412 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1413 const struct soc_camera_data_format *cam_fmt = NULL;
1414 const struct soc_camera_format_xlate *xlate = NULL;
1415 struct soc_camera_sense sense = {
1416 .master_clock = pcdev->mclk,
1417 .pixel_clock_max = pcdev->ciclk / 4,
1418 };
1419 struct v4l2_pix_format *pix = &f->fmt.pix;
1420 struct v4l2_format cam_f = *f;
1421 int ret;
1422
1423 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1424 if (!xlate) {
1425 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1426 return -EINVAL;
1427 }
1428
1429 cam_fmt = xlate->cam_fmt;
1430
1431 /* If PCLK is used to latch data from the sensor, check sense */
1432 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1433 icd->sense = &sense;
1434
1435 cam_f.fmt.pix.pixelformat = cam_fmt->fourcc;
1436 ret = v4l2_subdev_call(sd, video, s_fmt, &cam_f);
1437 cam_f.fmt.pix.pixelformat = pix->pixelformat;
1438 *pix = cam_f.fmt.pix;
1439
1440 icd->sense = NULL;
1441
1442 if (ret < 0) {
1443 dev_warn(dev, "Failed to configure for format %x\n",
1444 pix->pixelformat);
1445 } else if (pxa_camera_check_frame(pix)) {
1446 dev_warn(dev,
1447 "Camera driver produced an unsupported frame %dx%d\n",
1448 pix->width, pix->height);
1449 ret = -EINVAL;
1450 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1451 if (sense.pixel_clock > sense.pixel_clock_max) {
1452 dev_err(dev,
1453 "pixel clock %lu set by the camera too high!",
1454 sense.pixel_clock);
1455 return -EIO;
1456 }
1457 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1458 }
1459
1460 if (!ret) {
1461 icd->buswidth = xlate->buswidth;
1462 icd->current_fmt = xlate->host_fmt;
1463 }
1464
1465 return ret;
1466 }
1467
1468 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1469 struct v4l2_format *f)
1470 {
1471 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1472 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1473 const struct soc_camera_format_xlate *xlate;
1474 struct v4l2_pix_format *pix = &f->fmt.pix;
1475 __u32 pixfmt = pix->pixelformat;
1476 enum v4l2_field field;
1477 int ret;
1478
1479 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1480 if (!xlate) {
1481 dev_warn(ici->v4l2_dev.dev, "Format %x not found\n", pixfmt);
1482 return -EINVAL;
1483 }
1484
1485 /*
1486 * Limit to pxa hardware capabilities. YUV422P planar format requires
1487 * images size to be a multiple of 16 bytes. If not, zeros will be
1488 * inserted between Y and U planes, and U and V planes, which violates
1489 * the YUV422P standard.
1490 */
1491 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1492 &pix->height, 32, 2048, 0,
1493 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1494
1495 pix->bytesperline = pix->width *
1496 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1497 pix->sizeimage = pix->height * pix->bytesperline;
1498
1499 /* camera has to see its format, but the user the original one */
1500 pix->pixelformat = xlate->cam_fmt->fourcc;
1501 /* limit to sensor capabilities */
1502 ret = v4l2_subdev_call(sd, video, try_fmt, f);
1503 pix->pixelformat = pixfmt;
1504
1505 field = pix->field;
1506
1507 if (field == V4L2_FIELD_ANY) {
1508 pix->field = V4L2_FIELD_NONE;
1509 } else if (field != V4L2_FIELD_NONE) {
1510 dev_err(icd->dev.parent, "Field type %d unsupported.\n", field);
1511 return -EINVAL;
1512 }
1513
1514 return ret;
1515 }
1516
1517 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1518 struct v4l2_requestbuffers *p)
1519 {
1520 int i;
1521
1522 /* This is for locking debugging only. I removed spinlocks and now I
1523 * check whether .prepare is ever called on a linked buffer, or whether
1524 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1525 * it hadn't triggered */
1526 for (i = 0; i < p->count; i++) {
1527 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1528 struct pxa_buffer, vb);
1529 buf->inwork = 0;
1530 INIT_LIST_HEAD(&buf->vb.queue);
1531 }
1532
1533 return 0;
1534 }
1535
1536 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1537 {
1538 struct soc_camera_file *icf = file->private_data;
1539 struct pxa_buffer *buf;
1540
1541 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1542 vb.stream);
1543
1544 poll_wait(file, &buf->vb.done, pt);
1545
1546 if (buf->vb.state == VIDEOBUF_DONE ||
1547 buf->vb.state == VIDEOBUF_ERROR)
1548 return POLLIN|POLLRDNORM;
1549
1550 return 0;
1551 }
1552
1553 static int pxa_camera_querycap(struct soc_camera_host *ici,
1554 struct v4l2_capability *cap)
1555 {
1556 /* cap->name is set by the firendly caller:-> */
1557 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1558 cap->version = PXA_CAM_VERSION_CODE;
1559 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1560
1561 return 0;
1562 }
1563
1564 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1565 {
1566 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1567 struct pxa_camera_dev *pcdev = ici->priv;
1568 int i = 0, ret = 0;
1569
1570 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1571 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1572 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1573 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1574 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1575
1576 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1577 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1578
1579 return ret;
1580 }
1581
1582 static int pxa_camera_resume(struct soc_camera_device *icd)
1583 {
1584 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1585 struct pxa_camera_dev *pcdev = ici->priv;
1586 int i = 0, ret = 0;
1587
1588 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1589 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1590 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1591
1592 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1593 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1594 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1595 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1596 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1597
1598 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1599 ret = pcdev->icd->ops->resume(pcdev->icd);
1600
1601 /* Restart frame capture if active buffer exists */
1602 if (!ret && pcdev->active)
1603 pxa_camera_start_capture(pcdev);
1604
1605 return ret;
1606 }
1607
1608 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1609 .owner = THIS_MODULE,
1610 .add = pxa_camera_add_device,
1611 .remove = pxa_camera_remove_device,
1612 .suspend = pxa_camera_suspend,
1613 .resume = pxa_camera_resume,
1614 .set_crop = pxa_camera_set_crop,
1615 .get_formats = pxa_camera_get_formats,
1616 .put_formats = pxa_camera_put_formats,
1617 .set_fmt = pxa_camera_set_fmt,
1618 .try_fmt = pxa_camera_try_fmt,
1619 .init_videobuf = pxa_camera_init_videobuf,
1620 .reqbufs = pxa_camera_reqbufs,
1621 .poll = pxa_camera_poll,
1622 .querycap = pxa_camera_querycap,
1623 .set_bus_param = pxa_camera_set_bus_param,
1624 };
1625
1626 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1627 {
1628 struct pxa_camera_dev *pcdev;
1629 struct resource *res;
1630 void __iomem *base;
1631 int irq;
1632 int err = 0;
1633
1634 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1635 irq = platform_get_irq(pdev, 0);
1636 if (!res || irq < 0) {
1637 err = -ENODEV;
1638 goto exit;
1639 }
1640
1641 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1642 if (!pcdev) {
1643 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1644 err = -ENOMEM;
1645 goto exit;
1646 }
1647
1648 pcdev->clk = clk_get(&pdev->dev, NULL);
1649 if (IS_ERR(pcdev->clk)) {
1650 err = PTR_ERR(pcdev->clk);
1651 goto exit_kfree;
1652 }
1653
1654 pcdev->res = res;
1655
1656 pcdev->pdata = pdev->dev.platform_data;
1657 pcdev->platform_flags = pcdev->pdata->flags;
1658 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1659 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1660 /* Platform hasn't set available data widths. This is bad.
1661 * Warn and use a default. */
1662 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1663 "data widths, using default 10 bit\n");
1664 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1665 }
1666 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1667 if (!pcdev->mclk) {
1668 dev_warn(&pdev->dev,
1669 "mclk == 0! Please, fix your platform data. "
1670 "Using default 20MHz\n");
1671 pcdev->mclk = 20000000;
1672 }
1673
1674 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1675
1676 INIT_LIST_HEAD(&pcdev->capture);
1677 spin_lock_init(&pcdev->lock);
1678
1679 /*
1680 * Request the regions.
1681 */
1682 if (!request_mem_region(res->start, resource_size(res),
1683 PXA_CAM_DRV_NAME)) {
1684 err = -EBUSY;
1685 goto exit_clk;
1686 }
1687
1688 base = ioremap(res->start, resource_size(res));
1689 if (!base) {
1690 err = -ENOMEM;
1691 goto exit_release;
1692 }
1693 pcdev->irq = irq;
1694 pcdev->base = base;
1695
1696 /* request dma */
1697 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1698 pxa_camera_dma_irq_y, pcdev);
1699 if (err < 0) {
1700 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1701 goto exit_iounmap;
1702 }
1703 pcdev->dma_chans[0] = err;
1704 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1705
1706 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1707 pxa_camera_dma_irq_u, pcdev);
1708 if (err < 0) {
1709 dev_err(&pdev->dev, "Can't request DMA for U\n");
1710 goto exit_free_dma_y;
1711 }
1712 pcdev->dma_chans[1] = err;
1713 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1714
1715 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1716 pxa_camera_dma_irq_v, pcdev);
1717 if (err < 0) {
1718 dev_err(&pdev->dev, "Can't request DMA for V\n");
1719 goto exit_free_dma_u;
1720 }
1721 pcdev->dma_chans[2] = err;
1722 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1723
1724 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1725 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1726 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1727
1728 /* request irq */
1729 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1730 pcdev);
1731 if (err) {
1732 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1733 goto exit_free_dma;
1734 }
1735
1736 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1737 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1738 pcdev->soc_host.priv = pcdev;
1739 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1740 pcdev->soc_host.nr = pdev->id;
1741
1742 err = soc_camera_host_register(&pcdev->soc_host);
1743 if (err)
1744 goto exit_free_irq;
1745
1746 return 0;
1747
1748 exit_free_irq:
1749 free_irq(pcdev->irq, pcdev);
1750 exit_free_dma:
1751 pxa_free_dma(pcdev->dma_chans[2]);
1752 exit_free_dma_u:
1753 pxa_free_dma(pcdev->dma_chans[1]);
1754 exit_free_dma_y:
1755 pxa_free_dma(pcdev->dma_chans[0]);
1756 exit_iounmap:
1757 iounmap(base);
1758 exit_release:
1759 release_mem_region(res->start, resource_size(res));
1760 exit_clk:
1761 clk_put(pcdev->clk);
1762 exit_kfree:
1763 kfree(pcdev);
1764 exit:
1765 return err;
1766 }
1767
1768 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1769 {
1770 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1771 struct pxa_camera_dev *pcdev = container_of(soc_host,
1772 struct pxa_camera_dev, soc_host);
1773 struct resource *res;
1774
1775 clk_put(pcdev->clk);
1776
1777 pxa_free_dma(pcdev->dma_chans[0]);
1778 pxa_free_dma(pcdev->dma_chans[1]);
1779 pxa_free_dma(pcdev->dma_chans[2]);
1780 free_irq(pcdev->irq, pcdev);
1781
1782 soc_camera_host_unregister(soc_host);
1783
1784 iounmap(pcdev->base);
1785
1786 res = pcdev->res;
1787 release_mem_region(res->start, resource_size(res));
1788
1789 kfree(pcdev);
1790
1791 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1792
1793 return 0;
1794 }
1795
1796 static struct platform_driver pxa_camera_driver = {
1797 .driver = {
1798 .name = PXA_CAM_DRV_NAME,
1799 },
1800 .probe = pxa_camera_probe,
1801 .remove = __devexit_p(pxa_camera_remove),
1802 };
1803
1804
1805 static int __init pxa_camera_init(void)
1806 {
1807 return platform_driver_register(&pxa_camera_driver);
1808 }
1809
1810 static void __exit pxa_camera_exit(void)
1811 {
1812 platform_driver_unregister(&pxa_camera_driver);
1813 }
1814
1815 module_init(pxa_camera_init);
1816 module_exit(pxa_camera_exit);
1817
1818 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1819 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1820 MODULE_LICENSE("GPL");
1821 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux with added FPC-III support