drivers/net/benet/be_hw.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /********* Mailbox door bell *************/
  19 /* Used for driver communication with the FW.
  20  * The software must write this register twice to post any command. First,
  21  * it writes the register with hi=1 and the upper bits of the physical address
  22  * for the MAILBOX structure. Software must poll the ready bit until this
  23  * is acknowledged. Then, sotware writes the register with hi=0 with the lower
  24  * bits in the address. It must poll the ready bit until the command is
  25  * complete. Upon completion, the MAILBOX will contain a valid completion
  26  * queue entry.
  27  */
  28 #define MPU_MAILBOX_DB_OFFSET   0x160
  29 #define MPU_MAILBOX_DB_RDY_MASK 0x1     /* bit 0 */
  30 #define MPU_MAILBOX_DB_HI_MASK  0x2     /* bit 1 */
  31
  32 #define MPU_EP_CONTROL          0
  33
  34 /********** MPU semphore ******************/
  35 #define MPU_EP_SEMAPHORE_OFFSET         0xac
  36 #define EP_SEMAPHORE_POST_STAGE_MASK    0x0000FFFF
  37 #define EP_SEMAPHORE_POST_ERR_MASK      0x1
  38 #define EP_SEMAPHORE_POST_ERR_SHIFT     31
  39 /* MPU semphore POST stage values */
  40 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
  41 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
  42 #define POST_STAGE_BE_RESET             0x3 /* Host wants to reset chip */
  43 #define POST_STAGE_ARMFW_RDY            0xc000  /* FW is done with POST */
  44
  45 /********* Memory BAR register ************/
  46 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
  47 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
  48  * Disable" may still globally block interrupts in addition to individual
  49  * interrupt masks; a mechanism for the device driver to block all interrupts
  50  * atomically without having to arbitrate for the PCI Interrupt Disable bit
  51  * with the OS.
  52  */
  53 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29) /* bit 29 */
  54
  55 /********* ISR0 Register offset **********/
  56 #define CEV_ISR0_OFFSET                         0xC18
  57 #define CEV_ISR_SIZE                            4
  58
  59 /********* Event Q door bell *************/
  60 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
  61 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
  62 /* Clear the interrupt for this eq */
  63 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
  64 /* Must be 1 */
  65 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
  66 /* Number of event entries processed */
  67 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  68 /* Rearm bit */
  69 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
  70
  71 /********* Compl Q door bell *************/
  72 #define DB_CQ_OFFSET                    0x120
  73 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  74 /* Number of event entries processed */
  75 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
  76 /* Rearm bit */
  77 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
  78
  79 /********** TX ULP door bell *************/
  80 #define DB_TXULP1_OFFSET                0x60
  81 #define DB_TXULP_RING_ID_MASK           0x7FF   /* bits 0 - 10 */
  82 /* Number of tx entries posted */
  83 #define DB_TXULP_NUM_POSTED_SHIFT       (16)    /* bits 16 - 29 */
  84 #define DB_TXULP_NUM_POSTED_MASK        0x3FFF  /* bits 16 - 29 */
  85
  86 /********** RQ(erx) door bell ************/
  87 #define DB_RQ_OFFSET                    0x100
  88 #define DB_RQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
  89 /* Number of rx frags posted */
  90 #define DB_RQ_NUM_POSTED_SHIFT          (24)    /* bits 24 - 31 */
  91
  92 /********** MCC door bell ************/
  93 #define DB_MCCQ_OFFSET                  0x140
  94 #define DB_MCCQ_RING_ID_MASK            0x7FF   /* bits 0 - 10 */
  95 /* Number of entries posted */
  96 #define DB_MCCQ_NUM_POSTED_SHIFT        (16)    /* bits 16 - 29 */
  97
  98 /*
  99  * BE descriptors: host memory data structures whose formats
 100  * are hardwired in BE silicon.
 101  */
 102 /* Event Queue Descriptor */
 103 #define EQ_ENTRY_VALID_MASK             0x1     /* bit 0 */
 104 #define EQ_ENTRY_RES_ID_MASK            0xFFFF  /* bits 16 - 31 */
 105 #define EQ_ENTRY_RES_ID_SHIFT           16
 106 struct be_eq_entry {
 107         u32 evt;
 108 };
 109
 110 /* TX Queue Descriptor */
 111 #define ETH_WRB_FRAG_LEN_MASK           0xFFFF
 112 struct be_eth_wrb {
 113         u32 frag_pa_hi;         /* dword 0 */
 114         u32 frag_pa_lo;         /* dword 1 */
 115         u32 rsvd0;              /* dword 2 */
 116         u32 frag_len;           /* dword 3: bits 0 - 15 */
 117 } __packed;
 118
 119 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
 120  * actual structure is defined as a byte : used to calculate
 121  * offset/shift/mask of each field */
 122 struct amap_eth_hdr_wrb {
 123         u8 rsvd0[32];           /* dword 0 */
 124         u8 rsvd1[32];           /* dword 1 */
 125         u8 complete;            /* dword 2 */
 126         u8 event;
 127         u8 crc;
 128         u8 forward;
 129         u8 ipsec;
 130         u8 mgmt;
 131         u8 ipcs;
 132         u8 udpcs;
 133         u8 tcpcs;
 134         u8 lso;
 135         u8 vlan;
 136         u8 gso[2];
 137         u8 num_wrb[5];
 138         u8 lso_mss[14];
 139         u8 len[16];             /* dword 3 */
 140         u8 vlan_tag[16];
 141 } __packed;
 142
 143 struct be_eth_hdr_wrb {
 144         u32 dw[4];
 145 };
 146
 147 /* TX Compl Queue Descriptor */
 148
 149 /* Pseudo amap definition for eth_tx_compl in which each bit of the
 150  * actual structure is defined as a byte: used to calculate
 151  * offset/shift/mask of each field */
 152 struct amap_eth_tx_compl {
 153         u8 wrb_index[16];       /* dword 0 */
 154         u8 ct[2];               /* dword 0 */
 155         u8 port[2];             /* dword 0 */
 156         u8 rsvd0[8];            /* dword 0 */
 157         u8 status[4];           /* dword 0 */
 158         u8 user_bytes[16];      /* dword 1 */
 159         u8 nwh_bytes[8];        /* dword 1 */
 160         u8 lso;                 /* dword 1 */
 161         u8 cast_enc[2];         /* dword 1 */
 162         u8 rsvd1[5];            /* dword 1 */
 163         u8 rsvd2[32];           /* dword 2 */
 164         u8 pkts[16];            /* dword 3 */
 165         u8 ringid[11];          /* dword 3 */
 166         u8 hash_val[4];         /* dword 3 */
 167         u8 valid;               /* dword 3 */
 168 } __packed;
 169
 170 struct be_eth_tx_compl {
 171         u32 dw[4];
 172 };
 173
 174 /* RX Queue Descriptor */
 175 struct be_eth_rx_d {
 176         u32 fragpa_hi;
 177         u32 fragpa_lo;
 178 };
 179
 180 /* RX Compl Queue Descriptor */
 181
 182 /* Pseudo amap definition for eth_rx_compl in which each bit of the
 183  * actual structure is defined as a byte: used to calculate
 184  * offset/shift/mask of each field */
 185 struct amap_eth_rx_compl {
 186         u8 vlan_tag[16];        /* dword 0 */
 187         u8 pktsize[14];         /* dword 0 */
 188         u8 port;                /* dword 0 */
 189         u8 ip_opt;              /* dword 0 */
 190         u8 err;                 /* dword 1 */
 191         u8 rsshp;               /* dword 1 */
 192         u8 ipf;                 /* dword 1 */
 193         u8 tcpf;                /* dword 1 */
 194         u8 udpf;                /* dword 1 */
 195         u8 ipcksm;              /* dword 1 */
 196         u8 l4_cksm;             /* dword 1 */
 197         u8 ip_version;          /* dword 1 */
 198         u8 macdst[6];           /* dword 1 */
 199         u8 vtp;                 /* dword 1 */
 200         u8 rsvd0;               /* dword 1 */
 201         u8 fragndx[10];         /* dword 1 */
 202         u8 ct[2];               /* dword 1 */
 203         u8 sw;                  /* dword 1 */
 204         u8 numfrags[3];         /* dword 1 */
 205         u8 rss_flush;           /* dword 2 */
 206         u8 cast_enc[2];         /* dword 2 */
 207         u8 vtm;                 /* dword 2 */
 208         u8 rss_bank;            /* dword 2 */
 209         u8 rsvd1[23];           /* dword 2 */
 210         u8 lro_pkt;             /* dword 2 */
 211         u8 rsvd2[2];            /* dword 2 */
 212         u8 valid;               /* dword 2 */
 213         u8 rsshash[32];         /* dword 3 */
 214 } __packed;
 215
 216 struct be_eth_rx_compl {
 217         u32 dw[4];
 218 };
 219
 220 /* Flashrom related descriptors */
 221 #define IMAGE_TYPE_FIRMWARE             160
 222 #define IMAGE_TYPE_BOOTCODE             224
 223 #define IMAGE_TYPE_OPTIONROM            32
 224
 225 #define NUM_FLASHDIR_ENTRIES            32
 226
 227 #define FLASHROM_TYPE_ISCSI_ACTIVE      0
 228 #define FLASHROM_TYPE_BIOS              2
 229 #define FLASHROM_TYPE_PXE_BIOS          3
 230 #define FLASHROM_TYPE_FCOE_BIOS         8
 231 #define FLASHROM_TYPE_ISCSI_BACKUP      9
 232 #define FLASHROM_TYPE_FCOE_FW_ACTIVE    10
 233 #define FLASHROM_TYPE_FCOE_FW_BACKUP    11
 234
 235 #define FLASHROM_OPER_FLASH             1
 236 #define FLASHROM_OPER_SAVE              2
 237
 238 #define FLASH_IMAGE_MAX_SIZE            (1310720) /* Max firmware image size */
 239 #define FLASH_BIOS_IMAGE_MAX_SIZE       (262144)  /* Max OPTION ROM image sz */
 240
 241 /* Offsets for components on Flash. */
 242 #define FLASH_iSCSI_PRIMARY_IMAGE_START (1048576)
 243 #define FLASH_iSCSI_BACKUP_IMAGE_START  (2359296)
 244 #define FLASH_FCoE_PRIMARY_IMAGE_START  (3670016)
 245 #define FLASH_FCoE_BACKUP_IMAGE_START   (4980736)
 246 #define FLASH_iSCSI_BIOS_START          (7340032)
 247 #define FLASH_PXE_BIOS_START            (7864320)
 248 #define FLASH_FCoE_BIOS_START           (524288)
 249
 250 struct controller_id {
 251         u32 vendor;
 252         u32 device;
 253         u32 subvendor;
 254         u32 subdevice;
 255 };
 256
 257 struct flash_file_hdr {
 258         u8 sign[32];
 259         u32 cksum;
 260         u32 antidote;
 261         struct controller_id cont_id;
 262         u32 file_len;
 263         u32 chunk_num;
 264         u32 total_chunks;
 265         u32 num_imgs;
 266         u8 build[24];
 267 };
 268
 269 struct flash_section_hdr {
 270         u32 format_rev;
 271         u32 cksum;
 272         u32 antidote;
 273         u32 build_no;
 274         u8 id_string[64];
 275         u32 active_entry_mask;
 276         u32 valid_entry_mask;
 277         u32 org_content_mask;
 278         u32 rsvd0;
 279         u32 rsvd1;
 280         u32 rsvd2;
 281         u32 rsvd3;
 282         u32 rsvd4;
 283 };
 284
 285 struct flash_section_entry {
 286         u32 type;
 287         u32 offset;
 288         u32 pad_size;
 289         u32 image_size;
 290         u32 cksum;
 291         u32 entry_point;
 292         u32 rsvd0;
 293         u32 rsvd1;
 294         u8 ver_data[32];
 295 };
 296
 297 struct flash_section_info {
 298         u8 cookie[32];
 299         struct flash_section_hdr fsec_hdr;
 300         struct flash_section_entry fsec_entry[32];
 301 };