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x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / drivers / net / mlx4 / fw.c
blob3c16602172fc3ca1b9f40d1b302d2d4cf0512a5f
1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/mlx4/cmd.h>
36 #include <linux/cache.h>
37
38 #include "fw.h"
39 #include "icm.h"
40
41 enum {
42 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
43 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
44 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
45 };
46
47 extern void __buggy_use_of_MLX4_GET(void);
48 extern void __buggy_use_of_MLX4_PUT(void);
49
50 static int enable_qos;
51 module_param(enable_qos, bool, 0444);
52 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
53
54 #define MLX4_GET(dest, source, offset) \
55 do { \
56 void *__p = (char *) (source) + (offset); \
57 switch (sizeof (dest)) { \
58 case 1: (dest) = *(u8 *) __p; break; \
59 case 2: (dest) = be16_to_cpup(__p); break; \
60 case 4: (dest) = be32_to_cpup(__p); break; \
61 case 8: (dest) = be64_to_cpup(__p); break; \
62 default: __buggy_use_of_MLX4_GET(); \
63 } \
64 } while (0)
65
66 #define MLX4_PUT(dest, source, offset) \
67 do { \
68 void *__d = ((char *) (dest) + (offset)); \
69 switch (sizeof(source)) { \
70 case 1: *(u8 *) __d = (source); break; \
71 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
72 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
73 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
74 default: __buggy_use_of_MLX4_PUT(); \
75 } \
76 } while (0)
77
78 static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
79 {
80 static const char *fname[] = {
81 [ 0] = "RC transport",
82 [ 1] = "UC transport",
83 [ 2] = "UD transport",
84 [ 3] = "XRC transport",
85 [ 4] = "reliable multicast",
86 [ 5] = "FCoIB support",
87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
91 [10] = "VMM",
92 [12] = "DPDP",
93 [16] = "MW support",
94 [17] = "APM support",
95 [18] = "Atomic ops support",
96 [19] = "Raw multicast support",
97 [20] = "Address vector port checking support",
98 [21] = "UD multicast support",
99 [24] = "Demand paging support",
100 [25] = "Router support"
101 };
102 int i;
103
104 mlx4_dbg(dev, "DEV_CAP flags:\n");
105 for (i = 0; i < ARRAY_SIZE(fname); ++i)
106 if (fname[i] && (flags & (1 << i)))
107 mlx4_dbg(dev, " %s\n", fname[i]);
108 }
109
110 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
111 {
112 struct mlx4_cmd_mailbox *mailbox;
113 u32 *inbox;
114 int err = 0;
115
116 #define MOD_STAT_CFG_IN_SIZE 0x100
117
118 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
119 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
120
121 mailbox = mlx4_alloc_cmd_mailbox(dev);
122 if (IS_ERR(mailbox))
123 return PTR_ERR(mailbox);
124 inbox = mailbox->buf;
125
126 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
127
128 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
129 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
130
131 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
132 MLX4_CMD_TIME_CLASS_A);
133
134 mlx4_free_cmd_mailbox(dev, mailbox);
135 return err;
136 }
137
138 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
139 {
140 struct mlx4_cmd_mailbox *mailbox;
141 u32 *outbox;
142 u8 field;
143 u16 size;
144 u16 stat_rate;
145 int err;
146 int i;
147
148 #define QUERY_DEV_CAP_OUT_SIZE 0x100
149 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
150 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
151 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
152 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
153 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
154 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
155 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
156 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
157 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
158 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
159 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
160 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
161 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
162 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
163 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
164 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
165 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
166 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
167 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
168 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
169 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
170 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
171 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
172 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
173 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
174 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
175 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
176 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
177 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
178 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
179 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
180 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
181 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
182 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
183 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
184 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
185 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
186 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
187 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
188 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
189 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
190 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
191 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
192 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
193 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
194 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
195 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
196 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
197 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
198 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
199 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
200 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
201 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
202 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
203 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
204 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
205 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
206 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
207 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
208 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
209 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
210
211 mailbox = mlx4_alloc_cmd_mailbox(dev);
212 if (IS_ERR(mailbox))
213 return PTR_ERR(mailbox);
214 outbox = mailbox->buf;
215
216 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
217 MLX4_CMD_TIME_CLASS_A);
218 if (err)
219 goto out;
220
221 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
222 dev_cap->reserved_qps = 1 << (field & 0xf);
223 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
224 dev_cap->max_qps = 1 << (field & 0x1f);
225 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
226 dev_cap->reserved_srqs = 1 << (field >> 4);
227 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
228 dev_cap->max_srqs = 1 << (field & 0x1f);
229 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
230 dev_cap->max_cq_sz = 1 << field;
231 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
232 dev_cap->reserved_cqs = 1 << (field & 0xf);
233 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
234 dev_cap->max_cqs = 1 << (field & 0x1f);
235 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
236 dev_cap->max_mpts = 1 << (field & 0x3f);
237 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
238 dev_cap->reserved_eqs = 1 << (field & 0xf);
239 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
240 dev_cap->max_eqs = 1 << (field & 0xf);
241 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
242 dev_cap->reserved_mtts = 1 << (field >> 4);
243 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
244 dev_cap->max_mrw_sz = 1 << field;
245 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
246 dev_cap->reserved_mrws = 1 << (field & 0xf);
247 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
248 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
249 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
250 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
251 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
252 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
253 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
254 field &= 0x1f;
255 if (!field)
256 dev_cap->max_gso_sz = 0;
257 else
258 dev_cap->max_gso_sz = 1 << field;
259
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
261 dev_cap->max_rdma_global = 1 << (field & 0x3f);
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
263 dev_cap->local_ca_ack_delay = field & 0x1f;
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
265 dev_cap->num_ports = field & 0xf;
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
267 dev_cap->max_msg_sz = 1 << (field & 0x1f);
268 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
269 dev_cap->stat_rate_support = stat_rate;
270 MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
271 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
272 dev_cap->reserved_uars = field >> 4;
273 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
274 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
276 dev_cap->min_page_sz = 1 << field;
277
278 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
279 if (field & 0x80) {
280 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
281 dev_cap->bf_reg_size = 1 << (field & 0x1f);
282 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
283 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
284 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
285 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
286 } else {
287 dev_cap->bf_reg_size = 0;
288 mlx4_dbg(dev, "BlueFlame not available\n");
289 }
290
291 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
292 dev_cap->max_sq_sg = field;
293 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
294 dev_cap->max_sq_desc_sz = size;
295
296 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
297 dev_cap->max_qp_per_mcg = 1 << field;
298 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
299 dev_cap->reserved_mgms = field & 0xf;
300 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
301 dev_cap->max_mcgs = 1 << field;
302 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
303 dev_cap->reserved_pds = field >> 4;
304 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
305 dev_cap->max_pds = 1 << (field & 0x3f);
306
307 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
308 dev_cap->rdmarc_entry_sz = size;
309 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
310 dev_cap->qpc_entry_sz = size;
311 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
312 dev_cap->aux_entry_sz = size;
313 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
314 dev_cap->altc_entry_sz = size;
315 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
316 dev_cap->eqc_entry_sz = size;
317 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
318 dev_cap->cqc_entry_sz = size;
319 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
320 dev_cap->srq_entry_sz = size;
321 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
322 dev_cap->cmpt_entry_sz = size;
323 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
324 dev_cap->mtt_entry_sz = size;
325 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
326 dev_cap->dmpt_entry_sz = size;
327
328 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
329 dev_cap->max_srq_sz = 1 << field;
330 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
331 dev_cap->max_qp_sz = 1 << field;
332 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
333 dev_cap->resize_srq = field & 1;
334 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
335 dev_cap->max_rq_sg = field;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
337 dev_cap->max_rq_desc_sz = size;
338
339 MLX4_GET(dev_cap->bmme_flags, outbox,
340 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
341 MLX4_GET(dev_cap->reserved_lkey, outbox,
342 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
343 MLX4_GET(dev_cap->max_icm_sz, outbox,
344 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
345
346 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
347 for (i = 1; i <= dev_cap->num_ports; ++i) {
348 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
349 dev_cap->max_vl[i] = field >> 4;
350 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
351 dev_cap->ib_mtu[i] = field >> 4;
352 dev_cap->max_port_width[i] = field & 0xf;
353 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
354 dev_cap->max_gids[i] = 1 << (field & 0xf);
355 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
356 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
357 }
358 } else {
359 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
360 #define QUERY_PORT_MTU_OFFSET 0x01
361 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
362 #define QUERY_PORT_WIDTH_OFFSET 0x06
363 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
364 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
365 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
366 #define QUERY_PORT_MAC_OFFSET 0x10
367
368 for (i = 1; i <= dev_cap->num_ports; ++i) {
369 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
370 MLX4_CMD_TIME_CLASS_B);
371 if (err)
372 goto out;
373
374 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
375 dev_cap->supported_port_types[i] = field & 3;
376 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
377 dev_cap->ib_mtu[i] = field & 0xf;
378 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
379 dev_cap->max_port_width[i] = field & 0xf;
380 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
381 dev_cap->max_gids[i] = 1 << (field >> 4);
382 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
383 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
384 dev_cap->max_vl[i] = field & 0xf;
385 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
386 dev_cap->log_max_macs[i] = field & 0xf;
387 dev_cap->log_max_vlans[i] = field >> 4;
388 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
389 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
390 }
391 }
392
393 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
394 dev_cap->bmme_flags, dev_cap->reserved_lkey);
395
396 /*
397 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
398 * we can't use any EQs whose doorbell falls on that page,
399 * even if the EQ itself isn't reserved.
400 */
401 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
402 dev_cap->reserved_eqs);
403
404 mlx4_dbg(dev, "Max ICM size %lld MB\n",
405 (unsigned long long) dev_cap->max_icm_sz >> 20);
406 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
407 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
408 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
409 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
410 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
411 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
412 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
413 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
414 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
415 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
416 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
417 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
418 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
419 dev_cap->max_pds, dev_cap->reserved_mgms);
420 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
421 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
422 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
423 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
424 dev_cap->max_port_width[1]);
425 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
426 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
427 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
428 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
429 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
430
431 dump_dev_cap_flags(dev, dev_cap->flags);
432
433 out:
434 mlx4_free_cmd_mailbox(dev, mailbox);
435 return err;
436 }
437
438 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
439 {
440 struct mlx4_cmd_mailbox *mailbox;
441 struct mlx4_icm_iter iter;
442 __be64 *pages;
443 int lg;
444 int nent = 0;
445 int i;
446 int err = 0;
447 int ts = 0, tc = 0;
448
449 mailbox = mlx4_alloc_cmd_mailbox(dev);
450 if (IS_ERR(mailbox))
451 return PTR_ERR(mailbox);
452 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
453 pages = mailbox->buf;
454
455 for (mlx4_icm_first(icm, &iter);
456 !mlx4_icm_last(&iter);
457 mlx4_icm_next(&iter)) {
458 /*
459 * We have to pass pages that are aligned to their
460 * size, so find the least significant 1 in the
461 * address or size and use that as our log2 size.
462 */
463 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
464 if (lg < MLX4_ICM_PAGE_SHIFT) {
465 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
466 MLX4_ICM_PAGE_SIZE,
467 (unsigned long long) mlx4_icm_addr(&iter),
468 mlx4_icm_size(&iter));
469 err = -EINVAL;
470 goto out;
471 }
472
473 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
474 if (virt != -1) {
475 pages[nent * 2] = cpu_to_be64(virt);
476 virt += 1 << lg;
477 }
478
479 pages[nent * 2 + 1] =
480 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
481 (lg - MLX4_ICM_PAGE_SHIFT));
482 ts += 1 << (lg - 10);
483 ++tc;
484
485 if (++nent == MLX4_MAILBOX_SIZE / 16) {
486 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
487 MLX4_CMD_TIME_CLASS_B);
488 if (err)
489 goto out;
490 nent = 0;
491 }
492 }
493 }
494
495 if (nent)
496 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
497 if (err)
498 goto out;
499
500 switch (op) {
501 case MLX4_CMD_MAP_FA:
502 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
503 break;
504 case MLX4_CMD_MAP_ICM_AUX:
505 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
506 break;
507 case MLX4_CMD_MAP_ICM:
508 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
509 tc, ts, (unsigned long long) virt - (ts << 10));
510 break;
511 }
512
513 out:
514 mlx4_free_cmd_mailbox(dev, mailbox);
515 return err;
516 }
517
518 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
519 {
520 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
521 }
522
523 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
524 {
525 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
526 }
527
528
529 int mlx4_RUN_FW(struct mlx4_dev *dev)
530 {
531 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
532 }
533
534 int mlx4_QUERY_FW(struct mlx4_dev *dev)
535 {
536 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
537 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
538 struct mlx4_cmd_mailbox *mailbox;
539 u32 *outbox;
540 int err = 0;
541 u64 fw_ver;
542 u16 cmd_if_rev;
543 u8 lg;
544
545 #define QUERY_FW_OUT_SIZE 0x100
546 #define QUERY_FW_VER_OFFSET 0x00
547 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
548 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
549 #define QUERY_FW_ERR_START_OFFSET 0x30
550 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
551 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
552
553 #define QUERY_FW_SIZE_OFFSET 0x00
554 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
555 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
556
557 mailbox = mlx4_alloc_cmd_mailbox(dev);
558 if (IS_ERR(mailbox))
559 return PTR_ERR(mailbox);
560 outbox = mailbox->buf;
561
562 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
563 MLX4_CMD_TIME_CLASS_A);
564 if (err)
565 goto out;
566
567 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
568 /*
569 * FW subminor version is at more significant bits than minor
570 * version, so swap here.
571 */
572 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
573 ((fw_ver & 0xffff0000ull) >> 16) |
574 ((fw_ver & 0x0000ffffull) << 16);
575
576 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
577 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
578 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
579 mlx4_err(dev, "Installed FW has unsupported "
580 "command interface revision %d.\n",
581 cmd_if_rev);
582 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
583 (int) (dev->caps.fw_ver >> 32),
584 (int) (dev->caps.fw_ver >> 16) & 0xffff,
585 (int) dev->caps.fw_ver & 0xffff);
586 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
587 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
588 err = -ENODEV;
589 goto out;
590 }
591
592 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
593 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
594
595 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
596 cmd->max_cmds = 1 << lg;
597
598 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
599 (int) (dev->caps.fw_ver >> 32),
600 (int) (dev->caps.fw_ver >> 16) & 0xffff,
601 (int) dev->caps.fw_ver & 0xffff,
602 cmd_if_rev, cmd->max_cmds);
603
604 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
605 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
606 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
607 fw->catas_bar = (fw->catas_bar >> 6) * 2;
608
609 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
610 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
611
612 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
613 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
614 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
615 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
616
617 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
618
619 /*
620 * Round up number of system pages needed in case
621 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
622 */
623 fw->fw_pages =
624 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
625 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
626
627 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
628 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
629
630 out:
631 mlx4_free_cmd_mailbox(dev, mailbox);
632 return err;
633 }
634
635 static void get_board_id(void *vsd, char *board_id)
636 {
637 int i;
638
639 #define VSD_OFFSET_SIG1 0x00
640 #define VSD_OFFSET_SIG2 0xde
641 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
642 #define VSD_OFFSET_TS_BOARD_ID 0x20
643
644 #define VSD_SIGNATURE_TOPSPIN 0x5ad
645
646 memset(board_id, 0, MLX4_BOARD_ID_LEN);
647
648 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
649 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
650 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
651 } else {
652 /*
653 * The board ID is a string but the firmware byte
654 * swaps each 4-byte word before passing it back to
655 * us. Therefore we need to swab it before printing.
656 */
657 for (i = 0; i < 4; ++i)
658 ((u32 *) board_id)[i] =
659 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
660 }
661 }
662
663 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
664 {
665 struct mlx4_cmd_mailbox *mailbox;
666 u32 *outbox;
667 int err;
668
669 #define QUERY_ADAPTER_OUT_SIZE 0x100
670 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
671 #define QUERY_ADAPTER_VSD_OFFSET 0x20
672
673 mailbox = mlx4_alloc_cmd_mailbox(dev);
674 if (IS_ERR(mailbox))
675 return PTR_ERR(mailbox);
676 outbox = mailbox->buf;
677
678 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
679 MLX4_CMD_TIME_CLASS_A);
680 if (err)
681 goto out;
682
683 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
684
685 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
686 adapter->board_id);
687
688 out:
689 mlx4_free_cmd_mailbox(dev, mailbox);
690 return err;
691 }
692
693 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
694 {
695 struct mlx4_cmd_mailbox *mailbox;
696 __be32 *inbox;
697 int err;
698
699 #define INIT_HCA_IN_SIZE 0x200
700 #define INIT_HCA_VERSION_OFFSET 0x000
701 #define INIT_HCA_VERSION 2
702 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
703 #define INIT_HCA_FLAGS_OFFSET 0x014
704 #define INIT_HCA_QPC_OFFSET 0x020
705 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
706 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
707 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
708 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
709 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
710 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
711 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
712 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
713 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
714 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
715 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
716 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
717 #define INIT_HCA_MCAST_OFFSET 0x0c0
718 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
719 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
720 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
721 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
722 #define INIT_HCA_TPT_OFFSET 0x0f0
723 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
724 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
725 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
726 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
727 #define INIT_HCA_UAR_OFFSET 0x120
728 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
729 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
730
731 mailbox = mlx4_alloc_cmd_mailbox(dev);
732 if (IS_ERR(mailbox))
733 return PTR_ERR(mailbox);
734 inbox = mailbox->buf;
735
736 memset(inbox, 0, INIT_HCA_IN_SIZE);
737
738 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
739
740 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
741 (ilog2(cache_line_size()) - 4) << 5;
742
743 #if defined(__LITTLE_ENDIAN)
744 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
745 #elif defined(__BIG_ENDIAN)
746 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
747 #else
748 #error Host endianness not defined
749 #endif
750 /* Check port for UD address vector: */
751 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
752
753 /* Enable IPoIB checksumming if we can: */
754 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
755 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
756
757 /* Enable QoS support if module parameter set */
758 if (enable_qos)
759 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
760
761 /* QPC/EEC/CQC/EQC/RDMARC attributes */
762
763 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
764 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
765 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
766 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
767 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
768 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
769 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
770 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
771 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
772 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
773 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
774 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
775
776 /* multicast attributes */
777
778 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
779 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
780 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
781 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
782
783 /* TPT attributes */
784
785 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
786 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
787 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
788 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
789
790 /* UAR attributes */
791
792 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
793 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
794
795 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
796
797 if (err)
798 mlx4_err(dev, "INIT_HCA returns %d\n", err);
799
800 mlx4_free_cmd_mailbox(dev, mailbox);
801 return err;
802 }
803
804 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
805 {
806 struct mlx4_cmd_mailbox *mailbox;
807 u32 *inbox;
808 int err;
809 u32 flags;
810 u16 field;
811
812 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
813 #define INIT_PORT_IN_SIZE 256
814 #define INIT_PORT_FLAGS_OFFSET 0x00
815 #define INIT_PORT_FLAG_SIG (1 << 18)
816 #define INIT_PORT_FLAG_NG (1 << 17)
817 #define INIT_PORT_FLAG_G0 (1 << 16)
818 #define INIT_PORT_VL_SHIFT 4
819 #define INIT_PORT_PORT_WIDTH_SHIFT 8
820 #define INIT_PORT_MTU_OFFSET 0x04
821 #define INIT_PORT_MAX_GID_OFFSET 0x06
822 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
823 #define INIT_PORT_GUID0_OFFSET 0x10
824 #define INIT_PORT_NODE_GUID_OFFSET 0x18
825 #define INIT_PORT_SI_GUID_OFFSET 0x20
826
827 mailbox = mlx4_alloc_cmd_mailbox(dev);
828 if (IS_ERR(mailbox))
829 return PTR_ERR(mailbox);
830 inbox = mailbox->buf;
831
832 memset(inbox, 0, INIT_PORT_IN_SIZE);
833
834 flags = 0;
835 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
836 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
837 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
838
839 field = 128 << dev->caps.ib_mtu_cap[port];
840 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
841 field = dev->caps.gid_table_len[port];
842 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
843 field = dev->caps.pkey_table_len[port];
844 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
845
846 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
847 MLX4_CMD_TIME_CLASS_A);
848
849 mlx4_free_cmd_mailbox(dev, mailbox);
850 } else
851 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
852 MLX4_CMD_TIME_CLASS_A);
853
854 return err;
855 }
856 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
857
858 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
859 {
860 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
861 }
862 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
863
864 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
865 {
866 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
867 }
868
869 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
870 {
871 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
872 MLX4_CMD_SET_ICM_SIZE,
873 MLX4_CMD_TIME_CLASS_A);
874 if (ret)
875 return ret;
876
877 /*
878 * Round up number of system pages needed in case
879 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
880 */
881 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
882 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
883
884 return 0;
885 }
886
887 int mlx4_NOP(struct mlx4_dev *dev)
888 {
889 /* Input modifier of 0x1f means "finish as soon as possible." */
890 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
891 }
Linux with added FPC-III support