?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86/amd-iommu: Add function to complete a tlb flush
[linux/fpc-iii.git] / drivers / net / tulip / tulip_core.c
blob6b2330e4206e12467c7e28c08e155a4c5bccf668
1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
2
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
11
12 Please submit bugs to http://bugzilla.kernel.org/ .
13 */
14
15
16 #define DRV_NAME "tulip"
17 #ifdef CONFIG_TULIP_NAPI
18 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
19 #else
20 #define DRV_VERSION "1.1.15"
21 #endif
22 #define DRV_RELDATE "Feb 27, 2007"
23
24
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include "tulip.h"
28 #include <linux/init.h>
29 #include <linux/etherdevice.h>
30 #include <linux/delay.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/crc32.h>
34 #include <asm/unaligned.h>
35 #include <asm/uaccess.h>
36
37 #ifdef CONFIG_SPARC
38 #include <asm/prom.h>
39 #endif
40
41 static char version[] __devinitdata =
42 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
43
44
45 /* A few user-configurable values. */
46
47 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
48 static unsigned int max_interrupt_work = 25;
49
50 #define MAX_UNITS 8
51 /* Used to pass the full-duplex flag, etc. */
52 static int full_duplex[MAX_UNITS];
53 static int options[MAX_UNITS];
54 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
55
56 /* The possible media types that can be set in options[] are: */
57 const char * const medianame[32] = {
58 "10baseT", "10base2", "AUI", "100baseTx",
59 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
60 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
61 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
62 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
63 "","","","", "","","","", "","","","Transceiver reset",
64 };
65
66 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
67 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
68 || defined(CONFIG_SPARC) || defined(__ia64__) \
69 || defined(__sh__) || defined(__mips__)
70 static int rx_copybreak = 1518;
71 #else
72 static int rx_copybreak = 100;
73 #endif
74
75 /*
76 Set the bus performance register.
77 Typical: Set 16 longword cache alignment, no burst limit.
78 Cache alignment bits 15:14 Burst length 13:8
79 0000 No alignment 0x00000000 unlimited 0800 8 longwords
80 4000 8 longwords 0100 1 longword 1000 16 longwords
81 8000 16 longwords 0200 2 longwords 2000 32 longwords
82 C000 32 longwords 0400 4 longwords
83 Warning: many older 486 systems are broken and require setting 0x00A04800
84 8 longword cache alignment, 8 longword burst.
85 ToDo: Non-Intel setting could be better.
86 */
87
88 #if defined(__alpha__) || defined(__ia64__)
89 static int csr0 = 0x01A00000 | 0xE000;
90 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
91 static int csr0 = 0x01A00000 | 0x8000;
92 #elif defined(CONFIG_SPARC) || defined(__hppa__)
93 /* The UltraSparc PCI controllers will disconnect at every 64-byte
94 * crossing anyways so it makes no sense to tell Tulip to burst
95 * any more than that.
96 */
97 static int csr0 = 0x01A00000 | 0x9000;
98 #elif defined(__arm__) || defined(__sh__)
99 static int csr0 = 0x01A00000 | 0x4800;
100 #elif defined(__mips__)
101 static int csr0 = 0x00200000 | 0x4000;
102 #else
103 #warning Processor architecture undefined!
104 static int csr0 = 0x00A00000 | 0x4800;
105 #endif
106
107 /* Operational parameters that usually are not changed. */
108 /* Time in jiffies before concluding the transmitter is hung. */
109 #define TX_TIMEOUT (4*HZ)
110
111
112 MODULE_AUTHOR("The Linux Kernel Team");
113 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
114 MODULE_LICENSE("GPL");
115 MODULE_VERSION(DRV_VERSION);
116 module_param(tulip_debug, int, 0);
117 module_param(max_interrupt_work, int, 0);
118 module_param(rx_copybreak, int, 0);
119 module_param(csr0, int, 0);
120 module_param_array(options, int, NULL, 0);
121 module_param_array(full_duplex, int, NULL, 0);
122
123 #define PFX DRV_NAME ": "
124
125 #ifdef TULIP_DEBUG
126 int tulip_debug = TULIP_DEBUG;
127 #else
128 int tulip_debug = 1;
129 #endif
130
131 static void tulip_timer(unsigned long data)
132 {
133 struct net_device *dev = (struct net_device *)data;
134 struct tulip_private *tp = netdev_priv(dev);
135
136 if (netif_running(dev))
137 schedule_work(&tp->media_work);
138 }
139
140 /*
141 * This table use during operation for capabilities and media timer.
142 *
143 * It is indexed via the values in 'enum chips'
144 */
145
146 struct tulip_chip_table tulip_tbl[] = {
147 { }, /* placeholder for array, slot unused currently */
148 { }, /* placeholder for array, slot unused currently */
149
150 /* DC21140 */
151 { "Digital DS21140 Tulip", 128, 0x0001ebef,
152 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
153 tulip_media_task },
154
155 /* DC21142, DC21143 */
156 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
157 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
158 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
159
160 /* LC82C168 */
161 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
162 HAS_MII | HAS_PNICNWAY, pnic_timer, },
163
164 /* MX98713 */
165 { "Macronix 98713 PMAC", 128, 0x0001ebef,
166 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
167
168 /* MX98715 */
169 { "Macronix 98715 PMAC", 256, 0x0001ebef,
170 HAS_MEDIA_TABLE, mxic_timer, },
171
172 /* MX98725 */
173 { "Macronix 98725 PMAC", 256, 0x0001ebef,
174 HAS_MEDIA_TABLE, mxic_timer, },
175
176 /* AX88140 */
177 { "ASIX AX88140", 128, 0x0001fbff,
178 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
179 | IS_ASIX, tulip_timer, tulip_media_task },
180
181 /* PNIC2 */
182 { "Lite-On PNIC-II", 256, 0x0801fbff,
183 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
184
185 /* COMET */
186 { "ADMtek Comet", 256, 0x0001abef,
187 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
188
189 /* COMPEX9881 */
190 { "Compex 9881 PMAC", 128, 0x0001ebef,
191 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
192
193 /* I21145 */
194 { "Intel DS21145 Tulip", 128, 0x0801fbff,
195 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
196 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
197
198 /* DM910X */
199 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
200 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
201 tulip_timer, tulip_media_task },
202
203 /* RS7112 */
204 { "Conexant LANfinity", 256, 0x0001ebef,
205 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
206
207 };
208
209
210 static struct pci_device_id tulip_pci_tbl[] = {
211 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
212 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
213 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
214 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
215 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
216 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
217 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
218 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
219 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
220 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
221 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
230 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
231 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
232 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
233 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
234 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
235 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
237 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
240 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
245 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
246 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { } /* terminate list */
248 };
249 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
250
251
252 /* A full-duplex map for media types. */
253 const char tulip_media_cap[32] =
254 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
255
256 static void tulip_tx_timeout(struct net_device *dev);
257 static void tulip_init_ring(struct net_device *dev);
258 static void tulip_free_ring(struct net_device *dev);
259 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
260 struct net_device *dev);
261 static int tulip_open(struct net_device *dev);
262 static int tulip_close(struct net_device *dev);
263 static void tulip_up(struct net_device *dev);
264 static void tulip_down(struct net_device *dev);
265 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
266 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
267 static void set_rx_mode(struct net_device *dev);
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269 static void poll_tulip(struct net_device *dev);
270 #endif
271
272 static void tulip_set_power_state (struct tulip_private *tp,
273 int sleep, int snooze)
274 {
275 if (tp->flags & HAS_ACPI) {
276 u32 tmp, newtmp;
277 pci_read_config_dword (tp->pdev, CFDD, &tmp);
278 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
279 if (sleep)
280 newtmp |= CFDD_Sleep;
281 else if (snooze)
282 newtmp |= CFDD_Snooze;
283 if (tmp != newtmp)
284 pci_write_config_dword (tp->pdev, CFDD, newtmp);
285 }
286
287 }
288
289
290 static void tulip_up(struct net_device *dev)
291 {
292 struct tulip_private *tp = netdev_priv(dev);
293 void __iomem *ioaddr = tp->base_addr;
294 int next_tick = 3*HZ;
295 u32 reg;
296 int i;
297
298 #ifdef CONFIG_TULIP_NAPI
299 napi_enable(&tp->napi);
300 #endif
301
302 /* Wake the chip from sleep/snooze mode. */
303 tulip_set_power_state (tp, 0, 0);
304
305 /* On some chip revs we must set the MII/SYM port before the reset!? */
306 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
307 iowrite32(0x00040000, ioaddr + CSR6);
308
309 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
310 iowrite32(0x00000001, ioaddr + CSR0);
311 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
312 udelay(100);
313
314 /* Deassert reset.
315 Wait the specified 50 PCI cycles after a reset by initializing
316 Tx and Rx queues and the address filter list. */
317 iowrite32(tp->csr0, ioaddr + CSR0);
318 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
319 udelay(100);
320
321 if (tulip_debug > 1)
322 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
323
324 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
325 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
326 tp->cur_rx = tp->cur_tx = 0;
327 tp->dirty_rx = tp->dirty_tx = 0;
328
329 if (tp->flags & MC_HASH_ONLY) {
330 u32 addr_low = get_unaligned_le32(dev->dev_addr);
331 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
332 if (tp->chip_id == AX88140) {
333 iowrite32(0, ioaddr + CSR13);
334 iowrite32(addr_low, ioaddr + CSR14);
335 iowrite32(1, ioaddr + CSR13);
336 iowrite32(addr_high, ioaddr + CSR14);
337 } else if (tp->flags & COMET_MAC_ADDR) {
338 iowrite32(addr_low, ioaddr + 0xA4);
339 iowrite32(addr_high, ioaddr + 0xA8);
340 iowrite32(0, ioaddr + 0xAC);
341 iowrite32(0, ioaddr + 0xB0);
342 }
343 } else {
344 /* This is set_rx_mode(), but without starting the transmitter. */
345 u16 *eaddrs = (u16 *)dev->dev_addr;
346 u16 *setup_frm = &tp->setup_frame[15*6];
347 dma_addr_t mapping;
348
349 /* 21140 bug: you must add the broadcast address. */
350 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
351 /* Fill the final entry of the table with our physical address. */
352 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
353 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
354 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
355
356 mapping = pci_map_single(tp->pdev, tp->setup_frame,
357 sizeof(tp->setup_frame),
358 PCI_DMA_TODEVICE);
359 tp->tx_buffers[tp->cur_tx].skb = NULL;
360 tp->tx_buffers[tp->cur_tx].mapping = mapping;
361
362 /* Put the setup frame on the Tx list. */
363 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
364 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
365 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
366
367 tp->cur_tx++;
368 }
369
370 tp->saved_if_port = dev->if_port;
371 if (dev->if_port == 0)
372 dev->if_port = tp->default_port;
373
374 /* Allow selecting a default media. */
375 i = 0;
376 if (tp->mtable == NULL)
377 goto media_picked;
378 if (dev->if_port) {
379 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
380 (dev->if_port == 12 ? 0 : dev->if_port);
381 for (i = 0; i < tp->mtable->leafcount; i++)
382 if (tp->mtable->mleaf[i].media == looking_for) {
383 printk(KERN_INFO "%s: Using user-specified media %s.\n",
384 dev->name, medianame[dev->if_port]);
385 goto media_picked;
386 }
387 }
388 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
389 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
390 for (i = 0; i < tp->mtable->leafcount; i++)
391 if (tp->mtable->mleaf[i].media == looking_for) {
392 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
393 dev->name, medianame[looking_for]);
394 goto media_picked;
395 }
396 }
397 /* Start sensing first non-full-duplex media. */
398 for (i = tp->mtable->leafcount - 1;
399 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
400 ;
401 media_picked:
402
403 tp->csr6 = 0;
404 tp->cur_index = i;
405 tp->nwayset = 0;
406
407 if (dev->if_port) {
408 if (tp->chip_id == DC21143 &&
409 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
410 /* We must reset the media CSRs when we force-select MII mode. */
411 iowrite32(0x0000, ioaddr + CSR13);
412 iowrite32(0x0000, ioaddr + CSR14);
413 iowrite32(0x0008, ioaddr + CSR15);
414 }
415 tulip_select_media(dev, 1);
416 } else if (tp->chip_id == DC21142) {
417 if (tp->mii_cnt) {
418 tulip_select_media(dev, 1);
419 if (tulip_debug > 1)
420 printk(KERN_INFO "%s: Using MII transceiver %d, status "
421 "%4.4x.\n",
422 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
423 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
424 tp->csr6 = csr6_mask_hdcap;
425 dev->if_port = 11;
426 iowrite32(0x0000, ioaddr + CSR13);
427 iowrite32(0x0000, ioaddr + CSR14);
428 } else
429 t21142_start_nway(dev);
430 } else if (tp->chip_id == PNIC2) {
431 /* for initial startup advertise 10/100 Full and Half */
432 tp->sym_advertise = 0x01E0;
433 /* enable autonegotiate end interrupt */
434 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
435 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
436 pnic2_start_nway(dev);
437 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
438 if (tp->mii_cnt) {
439 dev->if_port = 11;
440 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
441 iowrite32(0x0001, ioaddr + CSR15);
442 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
443 pnic_do_nway(dev);
444 else {
445 /* Start with 10mbps to do autonegotiation. */
446 iowrite32(0x32, ioaddr + CSR12);
447 tp->csr6 = 0x00420000;
448 iowrite32(0x0001B078, ioaddr + 0xB8);
449 iowrite32(0x0201B078, ioaddr + 0xB8);
450 next_tick = 1*HZ;
451 }
452 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
453 && ! tp->medialock) {
454 dev->if_port = 0;
455 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
456 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
457 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
458 /* Provided by BOLO, Macronix - 12/10/1998. */
459 dev->if_port = 0;
460 tp->csr6 = 0x01a80200;
461 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
462 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
463 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
464 /* Enable automatic Tx underrun recovery. */
465 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
466 dev->if_port = tp->mii_cnt ? 11 : 0;
467 tp->csr6 = 0x00040000;
468 } else if (tp->chip_id == AX88140) {
469 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
470 } else
471 tulip_select_media(dev, 1);
472
473 /* Start the chip's Tx to process setup frame. */
474 tulip_stop_rxtx(tp);
475 barrier();
476 udelay(5);
477 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
478
479 /* Enable interrupts by setting the interrupt mask. */
480 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
481 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
482 tulip_start_rxtx(tp);
483 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
484
485 if (tulip_debug > 2) {
486 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
487 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
488 ioread32(ioaddr + CSR6));
489 }
490
491 /* Set the timer to switch to check for link beat and perhaps switch
492 to an alternate media type. */
493 tp->timer.expires = RUN_AT(next_tick);
494 add_timer(&tp->timer);
495 #ifdef CONFIG_TULIP_NAPI
496 init_timer(&tp->oom_timer);
497 tp->oom_timer.data = (unsigned long)dev;
498 tp->oom_timer.function = oom_timer;
499 #endif
500 }
501
502 static int
503 tulip_open(struct net_device *dev)
504 {
505 int retval;
506
507 tulip_init_ring (dev);
508
509 retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev);
510 if (retval)
511 goto free_ring;
512
513 tulip_up (dev);
514
515 netif_start_queue (dev);
516
517 return 0;
518
519 free_ring:
520 tulip_free_ring (dev);
521 return retval;
522 }
523
524
525 static void tulip_tx_timeout(struct net_device *dev)
526 {
527 struct tulip_private *tp = netdev_priv(dev);
528 void __iomem *ioaddr = tp->base_addr;
529 unsigned long flags;
530
531 spin_lock_irqsave (&tp->lock, flags);
532
533 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
534 /* Do nothing -- the media monitor should handle this. */
535 if (tulip_debug > 1)
536 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
537 dev->name);
538 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
539 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
540 || tp->chip_id == DM910X) {
541 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
542 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
543 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
544 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
545 tp->timeout_recovery = 1;
546 schedule_work(&tp->media_work);
547 goto out_unlock;
548 } else if (tp->chip_id == PNIC2) {
549 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
550 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
551 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
552 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
553 } else {
554 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
555 "%8.8x, resetting...\n",
556 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
557 dev->if_port = 0;
558 }
559
560 #if defined(way_too_many_messages)
561 if (tulip_debug > 3) {
562 int i;
563 for (i = 0; i < RX_RING_SIZE; i++) {
564 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
565 int j;
566 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
567 "%2.2x %2.2x %2.2x.\n",
568 i, (unsigned int)tp->rx_ring[i].status,
569 (unsigned int)tp->rx_ring[i].length,
570 (unsigned int)tp->rx_ring[i].buffer1,
571 (unsigned int)tp->rx_ring[i].buffer2,
572 buf[0], buf[1], buf[2]);
573 for (j = 0; buf[j] != 0xee && j < 1600; j++)
574 if (j < 100)
575 printk(KERN_CONT " %2.2x", buf[j]);
576 printk(KERN_CONT " j=%d.\n", j);
577 }
578 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
579 for (i = 0; i < RX_RING_SIZE; i++)
580 printk(KERN_CONT " %8.8x",
581 (unsigned int)tp->rx_ring[i].status);
582 printk(KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
583 for (i = 0; i < TX_RING_SIZE; i++)
584 printk(KERN_CONT " %8.8x", (unsigned int)tp->tx_ring[i].status);
585 printk(KERN_CONT "\n");
586 }
587 #endif
588
589 tulip_tx_timeout_complete(tp, ioaddr);
590
591 out_unlock:
592 spin_unlock_irqrestore (&tp->lock, flags);
593 dev->trans_start = jiffies;
594 netif_wake_queue (dev);
595 }
596
597
598 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
599 static void tulip_init_ring(struct net_device *dev)
600 {
601 struct tulip_private *tp = netdev_priv(dev);
602 int i;
603
604 tp->susp_rx = 0;
605 tp->ttimer = 0;
606 tp->nir = 0;
607
608 for (i = 0; i < RX_RING_SIZE; i++) {
609 tp->rx_ring[i].status = 0x00000000;
610 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
611 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
612 tp->rx_buffers[i].skb = NULL;
613 tp->rx_buffers[i].mapping = 0;
614 }
615 /* Mark the last entry as wrapping the ring. */
616 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
617 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
618
619 for (i = 0; i < RX_RING_SIZE; i++) {
620 dma_addr_t mapping;
621
622 /* Note the receive buffer must be longword aligned.
623 dev_alloc_skb() provides 16 byte alignment. But do *not*
624 use skb_reserve() to align the IP header! */
625 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
626 tp->rx_buffers[i].skb = skb;
627 if (skb == NULL)
628 break;
629 mapping = pci_map_single(tp->pdev, skb->data,
630 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
631 tp->rx_buffers[i].mapping = mapping;
632 skb->dev = dev; /* Mark as being used by this device. */
633 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
634 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
635 }
636 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
637
638 /* The Tx buffer descriptor is filled in as needed, but we
639 do need to clear the ownership bit. */
640 for (i = 0; i < TX_RING_SIZE; i++) {
641 tp->tx_buffers[i].skb = NULL;
642 tp->tx_buffers[i].mapping = 0;
643 tp->tx_ring[i].status = 0x00000000;
644 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
645 }
646 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
647 }
648
649 static netdev_tx_t
650 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
651 {
652 struct tulip_private *tp = netdev_priv(dev);
653 int entry;
654 u32 flag;
655 dma_addr_t mapping;
656 unsigned long flags;
657
658 spin_lock_irqsave(&tp->lock, flags);
659
660 /* Calculate the next Tx descriptor entry. */
661 entry = tp->cur_tx % TX_RING_SIZE;
662
663 tp->tx_buffers[entry].skb = skb;
664 mapping = pci_map_single(tp->pdev, skb->data,
665 skb->len, PCI_DMA_TODEVICE);
666 tp->tx_buffers[entry].mapping = mapping;
667 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
668
669 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
670 flag = 0x60000000; /* No interrupt */
671 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
672 flag = 0xe0000000; /* Tx-done intr. */
673 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
674 flag = 0x60000000; /* No Tx-done intr. */
675 } else { /* Leave room for set_rx_mode() to fill entries. */
676 flag = 0xe0000000; /* Tx-done intr. */
677 netif_stop_queue(dev);
678 }
679 if (entry == TX_RING_SIZE-1)
680 flag = 0xe0000000 | DESC_RING_WRAP;
681
682 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
683 /* if we were using Transmit Automatic Polling, we would need a
684 * wmb() here. */
685 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
686 wmb();
687
688 tp->cur_tx++;
689
690 /* Trigger an immediate transmit demand. */
691 iowrite32(0, tp->base_addr + CSR1);
692
693 spin_unlock_irqrestore(&tp->lock, flags);
694
695 dev->trans_start = jiffies;
696
697 return NETDEV_TX_OK;
698 }
699
700 static void tulip_clean_tx_ring(struct tulip_private *tp)
701 {
702 unsigned int dirty_tx;
703
704 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
705 dirty_tx++) {
706 int entry = dirty_tx % TX_RING_SIZE;
707 int status = le32_to_cpu(tp->tx_ring[entry].status);
708
709 if (status < 0) {
710 tp->stats.tx_errors++; /* It wasn't Txed */
711 tp->tx_ring[entry].status = 0;
712 }
713
714 /* Check for Tx filter setup frames. */
715 if (tp->tx_buffers[entry].skb == NULL) {
716 /* test because dummy frames not mapped */
717 if (tp->tx_buffers[entry].mapping)
718 pci_unmap_single(tp->pdev,
719 tp->tx_buffers[entry].mapping,
720 sizeof(tp->setup_frame),
721 PCI_DMA_TODEVICE);
722 continue;
723 }
724
725 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
726 tp->tx_buffers[entry].skb->len,
727 PCI_DMA_TODEVICE);
728
729 /* Free the original skb. */
730 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
731 tp->tx_buffers[entry].skb = NULL;
732 tp->tx_buffers[entry].mapping = 0;
733 }
734 }
735
736 static void tulip_down (struct net_device *dev)
737 {
738 struct tulip_private *tp = netdev_priv(dev);
739 void __iomem *ioaddr = tp->base_addr;
740 unsigned long flags;
741
742 cancel_work_sync(&tp->media_work);
743
744 #ifdef CONFIG_TULIP_NAPI
745 napi_disable(&tp->napi);
746 #endif
747
748 del_timer_sync (&tp->timer);
749 #ifdef CONFIG_TULIP_NAPI
750 del_timer_sync (&tp->oom_timer);
751 #endif
752 spin_lock_irqsave (&tp->lock, flags);
753
754 /* Disable interrupts by clearing the interrupt mask. */
755 iowrite32 (0x00000000, ioaddr + CSR7);
756
757 /* Stop the Tx and Rx processes. */
758 tulip_stop_rxtx(tp);
759
760 /* prepare receive buffers */
761 tulip_refill_rx(dev);
762
763 /* release any unconsumed transmit buffers */
764 tulip_clean_tx_ring(tp);
765
766 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
767 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
768
769 spin_unlock_irqrestore (&tp->lock, flags);
770
771 init_timer(&tp->timer);
772 tp->timer.data = (unsigned long)dev;
773 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
774
775 dev->if_port = tp->saved_if_port;
776
777 /* Leave the driver in snooze, not sleep, mode. */
778 tulip_set_power_state (tp, 0, 1);
779 }
780
781 static void tulip_free_ring (struct net_device *dev)
782 {
783 struct tulip_private *tp = netdev_priv(dev);
784 int i;
785
786 /* Free all the skbuffs in the Rx queue. */
787 for (i = 0; i < RX_RING_SIZE; i++) {
788 struct sk_buff *skb = tp->rx_buffers[i].skb;
789 dma_addr_t mapping = tp->rx_buffers[i].mapping;
790
791 tp->rx_buffers[i].skb = NULL;
792 tp->rx_buffers[i].mapping = 0;
793
794 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
795 tp->rx_ring[i].length = 0;
796 /* An invalid address. */
797 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
798 if (skb) {
799 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
800 PCI_DMA_FROMDEVICE);
801 dev_kfree_skb (skb);
802 }
803 }
804
805 for (i = 0; i < TX_RING_SIZE; i++) {
806 struct sk_buff *skb = tp->tx_buffers[i].skb;
807
808 if (skb != NULL) {
809 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
810 skb->len, PCI_DMA_TODEVICE);
811 dev_kfree_skb (skb);
812 }
813 tp->tx_buffers[i].skb = NULL;
814 tp->tx_buffers[i].mapping = 0;
815 }
816 }
817
818 static int tulip_close (struct net_device *dev)
819 {
820 struct tulip_private *tp = netdev_priv(dev);
821 void __iomem *ioaddr = tp->base_addr;
822
823 netif_stop_queue (dev);
824
825 tulip_down (dev);
826
827 if (tulip_debug > 1)
828 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
829 dev->name, ioread32 (ioaddr + CSR5));
830
831 free_irq (dev->irq, dev);
832
833 tulip_free_ring (dev);
834
835 return 0;
836 }
837
838 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
839 {
840 struct tulip_private *tp = netdev_priv(dev);
841 void __iomem *ioaddr = tp->base_addr;
842
843 if (netif_running(dev)) {
844 unsigned long flags;
845
846 spin_lock_irqsave (&tp->lock, flags);
847
848 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
849
850 spin_unlock_irqrestore(&tp->lock, flags);
851 }
852
853 return &tp->stats;
854 }
855
856
857 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
858 {
859 struct tulip_private *np = netdev_priv(dev);
860 strcpy(info->driver, DRV_NAME);
861 strcpy(info->version, DRV_VERSION);
862 strcpy(info->bus_info, pci_name(np->pdev));
863 }
864
865 static const struct ethtool_ops ops = {
866 .get_drvinfo = tulip_get_drvinfo
867 };
868
869 /* Provide ioctl() calls to examine the MII xcvr state. */
870 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
871 {
872 struct tulip_private *tp = netdev_priv(dev);
873 void __iomem *ioaddr = tp->base_addr;
874 struct mii_ioctl_data *data = if_mii(rq);
875 const unsigned int phy_idx = 0;
876 int phy = tp->phys[phy_idx] & 0x1f;
877 unsigned int regnum = data->reg_num;
878
879 switch (cmd) {
880 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
881 if (tp->mii_cnt)
882 data->phy_id = phy;
883 else if (tp->flags & HAS_NWAY)
884 data->phy_id = 32;
885 else if (tp->chip_id == COMET)
886 data->phy_id = 1;
887 else
888 return -ENODEV;
889
890 case SIOCGMIIREG: /* Read MII PHY register. */
891 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
892 int csr12 = ioread32 (ioaddr + CSR12);
893 int csr14 = ioread32 (ioaddr + CSR14);
894 switch (regnum) {
895 case 0:
896 if (((csr14<<5) & 0x1000) ||
897 (dev->if_port == 5 && tp->nwayset))
898 data->val_out = 0x1000;
899 else
900 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
901 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
902 break;
903 case 1:
904 data->val_out =
905 0x1848 +
906 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
907 ((csr12&0x06) == 6 ? 0 : 4);
908 data->val_out |= 0x6048;
909 break;
910 case 4:
911 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
912 data->val_out =
913 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
914 ((csr14 >> 1) & 0x20) + 1;
915 data->val_out |= ((csr14 >> 9) & 0x03C0);
916 break;
917 case 5: data->val_out = tp->lpar; break;
918 default: data->val_out = 0; break;
919 }
920 } else {
921 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
922 }
923 return 0;
924
925 case SIOCSMIIREG: /* Write MII PHY register. */
926 if (regnum & ~0x1f)
927 return -EINVAL;
928 if (data->phy_id == phy) {
929 u16 value = data->val_in;
930 switch (regnum) {
931 case 0: /* Check for autonegotiation on or reset. */
932 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
933 if (tp->full_duplex_lock)
934 tp->full_duplex = (value & 0x0100) ? 1 : 0;
935 break;
936 case 4:
937 tp->advertising[phy_idx] =
938 tp->mii_advertise = data->val_in;
939 break;
940 }
941 }
942 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
943 u16 value = data->val_in;
944 if (regnum == 0) {
945 if ((value & 0x1200) == 0x1200) {
946 if (tp->chip_id == PNIC2) {
947 pnic2_start_nway (dev);
948 } else {
949 t21142_start_nway (dev);
950 }
951 }
952 } else if (regnum == 4)
953 tp->sym_advertise = value;
954 } else {
955 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
956 }
957 return 0;
958 default:
959 return -EOPNOTSUPP;
960 }
961
962 return -EOPNOTSUPP;
963 }
964
965
966 /* Set or clear the multicast filter for this adaptor.
967 Note that we only use exclusion around actually queueing the
968 new frame, not around filling tp->setup_frame. This is non-deterministic
969 when re-entered but still correct. */
970
971 #undef set_bit_le
972 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
973
974 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
975 {
976 struct tulip_private *tp = netdev_priv(dev);
977 u16 hash_table[32];
978 struct dev_mc_list *mclist;
979 int i;
980 u16 *eaddrs;
981
982 memset(hash_table, 0, sizeof(hash_table));
983 set_bit_le(255, hash_table); /* Broadcast entry */
984 /* This should work on big-endian machines as well. */
985 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
986 i++, mclist = mclist->next) {
987 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
988
989 set_bit_le(index, hash_table);
990
991 }
992 for (i = 0; i < 32; i++) {
993 *setup_frm++ = hash_table[i];
994 *setup_frm++ = hash_table[i];
995 }
996 setup_frm = &tp->setup_frame[13*6];
997
998 /* Fill the final entry with our physical address. */
999 eaddrs = (u16 *)dev->dev_addr;
1000 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1001 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1002 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1003 }
1004
1005 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1006 {
1007 struct tulip_private *tp = netdev_priv(dev);
1008 struct dev_mc_list *mclist;
1009 int i;
1010 u16 *eaddrs;
1011
1012 /* We have <= 14 addresses so we can use the wonderful
1013 16 address perfect filtering of the Tulip. */
1014 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1015 i++, mclist = mclist->next) {
1016 eaddrs = (u16 *)mclist->dmi_addr;
1017 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1018 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1019 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1020 }
1021 /* Fill the unused entries with the broadcast address. */
1022 memset(setup_frm, 0xff, (15-i)*12);
1023 setup_frm = &tp->setup_frame[15*6];
1024
1025 /* Fill the final entry with our physical address. */
1026 eaddrs = (u16 *)dev->dev_addr;
1027 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1028 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1029 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1030 }
1031
1032
1033 static void set_rx_mode(struct net_device *dev)
1034 {
1035 struct tulip_private *tp = netdev_priv(dev);
1036 void __iomem *ioaddr = tp->base_addr;
1037 int csr6;
1038
1039 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1040
1041 tp->csr6 &= ~0x00D5;
1042 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1043 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1044 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1045 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1046 /* Too many to filter well -- accept all multicasts. */
1047 tp->csr6 |= AcceptAllMulticast;
1048 csr6 |= AcceptAllMulticast;
1049 } else if (tp->flags & MC_HASH_ONLY) {
1050 /* Some work-alikes have only a 64-entry hash filter table. */
1051 /* Should verify correctness on big-endian/__powerpc__ */
1052 struct dev_mc_list *mclist;
1053 int i;
1054 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1055 tp->csr6 |= AcceptAllMulticast;
1056 csr6 |= AcceptAllMulticast;
1057 } else {
1058 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1059 int filterbit;
1060 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1061 i++, mclist = mclist->next) {
1062 if (tp->flags & COMET_MAC_ADDR)
1063 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1064 else
1065 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1066 filterbit &= 0x3f;
1067 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1068 if (tulip_debug > 2)
1069 printk(KERN_INFO "%s: Added filter for %pM"
1070 " %8.8x bit %d.\n",
1071 dev->name, mclist->dmi_addr,
1072 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1073 }
1074 if (mc_filter[0] == tp->mc_filter[0] &&
1075 mc_filter[1] == tp->mc_filter[1])
1076 ; /* No change. */
1077 else if (tp->flags & IS_ASIX) {
1078 iowrite32(2, ioaddr + CSR13);
1079 iowrite32(mc_filter[0], ioaddr + CSR14);
1080 iowrite32(3, ioaddr + CSR13);
1081 iowrite32(mc_filter[1], ioaddr + CSR14);
1082 } else if (tp->flags & COMET_MAC_ADDR) {
1083 iowrite32(mc_filter[0], ioaddr + 0xAC);
1084 iowrite32(mc_filter[1], ioaddr + 0xB0);
1085 }
1086 tp->mc_filter[0] = mc_filter[0];
1087 tp->mc_filter[1] = mc_filter[1];
1088 }
1089 } else {
1090 unsigned long flags;
1091 u32 tx_flags = 0x08000000 | 192;
1092
1093 /* Note that only the low-address shortword of setup_frame is valid!
1094 The values are doubled for big-endian architectures. */
1095 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1096 build_setup_frame_hash(tp->setup_frame, dev);
1097 tx_flags = 0x08400000 | 192;
1098 } else {
1099 build_setup_frame_perfect(tp->setup_frame, dev);
1100 }
1101
1102 spin_lock_irqsave(&tp->lock, flags);
1103
1104 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1105 /* Same setup recently queued, we need not add it. */
1106 } else {
1107 unsigned int entry;
1108 int dummy = -1;
1109
1110 /* Now add this frame to the Tx list. */
1111
1112 entry = tp->cur_tx++ % TX_RING_SIZE;
1113
1114 if (entry != 0) {
1115 /* Avoid a chip errata by prefixing a dummy entry. */
1116 tp->tx_buffers[entry].skb = NULL;
1117 tp->tx_buffers[entry].mapping = 0;
1118 tp->tx_ring[entry].length =
1119 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1120 tp->tx_ring[entry].buffer1 = 0;
1121 /* Must set DescOwned later to avoid race with chip */
1122 dummy = entry;
1123 entry = tp->cur_tx++ % TX_RING_SIZE;
1124
1125 }
1126
1127 tp->tx_buffers[entry].skb = NULL;
1128 tp->tx_buffers[entry].mapping =
1129 pci_map_single(tp->pdev, tp->setup_frame,
1130 sizeof(tp->setup_frame),
1131 PCI_DMA_TODEVICE);
1132 /* Put the setup frame on the Tx list. */
1133 if (entry == TX_RING_SIZE-1)
1134 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1135 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1136 tp->tx_ring[entry].buffer1 =
1137 cpu_to_le32(tp->tx_buffers[entry].mapping);
1138 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1139 if (dummy >= 0)
1140 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1141 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1142 netif_stop_queue(dev);
1143
1144 /* Trigger an immediate transmit demand. */
1145 iowrite32(0, ioaddr + CSR1);
1146 }
1147
1148 spin_unlock_irqrestore(&tp->lock, flags);
1149 }
1150
1151 iowrite32(csr6, ioaddr + CSR6);
1152 }
1153
1154 #ifdef CONFIG_TULIP_MWI
1155 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1156 struct net_device *dev)
1157 {
1158 struct tulip_private *tp = netdev_priv(dev);
1159 u8 cache;
1160 u16 pci_command;
1161 u32 csr0;
1162
1163 if (tulip_debug > 3)
1164 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1165
1166 tp->csr0 = csr0 = 0;
1167
1168 /* if we have any cache line size at all, we can do MRM and MWI */
1169 csr0 |= MRM | MWI;
1170
1171 /* Enable MWI in the standard PCI command bit.
1172 * Check for the case where MWI is desired but not available
1173 */
1174 pci_try_set_mwi(pdev);
1175
1176 /* read result from hardware (in case bit refused to enable) */
1177 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1178 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1179 csr0 &= ~MWI;
1180
1181 /* if cache line size hardwired to zero, no MWI */
1182 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1183 if ((csr0 & MWI) && (cache == 0)) {
1184 csr0 &= ~MWI;
1185 pci_clear_mwi(pdev);
1186 }
1187
1188 /* assign per-cacheline-size cache alignment and
1189 * burst length values
1190 */
1191 switch (cache) {
1192 case 8:
1193 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1194 break;
1195 case 16:
1196 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1197 break;
1198 case 32:
1199 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1200 break;
1201 default:
1202 cache = 0;
1203 break;
1204 }
1205
1206 /* if we have a good cache line size, we by now have a good
1207 * csr0, so save it and exit
1208 */
1209 if (cache)
1210 goto out;
1211
1212 /* we don't have a good csr0 or cache line size, disable MWI */
1213 if (csr0 & MWI) {
1214 pci_clear_mwi(pdev);
1215 csr0 &= ~MWI;
1216 }
1217
1218 /* sane defaults for burst length and cache alignment
1219 * originally from de4x5 driver
1220 */
1221 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1222
1223 out:
1224 tp->csr0 = csr0;
1225 if (tulip_debug > 2)
1226 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1227 pci_name(pdev), cache, csr0);
1228 }
1229 #endif
1230
1231 /*
1232 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1233 * is the DM910X and the on chip ULi devices
1234 */
1235
1236 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1237 {
1238 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1239 return 1;
1240 return 0;
1241 }
1242
1243 static const struct net_device_ops tulip_netdev_ops = {
1244 .ndo_open = tulip_open,
1245 .ndo_start_xmit = tulip_start_xmit,
1246 .ndo_tx_timeout = tulip_tx_timeout,
1247 .ndo_stop = tulip_close,
1248 .ndo_get_stats = tulip_get_stats,
1249 .ndo_do_ioctl = private_ioctl,
1250 .ndo_set_multicast_list = set_rx_mode,
1251 .ndo_change_mtu = eth_change_mtu,
1252 .ndo_set_mac_address = eth_mac_addr,
1253 .ndo_validate_addr = eth_validate_addr,
1254 #ifdef CONFIG_NET_POLL_CONTROLLER
1255 .ndo_poll_controller = poll_tulip,
1256 #endif
1257 };
1258
1259 static int __devinit tulip_init_one (struct pci_dev *pdev,
1260 const struct pci_device_id *ent)
1261 {
1262 struct tulip_private *tp;
1263 /* See note below on the multiport cards. */
1264 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1265 static struct pci_device_id early_486_chipsets[] = {
1266 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1267 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1268 { },
1269 };
1270 static int last_irq;
1271 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1272 int i, irq;
1273 unsigned short sum;
1274 unsigned char *ee_data;
1275 struct net_device *dev;
1276 void __iomem *ioaddr;
1277 static int board_idx = -1;
1278 int chip_idx = ent->driver_data;
1279 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1280 unsigned int eeprom_missing = 0;
1281 unsigned int force_csr0 = 0;
1282
1283 #ifndef MODULE
1284 static int did_version; /* Already printed version info. */
1285 if (tulip_debug > 0 && did_version++ == 0)
1286 printk (KERN_INFO "%s", version);
1287 #endif
1288
1289 board_idx++;
1290
1291 /*
1292 * Lan media wire a tulip chip to a wan interface. Needs a very
1293 * different driver (lmc driver)
1294 */
1295
1296 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1297 printk (KERN_ERR PFX "skipping LMC card.\n");
1298 return -ENODEV;
1299 }
1300
1301 /*
1302 * Early DM9100's need software CRC and the DMFE driver
1303 */
1304
1305 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1306 {
1307 /* Read Chip revision */
1308 if (pdev->revision < 0x30)
1309 {
1310 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1311 return -ENODEV;
1312 }
1313 }
1314
1315 /*
1316 * Looks for early PCI chipsets where people report hangs
1317 * without the workarounds being on.
1318 */
1319
1320 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1321 aligned. Aries might need this too. The Saturn errata are not
1322 pretty reading but thankfully it's an old 486 chipset.
1323
1324 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1325 Saturn.
1326 */
1327
1328 if (pci_dev_present(early_486_chipsets)) {
1329 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1330 force_csr0 = 1;
1331 }
1332
1333 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1334 if (chip_idx == AX88140) {
1335 if ((csr0 & 0x3f00) == 0)
1336 csr0 |= 0x2000;
1337 }
1338
1339 /* PNIC doesn't have MWI/MRL/MRM... */
1340 if (chip_idx == LC82C168)
1341 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1342
1343 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1344 if (tulip_uli_dm_quirk(pdev)) {
1345 csr0 &= ~0x01f100ff;
1346 #if defined(CONFIG_SPARC)
1347 csr0 = (csr0 & ~0xff00) | 0xe000;
1348 #endif
1349 }
1350 /*
1351 * And back to business
1352 */
1353
1354 i = pci_enable_device(pdev);
1355 if (i) {
1356 printk (KERN_ERR PFX
1357 "Cannot enable tulip board #%d, aborting\n",
1358 board_idx);
1359 return i;
1360 }
1361
1362 irq = pdev->irq;
1363
1364 /* alloc_etherdev ensures aligned and zeroed private structures */
1365 dev = alloc_etherdev (sizeof (*tp));
1366 if (!dev) {
1367 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1368 return -ENOMEM;
1369 }
1370
1371 SET_NETDEV_DEV(dev, &pdev->dev);
1372 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1373 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1374 "aborting\n", pci_name(pdev),
1375 (unsigned long long)pci_resource_len (pdev, 0),
1376 (unsigned long long)pci_resource_start (pdev, 0));
1377 goto err_out_free_netdev;
1378 }
1379
1380 /* grab all resources from both PIO and MMIO regions, as we
1381 * don't want anyone else messing around with our hardware */
1382 if (pci_request_regions (pdev, "tulip"))
1383 goto err_out_free_netdev;
1384
1385 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1386
1387 if (!ioaddr)
1388 goto err_out_free_res;
1389
1390 /*
1391 * initialize private data structure 'tp'
1392 * it is zeroed and aligned in alloc_etherdev
1393 */
1394 tp = netdev_priv(dev);
1395 tp->dev = dev;
1396
1397 tp->rx_ring = pci_alloc_consistent(pdev,
1398 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1399 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1400 &tp->rx_ring_dma);
1401 if (!tp->rx_ring)
1402 goto err_out_mtable;
1403 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1404 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1405
1406 tp->chip_id = chip_idx;
1407 tp->flags = tulip_tbl[chip_idx].flags;
1408 tp->pdev = pdev;
1409 tp->base_addr = ioaddr;
1410 tp->revision = pdev->revision;
1411 tp->csr0 = csr0;
1412 spin_lock_init(&tp->lock);
1413 spin_lock_init(&tp->mii_lock);
1414 init_timer(&tp->timer);
1415 tp->timer.data = (unsigned long)dev;
1416 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1417
1418 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1419
1420 dev->base_addr = (unsigned long)ioaddr;
1421
1422 #ifdef CONFIG_TULIP_MWI
1423 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1424 tulip_mwi_config (pdev, dev);
1425 #endif
1426
1427 /* Stop the chip's Tx and Rx processes. */
1428 tulip_stop_rxtx(tp);
1429
1430 pci_set_master(pdev);
1431
1432 #ifdef CONFIG_GSC
1433 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1434 switch (pdev->subsystem_device) {
1435 default:
1436 break;
1437 case 0x1061:
1438 case 0x1062:
1439 case 0x1063:
1440 case 0x1098:
1441 case 0x1099:
1442 case 0x10EE:
1443 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1444 chip_name = "GSC DS21140 Tulip";
1445 }
1446 }
1447 #endif
1448
1449 /* Clear the missed-packet counter. */
1450 ioread32(ioaddr + CSR8);
1451
1452 /* The station address ROM is read byte serially. The register must
1453 be polled, waiting for the value to be read bit serially from the
1454 EEPROM.
1455 */
1456 ee_data = tp->eeprom;
1457 memset(ee_data, 0, sizeof(tp->eeprom));
1458 sum = 0;
1459 if (chip_idx == LC82C168) {
1460 for (i = 0; i < 3; i++) {
1461 int value, boguscnt = 100000;
1462 iowrite32(0x600 | i, ioaddr + 0x98);
1463 do {
1464 value = ioread32(ioaddr + CSR9);
1465 } while (value < 0 && --boguscnt > 0);
1466 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1467 sum += value & 0xffff;
1468 }
1469 } else if (chip_idx == COMET) {
1470 /* No need to read the EEPROM. */
1471 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1472 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1473 for (i = 0; i < 6; i ++)
1474 sum += dev->dev_addr[i];
1475 } else {
1476 /* A serial EEPROM interface, we read now and sort it out later. */
1477 int sa_offset = 0;
1478 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1479 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1480
1481 if (ee_max_addr > sizeof(tp->eeprom))
1482 ee_max_addr = sizeof(tp->eeprom);
1483
1484 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1485 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1486 ee_data[i] = data & 0xff;
1487 ee_data[i + 1] = data >> 8;
1488 }
1489
1490 /* DEC now has a specification (see Notes) but early board makers
1491 just put the address in the first EEPROM locations. */
1492 /* This does memcmp(ee_data, ee_data+16, 8) */
1493 for (i = 0; i < 8; i ++)
1494 if (ee_data[i] != ee_data[16+i])
1495 sa_offset = 20;
1496 if (chip_idx == CONEXANT) {
1497 /* Check that the tuple type and length is correct. */
1498 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1499 sa_offset = 0x19A;
1500 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1501 ee_data[2] == 0) {
1502 sa_offset = 2; /* Grrr, damn Matrox boards. */
1503 multiport_cnt = 4;
1504 }
1505 #ifdef CONFIG_MIPS_COBALT
1506 if ((pdev->bus->number == 0) &&
1507 ((PCI_SLOT(pdev->devfn) == 7) ||
1508 (PCI_SLOT(pdev->devfn) == 12))) {
1509 /* Cobalt MAC address in first EEPROM locations. */
1510 sa_offset = 0;
1511 /* Ensure our media table fixup get's applied */
1512 memcpy(ee_data + 16, ee_data, 8);
1513 }
1514 #endif
1515 #ifdef CONFIG_GSC
1516 /* Check to see if we have a broken srom */
1517 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1518 /* pci_vendor_id and subsystem_id are swapped */
1519 ee_data[0] = ee_data[2];
1520 ee_data[1] = ee_data[3];
1521 ee_data[2] = 0x61;
1522 ee_data[3] = 0x10;
1523
1524 /* HSC-PCI boards need to be byte-swaped and shifted
1525 * up 1 word. This shift needs to happen at the end
1526 * of the MAC first because of the 2 byte overlap.
1527 */
1528 for (i = 4; i >= 0; i -= 2) {
1529 ee_data[17 + i + 3] = ee_data[17 + i];
1530 ee_data[16 + i + 5] = ee_data[16 + i];
1531 }
1532 }
1533 #endif
1534
1535 for (i = 0; i < 6; i ++) {
1536 dev->dev_addr[i] = ee_data[i + sa_offset];
1537 sum += ee_data[i + sa_offset];
1538 }
1539 }
1540 /* Lite-On boards have the address byte-swapped. */
1541 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1542 && dev->dev_addr[1] == 0x00)
1543 for (i = 0; i < 6; i+=2) {
1544 char tmp = dev->dev_addr[i];
1545 dev->dev_addr[i] = dev->dev_addr[i+1];
1546 dev->dev_addr[i+1] = tmp;
1547 }
1548 /* On the Zynx 315 Etherarray and other multiport boards only the
1549 first Tulip has an EEPROM.
1550 On Sparc systems the mac address is held in the OBP property
1551 "local-mac-address".
1552 The addresses of the subsequent ports are derived from the first.
1553 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1554 that here as well. */
1555 if (sum == 0 || sum == 6*0xff) {
1556 #if defined(CONFIG_SPARC)
1557 struct device_node *dp = pci_device_to_OF_node(pdev);
1558 const unsigned char *addr;
1559 int len;
1560 #endif
1561 eeprom_missing = 1;
1562 for (i = 0; i < 5; i++)
1563 dev->dev_addr[i] = last_phys_addr[i];
1564 dev->dev_addr[i] = last_phys_addr[i] + 1;
1565 #if defined(CONFIG_SPARC)
1566 addr = of_get_property(dp, "local-mac-address", &len);
1567 if (addr && len == 6)
1568 memcpy(dev->dev_addr, addr, 6);
1569 #endif
1570 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1571 if (last_irq)
1572 irq = last_irq;
1573 #endif
1574 }
1575
1576 for (i = 0; i < 6; i++)
1577 last_phys_addr[i] = dev->dev_addr[i];
1578 last_irq = irq;
1579 dev->irq = irq;
1580
1581 /* The lower four bits are the media type. */
1582 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1583 if (options[board_idx] & MEDIA_MASK)
1584 tp->default_port = options[board_idx] & MEDIA_MASK;
1585 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1586 tp->full_duplex = 1;
1587 if (mtu[board_idx] > 0)
1588 dev->mtu = mtu[board_idx];
1589 }
1590 if (dev->mem_start & MEDIA_MASK)
1591 tp->default_port = dev->mem_start & MEDIA_MASK;
1592 if (tp->default_port) {
1593 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1594 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1595 tp->medialock = 1;
1596 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1597 tp->full_duplex = 1;
1598 }
1599 if (tp->full_duplex)
1600 tp->full_duplex_lock = 1;
1601
1602 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1603 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1604 tp->mii_advertise = media2advert[tp->default_port - 9];
1605 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1606 }
1607
1608 if (tp->flags & HAS_MEDIA_TABLE) {
1609 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1610 tulip_parse_eeprom(dev);
1611 strcpy(dev->name, "eth%d"); /* un-hack */
1612 }
1613
1614 if ((tp->flags & ALWAYS_CHECK_MII) ||
1615 (tp->mtable && tp->mtable->has_mii) ||
1616 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1617 if (tp->mtable && tp->mtable->has_mii) {
1618 for (i = 0; i < tp->mtable->leafcount; i++)
1619 if (tp->mtable->mleaf[i].media == 11) {
1620 tp->cur_index = i;
1621 tp->saved_if_port = dev->if_port;
1622 tulip_select_media(dev, 2);
1623 dev->if_port = tp->saved_if_port;
1624 break;
1625 }
1626 }
1627
1628 /* Find the connected MII xcvrs.
1629 Doing this in open() would allow detecting external xcvrs
1630 later, but takes much time. */
1631 tulip_find_mii (dev, board_idx);
1632 }
1633
1634 /* The Tulip-specific entries in the device structure. */
1635 dev->netdev_ops = &tulip_netdev_ops;
1636 dev->watchdog_timeo = TX_TIMEOUT;
1637 #ifdef CONFIG_TULIP_NAPI
1638 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1639 #endif
1640 SET_ETHTOOL_OPS(dev, &ops);
1641
1642 if (register_netdev(dev))
1643 goto err_out_free_ring;
1644
1645 printk(KERN_INFO "%s: %s rev %d at "
1646 #ifdef CONFIG_TULIP_MMIO
1647 "MMIO"
1648 #else
1649 "Port"
1650 #endif
1651 " %#llx,", dev->name, chip_name, pdev->revision,
1652 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1653 pci_set_drvdata(pdev, dev);
1654
1655 if (eeprom_missing)
1656 printk(" EEPROM not present,");
1657 printk(" %pM", dev->dev_addr);
1658 printk(", IRQ %d.\n", irq);
1659
1660 if (tp->chip_id == PNIC2)
1661 tp->link_change = pnic2_lnk_change;
1662 else if (tp->flags & HAS_NWAY)
1663 tp->link_change = t21142_lnk_change;
1664 else if (tp->flags & HAS_PNICNWAY)
1665 tp->link_change = pnic_lnk_change;
1666
1667 /* Reset the xcvr interface and turn on heartbeat. */
1668 switch (chip_idx) {
1669 case DC21140:
1670 case DM910X:
1671 default:
1672 if (tp->mtable)
1673 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1674 break;
1675 case DC21142:
1676 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1677 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1678 iowrite32(0x0000, ioaddr + CSR13);
1679 iowrite32(0x0000, ioaddr + CSR14);
1680 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1681 } else
1682 t21142_start_nway(dev);
1683 break;
1684 case PNIC2:
1685 /* just do a reset for sanity sake */
1686 iowrite32(0x0000, ioaddr + CSR13);
1687 iowrite32(0x0000, ioaddr + CSR14);
1688 break;
1689 case LC82C168:
1690 if ( ! tp->mii_cnt) {
1691 tp->nway = 1;
1692 tp->nwayset = 0;
1693 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1694 iowrite32(0x30, ioaddr + CSR12);
1695 iowrite32(0x0001F078, ioaddr + CSR6);
1696 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1697 }
1698 break;
1699 case MX98713:
1700 case COMPEX9881:
1701 iowrite32(0x00000000, ioaddr + CSR6);
1702 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1703 iowrite32(0x00000001, ioaddr + CSR13);
1704 break;
1705 case MX98715:
1706 case MX98725:
1707 iowrite32(0x01a80000, ioaddr + CSR6);
1708 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1709 iowrite32(0x00001000, ioaddr + CSR12);
1710 break;
1711 case COMET:
1712 /* No initialization necessary. */
1713 break;
1714 }
1715
1716 /* put the chip in snooze mode until opened */
1717 tulip_set_power_state (tp, 0, 1);
1718
1719 return 0;
1720
1721 err_out_free_ring:
1722 pci_free_consistent (pdev,
1723 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1724 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1725 tp->rx_ring, tp->rx_ring_dma);
1726
1727 err_out_mtable:
1728 kfree (tp->mtable);
1729 pci_iounmap(pdev, ioaddr);
1730
1731 err_out_free_res:
1732 pci_release_regions (pdev);
1733
1734 err_out_free_netdev:
1735 free_netdev (dev);
1736 return -ENODEV;
1737 }
1738
1739
1740 #ifdef CONFIG_PM
1741
1742 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1743 {
1744 struct net_device *dev = pci_get_drvdata(pdev);
1745
1746 if (!dev)
1747 return -EINVAL;
1748
1749 if (!netif_running(dev))
1750 goto save_state;
1751
1752 tulip_down(dev);
1753
1754 netif_device_detach(dev);
1755 free_irq(dev->irq, dev);
1756
1757 save_state:
1758 pci_save_state(pdev);
1759 pci_disable_device(pdev);
1760 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1761
1762 return 0;
1763 }
1764
1765
1766 static int tulip_resume(struct pci_dev *pdev)
1767 {
1768 struct net_device *dev = pci_get_drvdata(pdev);
1769 int retval;
1770
1771 if (!dev)
1772 return -EINVAL;
1773
1774 pci_set_power_state(pdev, PCI_D0);
1775 pci_restore_state(pdev);
1776
1777 if (!netif_running(dev))
1778 return 0;
1779
1780 if ((retval = pci_enable_device(pdev))) {
1781 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1782 return retval;
1783 }
1784
1785 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1786 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1787 return retval;
1788 }
1789
1790 netif_device_attach(dev);
1791
1792 if (netif_running(dev))
1793 tulip_up(dev);
1794
1795 return 0;
1796 }
1797
1798 #endif /* CONFIG_PM */
1799
1800
1801 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1802 {
1803 struct net_device *dev = pci_get_drvdata (pdev);
1804 struct tulip_private *tp;
1805
1806 if (!dev)
1807 return;
1808
1809 tp = netdev_priv(dev);
1810 unregister_netdev(dev);
1811 pci_free_consistent (pdev,
1812 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1813 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1814 tp->rx_ring, tp->rx_ring_dma);
1815 kfree (tp->mtable);
1816 pci_iounmap(pdev, tp->base_addr);
1817 free_netdev (dev);
1818 pci_release_regions (pdev);
1819 pci_set_drvdata (pdev, NULL);
1820
1821 /* pci_power_off (pdev, -1); */
1822 }
1823
1824 #ifdef CONFIG_NET_POLL_CONTROLLER
1825 /*
1826 * Polling 'interrupt' - used by things like netconsole to send skbs
1827 * without having to re-enable interrupts. It's not called while
1828 * the interrupt routine is executing.
1829 */
1830
1831 static void poll_tulip (struct net_device *dev)
1832 {
1833 /* disable_irq here is not very nice, but with the lockless
1834 interrupt handler we have no other choice. */
1835 disable_irq(dev->irq);
1836 tulip_interrupt (dev->irq, dev);
1837 enable_irq(dev->irq);
1838 }
1839 #endif
1840
1841 static struct pci_driver tulip_driver = {
1842 .name = DRV_NAME,
1843 .id_table = tulip_pci_tbl,
1844 .probe = tulip_init_one,
1845 .remove = __devexit_p(tulip_remove_one),
1846 #ifdef CONFIG_PM
1847 .suspend = tulip_suspend,
1848 .resume = tulip_resume,
1849 #endif /* CONFIG_PM */
1850 };
1851
1852
1853 static int __init tulip_init (void)
1854 {
1855 #ifdef MODULE
1856 printk (KERN_INFO "%s", version);
1857 #endif
1858
1859 /* copy module parms into globals */
1860 tulip_rx_copybreak = rx_copybreak;
1861 tulip_max_interrupt_work = max_interrupt_work;
1862
1863 /* probe for and init boards */
1864 return pci_register_driver(&tulip_driver);
1865 }
1866
1867
1868 static void __exit tulip_cleanup (void)
1869 {
1870 pci_unregister_driver (&tulip_driver);
1871 }
1872
1873
1874 module_init(tulip_init);
1875 module_exit(tulip_cleanup);
Linux with added FPC-III support