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f81232: switch to ->get_serial()
[linux/fpc-iii.git] / drivers / media / platform / rcar_fdp1.c
blob2a15b7cca338fe6445ae11a8ec275c9e40ac1245
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Renesas R-Car Fine Display Processor
4 *
5 * Video format converter and frame deinterlacer device.
6 *
7 * Author: Kieran Bingham, <kieran@bingham.xyz>
8 * Copyright (c) 2016 Renesas Electronics Corporation.
9 *
10 * This code is developed and inspired from the vim2m, rcar_jpu,
11 * m2m-deinterlace, and vsp1 drivers.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/fs.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/sched.h>
25 #include <linux/slab.h>
26 #include <linux/timer.h>
27 #include <media/rcar-fcp.h>
28 #include <media/v4l2-ctrls.h>
29 #include <media/v4l2-device.h>
30 #include <media/v4l2-event.h>
31 #include <media/v4l2-ioctl.h>
32 #include <media/v4l2-mem2mem.h>
33 #include <media/videobuf2-dma-contig.h>
34
35 static unsigned int debug;
36 module_param(debug, uint, 0644);
37 MODULE_PARM_DESC(debug, "activate debug info");
38
39 /* Minimum and maximum frame width/height */
40 #define FDP1_MIN_W 80U
41 #define FDP1_MIN_H 80U
42
43 #define FDP1_MAX_W 3840U
44 #define FDP1_MAX_H 2160U
45
46 #define FDP1_MAX_PLANES 3U
47 #define FDP1_MAX_STRIDE 8190U
48
49 /* Flags that indicate a format can be used for capture/output */
50 #define FDP1_CAPTURE BIT(0)
51 #define FDP1_OUTPUT BIT(1)
52
53 #define DRIVER_NAME "rcar_fdp1"
54
55 /* Number of Job's to have available on the processing queue */
56 #define FDP1_NUMBER_JOBS 8
57
58 #define dprintk(fdp1, fmt, arg...) \
59 v4l2_dbg(1, debug, &fdp1->v4l2_dev, "%s: " fmt, __func__, ## arg)
60
61 /*
62 * FDP1 registers and bits
63 */
64
65 /* FDP1 start register - Imm */
66 #define FD1_CTL_CMD 0x0000
67 #define FD1_CTL_CMD_STRCMD BIT(0)
68
69 /* Sync generator register - Imm */
70 #define FD1_CTL_SGCMD 0x0004
71 #define FD1_CTL_SGCMD_SGEN BIT(0)
72
73 /* Register set end register - Imm */
74 #define FD1_CTL_REGEND 0x0008
75 #define FD1_CTL_REGEND_REGEND BIT(0)
76
77 /* Channel activation register - Vupdt */
78 #define FD1_CTL_CHACT 0x000c
79 #define FD1_CTL_CHACT_SMW BIT(9)
80 #define FD1_CTL_CHACT_WR BIT(8)
81 #define FD1_CTL_CHACT_SMR BIT(3)
82 #define FD1_CTL_CHACT_RD2 BIT(2)
83 #define FD1_CTL_CHACT_RD1 BIT(1)
84 #define FD1_CTL_CHACT_RD0 BIT(0)
85
86 /* Operation Mode Register - Vupdt */
87 #define FD1_CTL_OPMODE 0x0010
88 #define FD1_CTL_OPMODE_PRG BIT(4)
89 #define FD1_CTL_OPMODE_VIMD_INTERRUPT (0 << 0)
90 #define FD1_CTL_OPMODE_VIMD_BESTEFFORT (1 << 0)
91 #define FD1_CTL_OPMODE_VIMD_NOINTERRUPT (2 << 0)
92
93 #define FD1_CTL_VPERIOD 0x0014
94 #define FD1_CTL_CLKCTRL 0x0018
95 #define FD1_CTL_CLKCTRL_CSTP_N BIT(0)
96
97 /* Software reset register */
98 #define FD1_CTL_SRESET 0x001c
99 #define FD1_CTL_SRESET_SRST BIT(0)
100
101 /* Control status register (V-update-status) */
102 #define FD1_CTL_STATUS 0x0024
103 #define FD1_CTL_STATUS_VINT_CNT_MASK GENMASK(31, 16)
104 #define FD1_CTL_STATUS_VINT_CNT_SHIFT 16
105 #define FD1_CTL_STATUS_SGREGSET BIT(10)
106 #define FD1_CTL_STATUS_SGVERR BIT(9)
107 #define FD1_CTL_STATUS_SGFREND BIT(8)
108 #define FD1_CTL_STATUS_BSY BIT(0)
109
110 #define FD1_CTL_VCYCLE_STAT 0x0028
111
112 /* Interrupt enable register */
113 #define FD1_CTL_IRQENB 0x0038
114 /* Interrupt status register */
115 #define FD1_CTL_IRQSTA 0x003c
116 /* Interrupt control register */
117 #define FD1_CTL_IRQFSET 0x0040
118
119 /* Common IRQ Bit settings */
120 #define FD1_CTL_IRQ_VERE BIT(16)
121 #define FD1_CTL_IRQ_VINTE BIT(4)
122 #define FD1_CTL_IRQ_FREE BIT(0)
123 #define FD1_CTL_IRQ_MASK (FD1_CTL_IRQ_VERE | \
124 FD1_CTL_IRQ_VINTE | \
125 FD1_CTL_IRQ_FREE)
126
127 /* RPF */
128 #define FD1_RPF_SIZE 0x0060
129 #define FD1_RPF_SIZE_MASK GENMASK(12, 0)
130 #define FD1_RPF_SIZE_H_SHIFT 16
131 #define FD1_RPF_SIZE_V_SHIFT 0
132
133 #define FD1_RPF_FORMAT 0x0064
134 #define FD1_RPF_FORMAT_CIPM BIT(16)
135 #define FD1_RPF_FORMAT_RSPYCS BIT(13)
136 #define FD1_RPF_FORMAT_RSPUVS BIT(12)
137 #define FD1_RPF_FORMAT_CF BIT(8)
138
139 #define FD1_RPF_PSTRIDE 0x0068
140 #define FD1_RPF_PSTRIDE_Y_SHIFT 16
141 #define FD1_RPF_PSTRIDE_C_SHIFT 0
142
143 /* RPF0 Source Component Y Address register */
144 #define FD1_RPF0_ADDR_Y 0x006c
145
146 /* RPF1 Current Picture Registers */
147 #define FD1_RPF1_ADDR_Y 0x0078
148 #define FD1_RPF1_ADDR_C0 0x007c
149 #define FD1_RPF1_ADDR_C1 0x0080
150
151 /* RPF2 next picture register */
152 #define FD1_RPF2_ADDR_Y 0x0084
153
154 #define FD1_RPF_SMSK_ADDR 0x0090
155 #define FD1_RPF_SWAP 0x0094
156
157 /* WPF */
158 #define FD1_WPF_FORMAT 0x00c0
159 #define FD1_WPF_FORMAT_PDV_SHIFT 24
160 #define FD1_WPF_FORMAT_FCNL BIT(20)
161 #define FD1_WPF_FORMAT_WSPYCS BIT(15)
162 #define FD1_WPF_FORMAT_WSPUVS BIT(14)
163 #define FD1_WPF_FORMAT_WRTM_601_16 (0 << 9)
164 #define FD1_WPF_FORMAT_WRTM_601_0 (1 << 9)
165 #define FD1_WPF_FORMAT_WRTM_709_16 (2 << 9)
166 #define FD1_WPF_FORMAT_CSC BIT(8)
167
168 #define FD1_WPF_RNDCTL 0x00c4
169 #define FD1_WPF_RNDCTL_CBRM BIT(28)
170 #define FD1_WPF_RNDCTL_CLMD_NOCLIP (0 << 12)
171 #define FD1_WPF_RNDCTL_CLMD_CLIP_16_235 (1 << 12)
172 #define FD1_WPF_RNDCTL_CLMD_CLIP_1_254 (2 << 12)
173
174 #define FD1_WPF_PSTRIDE 0x00c8
175 #define FD1_WPF_PSTRIDE_Y_SHIFT 16
176 #define FD1_WPF_PSTRIDE_C_SHIFT 0
177
178 /* WPF Destination picture */
179 #define FD1_WPF_ADDR_Y 0x00cc
180 #define FD1_WPF_ADDR_C0 0x00d0
181 #define FD1_WPF_ADDR_C1 0x00d4
182 #define FD1_WPF_SWAP 0x00d8
183 #define FD1_WPF_SWAP_OSWAP_SHIFT 0
184 #define FD1_WPF_SWAP_SSWAP_SHIFT 4
185
186 /* WPF/RPF Common */
187 #define FD1_RWPF_SWAP_BYTE BIT(0)
188 #define FD1_RWPF_SWAP_WORD BIT(1)
189 #define FD1_RWPF_SWAP_LWRD BIT(2)
190 #define FD1_RWPF_SWAP_LLWD BIT(3)
191
192 /* IPC */
193 #define FD1_IPC_MODE 0x0100
194 #define FD1_IPC_MODE_DLI BIT(8)
195 #define FD1_IPC_MODE_DIM_ADAPT2D3D (0 << 0)
196 #define FD1_IPC_MODE_DIM_FIXED2D (1 << 0)
197 #define FD1_IPC_MODE_DIM_FIXED3D (2 << 0)
198 #define FD1_IPC_MODE_DIM_PREVFIELD (3 << 0)
199 #define FD1_IPC_MODE_DIM_NEXTFIELD (4 << 0)
200
201 #define FD1_IPC_SMSK_THRESH 0x0104
202 #define FD1_IPC_SMSK_THRESH_CONST 0x00010002
203
204 #define FD1_IPC_COMB_DET 0x0108
205 #define FD1_IPC_COMB_DET_CONST 0x00200040
206
207 #define FD1_IPC_MOTDEC 0x010c
208 #define FD1_IPC_MOTDEC_CONST 0x00008020
209
210 /* DLI registers */
211 #define FD1_IPC_DLI_BLEND 0x0120
212 #define FD1_IPC_DLI_BLEND_CONST 0x0080ff02
213
214 #define FD1_IPC_DLI_HGAIN 0x0124
215 #define FD1_IPC_DLI_HGAIN_CONST 0x001000ff
216
217 #define FD1_IPC_DLI_SPRS 0x0128
218 #define FD1_IPC_DLI_SPRS_CONST 0x009004ff
219
220 #define FD1_IPC_DLI_ANGLE 0x012c
221 #define FD1_IPC_DLI_ANGLE_CONST 0x0004080c
222
223 #define FD1_IPC_DLI_ISOPIX0 0x0130
224 #define FD1_IPC_DLI_ISOPIX0_CONST 0xff10ff10
225
226 #define FD1_IPC_DLI_ISOPIX1 0x0134
227 #define FD1_IPC_DLI_ISOPIX1_CONST 0x0000ff10
228
229 /* Sensor registers */
230 #define FD1_IPC_SENSOR_TH0 0x0140
231 #define FD1_IPC_SENSOR_TH0_CONST 0x20208080
232
233 #define FD1_IPC_SENSOR_TH1 0x0144
234 #define FD1_IPC_SENSOR_TH1_CONST 0
235
236 #define FD1_IPC_SENSOR_CTL0 0x0170
237 #define FD1_IPC_SENSOR_CTL0_CONST 0x00002201
238
239 #define FD1_IPC_SENSOR_CTL1 0x0174
240 #define FD1_IPC_SENSOR_CTL1_CONST 0
241
242 #define FD1_IPC_SENSOR_CTL2 0x0178
243 #define FD1_IPC_SENSOR_CTL2_X_SHIFT 16
244 #define FD1_IPC_SENSOR_CTL2_Y_SHIFT 0
245
246 #define FD1_IPC_SENSOR_CTL3 0x017c
247 #define FD1_IPC_SENSOR_CTL3_0_SHIFT 16
248 #define FD1_IPC_SENSOR_CTL3_1_SHIFT 0
249
250 /* Line memory pixel number register */
251 #define FD1_IPC_LMEM 0x01e0
252 #define FD1_IPC_LMEM_LINEAR 1024
253 #define FD1_IPC_LMEM_TILE 960
254
255 /* Internal Data (HW Version) */
256 #define FD1_IP_INTDATA 0x0800
257 #define FD1_IP_H3_ES1 0x02010101
258 #define FD1_IP_M3W 0x02010202
259 #define FD1_IP_H3 0x02010203
260
261 /* LUTs */
262 #define FD1_LUT_DIF_ADJ 0x1000
263 #define FD1_LUT_SAD_ADJ 0x1400
264 #define FD1_LUT_BLD_GAIN 0x1800
265 #define FD1_LUT_DIF_GAIN 0x1c00
266 #define FD1_LUT_MDET 0x2000
267
268 /**
269 * struct fdp1_fmt - The FDP1 internal format data
270 * @fourcc: the fourcc code, to match the V4L2 API
271 * @bpp: bits per pixel per plane
272 * @num_planes: number of planes
273 * @hsub: horizontal subsampling factor
274 * @vsub: vertical subsampling factor
275 * @fmt: 7-bit format code for the fdp1 hardware
276 * @swap_yc: the Y and C components are swapped (Y comes before C)
277 * @swap_uv: the U and V components are swapped (V comes before U)
278 * @swap: swap register control
279 * @types: types of queue this format is applicable to
280 */
281 struct fdp1_fmt {
282 u32 fourcc;
283 u8 bpp[3];
284 u8 num_planes;
285 u8 hsub;
286 u8 vsub;
287 u8 fmt;
288 bool swap_yc;
289 bool swap_uv;
290 u8 swap;
291 u8 types;
292 };
293
294 static const struct fdp1_fmt fdp1_formats[] = {
295 /* RGB formats are only supported by the Write Pixel Formatter */
296
297 { V4L2_PIX_FMT_RGB332, { 8, 0, 0 }, 1, 1, 1, 0x00, false, false,
298 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
299 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
300 FDP1_CAPTURE },
301 { V4L2_PIX_FMT_XRGB444, { 16, 0, 0 }, 1, 1, 1, 0x01, false, false,
302 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
303 FD1_RWPF_SWAP_WORD,
304 FDP1_CAPTURE },
305 { V4L2_PIX_FMT_XRGB555, { 16, 0, 0 }, 1, 1, 1, 0x04, false, false,
306 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
307 FD1_RWPF_SWAP_WORD,
308 FDP1_CAPTURE },
309 { V4L2_PIX_FMT_RGB565, { 16, 0, 0 }, 1, 1, 1, 0x06, false, false,
310 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
311 FD1_RWPF_SWAP_WORD,
312 FDP1_CAPTURE },
313 { V4L2_PIX_FMT_ABGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
314 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD,
315 FDP1_CAPTURE },
316 { V4L2_PIX_FMT_XBGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
317 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD,
318 FDP1_CAPTURE },
319 { V4L2_PIX_FMT_ARGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
320 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
321 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
322 FDP1_CAPTURE },
323 { V4L2_PIX_FMT_XRGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false,
324 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
325 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
326 FDP1_CAPTURE },
327 { V4L2_PIX_FMT_RGB24, { 24, 0, 0 }, 1, 1, 1, 0x15, false, false,
328 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
329 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
330 FDP1_CAPTURE },
331 { V4L2_PIX_FMT_BGR24, { 24, 0, 0 }, 1, 1, 1, 0x18, false, false,
332 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
333 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
334 FDP1_CAPTURE },
335 { V4L2_PIX_FMT_ARGB444, { 16, 0, 0 }, 1, 1, 1, 0x19, false, false,
336 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
337 FD1_RWPF_SWAP_WORD,
338 FDP1_CAPTURE },
339 { V4L2_PIX_FMT_ARGB555, { 16, 0, 0 }, 1, 1, 1, 0x1b, false, false,
340 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
341 FD1_RWPF_SWAP_WORD,
342 FDP1_CAPTURE },
343
344 /* YUV Formats are supported by Read and Write Pixel Formatters */
345
346 { V4L2_PIX_FMT_NV16M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, false,
347 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
348 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
349 FDP1_CAPTURE | FDP1_OUTPUT },
350 { V4L2_PIX_FMT_NV61M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, true,
351 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
352 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
353 FDP1_CAPTURE | FDP1_OUTPUT },
354 { V4L2_PIX_FMT_NV12M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, false,
355 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
356 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
357 FDP1_CAPTURE | FDP1_OUTPUT },
358 { V4L2_PIX_FMT_NV21M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, true,
359 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
360 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
361 FDP1_CAPTURE | FDP1_OUTPUT },
362 { V4L2_PIX_FMT_UYVY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, false,
363 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
364 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
365 FDP1_CAPTURE | FDP1_OUTPUT },
366 { V4L2_PIX_FMT_VYUY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, true,
367 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
368 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
369 FDP1_CAPTURE | FDP1_OUTPUT },
370 { V4L2_PIX_FMT_YUYV, { 16, 0, 0 }, 1, 2, 1, 0x47, true, false,
371 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
372 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
373 FDP1_CAPTURE | FDP1_OUTPUT },
374 { V4L2_PIX_FMT_YVYU, { 16, 0, 0 }, 1, 2, 1, 0x47, true, true,
375 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
376 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
377 FDP1_CAPTURE | FDP1_OUTPUT },
378 { V4L2_PIX_FMT_YUV444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, false,
379 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
380 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
381 FDP1_CAPTURE | FDP1_OUTPUT },
382 { V4L2_PIX_FMT_YVU444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, true,
383 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
384 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
385 FDP1_CAPTURE | FDP1_OUTPUT },
386 { V4L2_PIX_FMT_YUV422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, false,
387 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
388 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
389 FDP1_CAPTURE | FDP1_OUTPUT },
390 { V4L2_PIX_FMT_YVU422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, true,
391 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
392 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
393 FDP1_CAPTURE | FDP1_OUTPUT },
394 { V4L2_PIX_FMT_YUV420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, false,
395 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
396 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
397 FDP1_CAPTURE | FDP1_OUTPUT },
398 { V4L2_PIX_FMT_YVU420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, true,
399 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD |
400 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE,
401 FDP1_CAPTURE | FDP1_OUTPUT },
402 };
403
404 static int fdp1_fmt_is_rgb(const struct fdp1_fmt *fmt)
405 {
406 return fmt->fmt <= 0x1b; /* Last RGB code */
407 }
408
409 /*
410 * FDP1 Lookup tables range from 0...255 only
411 *
412 * Each table must be less than 256 entries, and all tables
413 * are padded out to 256 entries by duplicating the last value.
414 */
415 static const u8 fdp1_diff_adj[] = {
416 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf,
417 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3,
418 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff,
419 };
420
421 static const u8 fdp1_sad_adj[] = {
422 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf,
423 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3,
424 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff,
425 };
426
427 static const u8 fdp1_bld_gain[] = {
428 0x80,
429 };
430
431 static const u8 fdp1_dif_gain[] = {
432 0x80,
433 };
434
435 static const u8 fdp1_mdet[] = {
436 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
437 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
438 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
439 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
440 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
441 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
442 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
443 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
444 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
445 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
446 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
447 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
448 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
449 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
450 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
451 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
452 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
453 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
454 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
455 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f,
456 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
457 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf,
458 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7,
459 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf,
460 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
461 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf,
462 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7,
463 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf,
464 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7,
465 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef,
466 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7,
467 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff
468 };
469
470 /* Per-queue, driver-specific private data */
471 struct fdp1_q_data {
472 const struct fdp1_fmt *fmt;
473 struct v4l2_pix_format_mplane format;
474
475 unsigned int vsize;
476 unsigned int stride_y;
477 unsigned int stride_c;
478 };
479
480 static const struct fdp1_fmt *fdp1_find_format(u32 pixelformat)
481 {
482 const struct fdp1_fmt *fmt;
483 unsigned int i;
484
485 for (i = 0; i < ARRAY_SIZE(fdp1_formats); i++) {
486 fmt = &fdp1_formats[i];
487 if (fmt->fourcc == pixelformat)
488 return fmt;
489 }
490
491 return NULL;
492 }
493
494 enum fdp1_deint_mode {
495 FDP1_PROGRESSIVE = 0, /* Must be zero when !deinterlacing */
496 FDP1_ADAPT2D3D,
497 FDP1_FIXED2D,
498 FDP1_FIXED3D,
499 FDP1_PREVFIELD,
500 FDP1_NEXTFIELD,
501 };
502
503 #define FDP1_DEINT_MODE_USES_NEXT(mode) \
504 (mode == FDP1_ADAPT2D3D || \
505 mode == FDP1_FIXED3D || \
506 mode == FDP1_NEXTFIELD)
507
508 #define FDP1_DEINT_MODE_USES_PREV(mode) \
509 (mode == FDP1_ADAPT2D3D || \
510 mode == FDP1_FIXED3D || \
511 mode == FDP1_PREVFIELD)
512
513 /*
514 * FDP1 operates on potentially 3 fields, which are tracked
515 * from the VB buffers using this context structure.
516 * Will always be a field or a full frame, never two fields.
517 */
518 struct fdp1_field_buffer {
519 struct vb2_v4l2_buffer *vb;
520 dma_addr_t addrs[3];
521
522 /* Should be NONE:TOP:BOTTOM only */
523 enum v4l2_field field;
524
525 /* Flag to indicate this is the last field in the vb */
526 bool last_field;
527
528 /* Buffer queue lists */
529 struct list_head list;
530 };
531
532 struct fdp1_buffer {
533 struct v4l2_m2m_buffer m2m_buf;
534 struct fdp1_field_buffer fields[2];
535 unsigned int num_fields;
536 };
537
538 static inline struct fdp1_buffer *to_fdp1_buffer(struct vb2_v4l2_buffer *vb)
539 {
540 return container_of(vb, struct fdp1_buffer, m2m_buf.vb);
541 }
542
543 struct fdp1_job {
544 struct fdp1_field_buffer *previous;
545 struct fdp1_field_buffer *active;
546 struct fdp1_field_buffer *next;
547 struct fdp1_field_buffer *dst;
548
549 /* A job can only be on one list at a time */
550 struct list_head list;
551 };
552
553 struct fdp1_dev {
554 struct v4l2_device v4l2_dev;
555 struct video_device vfd;
556
557 struct mutex dev_mutex;
558 spinlock_t irqlock;
559 spinlock_t device_process_lock;
560
561 void __iomem *regs;
562 unsigned int irq;
563 struct device *dev;
564
565 /* Job Queues */
566 struct fdp1_job jobs[FDP1_NUMBER_JOBS];
567 struct list_head free_job_list;
568 struct list_head queued_job_list;
569 struct list_head hw_job_list;
570
571 unsigned int clk_rate;
572
573 struct rcar_fcp_device *fcp;
574 struct v4l2_m2m_dev *m2m_dev;
575 };
576
577 struct fdp1_ctx {
578 struct v4l2_fh fh;
579 struct fdp1_dev *fdp1;
580
581 struct v4l2_ctrl_handler hdl;
582 unsigned int sequence;
583
584 /* Processed buffers in this transaction */
585 u8 num_processed;
586
587 /* Transaction length (i.e. how many buffers per transaction) */
588 u32 translen;
589
590 /* Abort requested by m2m */
591 int aborting;
592
593 /* Deinterlace processing mode */
594 enum fdp1_deint_mode deint_mode;
595
596 /*
597 * Adaptive 2D/3D mode uses a shared mask
598 * This is allocated at streamon, if the ADAPT2D3D mode
599 * is requested
600 */
601 unsigned int smsk_size;
602 dma_addr_t smsk_addr[2];
603 void *smsk_cpu;
604
605 /* Capture pipeline, can specify an alpha value
606 * for supported formats. 0-255 only
607 */
608 unsigned char alpha;
609
610 /* Source and destination queue data */
611 struct fdp1_q_data out_q; /* HW Source */
612 struct fdp1_q_data cap_q; /* HW Destination */
613
614 /*
615 * Field Queues
616 * Interlaced fields are used on 3 occasions, and tracked in this list.
617 *
618 * V4L2 Buffers are tracked inside the fdp1_buffer
619 * and released when the last 'field' completes
620 */
621 struct list_head fields_queue;
622 unsigned int buffers_queued;
623
624 /*
625 * For de-interlacing we need to track our previous buffer
626 * while preparing our job lists.
627 */
628 struct fdp1_field_buffer *previous;
629 };
630
631 static inline struct fdp1_ctx *fh_to_ctx(struct v4l2_fh *fh)
632 {
633 return container_of(fh, struct fdp1_ctx, fh);
634 }
635
636 static struct fdp1_q_data *get_q_data(struct fdp1_ctx *ctx,
637 enum v4l2_buf_type type)
638 {
639 if (V4L2_TYPE_IS_OUTPUT(type))
640 return &ctx->out_q;
641 else
642 return &ctx->cap_q;
643 }
644
645 /*
646 * list_remove_job: Take the first item off the specified job list
647 *
648 * Returns: pointer to a job, or NULL if the list is empty.
649 */
650 static struct fdp1_job *list_remove_job(struct fdp1_dev *fdp1,
651 struct list_head *list)
652 {
653 struct fdp1_job *job;
654 unsigned long flags;
655
656 spin_lock_irqsave(&fdp1->irqlock, flags);
657 job = list_first_entry_or_null(list, struct fdp1_job, list);
658 if (job)
659 list_del(&job->list);
660 spin_unlock_irqrestore(&fdp1->irqlock, flags);
661
662 return job;
663 }
664
665 /*
666 * list_add_job: Add a job to the specified job list
667 *
668 * Returns: void - always succeeds
669 */
670 static void list_add_job(struct fdp1_dev *fdp1,
671 struct list_head *list,
672 struct fdp1_job *job)
673 {
674 unsigned long flags;
675
676 spin_lock_irqsave(&fdp1->irqlock, flags);
677 list_add_tail(&job->list, list);
678 spin_unlock_irqrestore(&fdp1->irqlock, flags);
679 }
680
681 static struct fdp1_job *fdp1_job_alloc(struct fdp1_dev *fdp1)
682 {
683 return list_remove_job(fdp1, &fdp1->free_job_list);
684 }
685
686 static void fdp1_job_free(struct fdp1_dev *fdp1, struct fdp1_job *job)
687 {
688 /* Ensure that all residue from previous jobs is gone */
689 memset(job, 0, sizeof(struct fdp1_job));
690
691 list_add_job(fdp1, &fdp1->free_job_list, job);
692 }
693
694 static void queue_job(struct fdp1_dev *fdp1, struct fdp1_job *job)
695 {
696 list_add_job(fdp1, &fdp1->queued_job_list, job);
697 }
698
699 static struct fdp1_job *get_queued_job(struct fdp1_dev *fdp1)
700 {
701 return list_remove_job(fdp1, &fdp1->queued_job_list);
702 }
703
704 static void queue_hw_job(struct fdp1_dev *fdp1, struct fdp1_job *job)
705 {
706 list_add_job(fdp1, &fdp1->hw_job_list, job);
707 }
708
709 static struct fdp1_job *get_hw_queued_job(struct fdp1_dev *fdp1)
710 {
711 return list_remove_job(fdp1, &fdp1->hw_job_list);
712 }
713
714 /*
715 * Buffer lists handling
716 */
717 static void fdp1_field_complete(struct fdp1_ctx *ctx,
718 struct fdp1_field_buffer *fbuf)
719 {
720 /* job->previous may be on the first field */
721 if (!fbuf)
722 return;
723
724 if (fbuf->last_field)
725 v4l2_m2m_buf_done(fbuf->vb, VB2_BUF_STATE_DONE);
726 }
727
728 static void fdp1_queue_field(struct fdp1_ctx *ctx,
729 struct fdp1_field_buffer *fbuf)
730 {
731 unsigned long flags;
732
733 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
734 list_add_tail(&fbuf->list, &ctx->fields_queue);
735 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
736
737 ctx->buffers_queued++;
738 }
739
740 static struct fdp1_field_buffer *fdp1_dequeue_field(struct fdp1_ctx *ctx)
741 {
742 struct fdp1_field_buffer *fbuf;
743 unsigned long flags;
744
745 ctx->buffers_queued--;
746
747 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
748 fbuf = list_first_entry_or_null(&ctx->fields_queue,
749 struct fdp1_field_buffer, list);
750 if (fbuf)
751 list_del(&fbuf->list);
752 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
753
754 return fbuf;
755 }
756
757 /*
758 * Return the next field in the queue - or NULL,
759 * without removing the item from the list
760 */
761 static struct fdp1_field_buffer *fdp1_peek_queued_field(struct fdp1_ctx *ctx)
762 {
763 struct fdp1_field_buffer *fbuf;
764 unsigned long flags;
765
766 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
767 fbuf = list_first_entry_or_null(&ctx->fields_queue,
768 struct fdp1_field_buffer, list);
769 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
770
771 return fbuf;
772 }
773
774 static u32 fdp1_read(struct fdp1_dev *fdp1, unsigned int reg)
775 {
776 u32 value = ioread32(fdp1->regs + reg);
777
778 if (debug >= 2)
779 dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg);
780
781 return value;
782 }
783
784 static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg)
785 {
786 if (debug >= 2)
787 dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg);
788
789 iowrite32(val, fdp1->regs + reg);
790 }
791
792 /* IPC registers are to be programmed with constant values */
793 static void fdp1_set_ipc_dli(struct fdp1_ctx *ctx)
794 {
795 struct fdp1_dev *fdp1 = ctx->fdp1;
796
797 fdp1_write(fdp1, FD1_IPC_SMSK_THRESH_CONST, FD1_IPC_SMSK_THRESH);
798 fdp1_write(fdp1, FD1_IPC_COMB_DET_CONST, FD1_IPC_COMB_DET);
799 fdp1_write(fdp1, FD1_IPC_MOTDEC_CONST, FD1_IPC_MOTDEC);
800
801 fdp1_write(fdp1, FD1_IPC_DLI_BLEND_CONST, FD1_IPC_DLI_BLEND);
802 fdp1_write(fdp1, FD1_IPC_DLI_HGAIN_CONST, FD1_IPC_DLI_HGAIN);
803 fdp1_write(fdp1, FD1_IPC_DLI_SPRS_CONST, FD1_IPC_DLI_SPRS);
804 fdp1_write(fdp1, FD1_IPC_DLI_ANGLE_CONST, FD1_IPC_DLI_ANGLE);
805 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX0_CONST, FD1_IPC_DLI_ISOPIX0);
806 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX1_CONST, FD1_IPC_DLI_ISOPIX1);
807 }
808
809
810 static void fdp1_set_ipc_sensor(struct fdp1_ctx *ctx)
811 {
812 struct fdp1_dev *fdp1 = ctx->fdp1;
813 struct fdp1_q_data *src_q_data = &ctx->out_q;
814 unsigned int x0, x1;
815 unsigned int hsize = src_q_data->format.width;
816 unsigned int vsize = src_q_data->format.height;
817
818 x0 = hsize / 3;
819 x1 = 2 * hsize / 3;
820
821 fdp1_write(fdp1, FD1_IPC_SENSOR_TH0_CONST, FD1_IPC_SENSOR_TH0);
822 fdp1_write(fdp1, FD1_IPC_SENSOR_TH1_CONST, FD1_IPC_SENSOR_TH1);
823 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL0_CONST, FD1_IPC_SENSOR_CTL0);
824 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL1_CONST, FD1_IPC_SENSOR_CTL1);
825
826 fdp1_write(fdp1, ((hsize - 1) << FD1_IPC_SENSOR_CTL2_X_SHIFT) |
827 ((vsize - 1) << FD1_IPC_SENSOR_CTL2_Y_SHIFT),
828 FD1_IPC_SENSOR_CTL2);
829
830 fdp1_write(fdp1, (x0 << FD1_IPC_SENSOR_CTL3_0_SHIFT) |
831 (x1 << FD1_IPC_SENSOR_CTL3_1_SHIFT),
832 FD1_IPC_SENSOR_CTL3);
833 }
834
835 /*
836 * fdp1_write_lut: Write a padded LUT to the hw
837 *
838 * FDP1 uses constant data for de-interlacing processing,
839 * with large tables. These hardware tables are all 256 bytes
840 * long, however they often contain repeated data at the end.
841 *
842 * The last byte of the table is written to all remaining entries.
843 */
844 static void fdp1_write_lut(struct fdp1_dev *fdp1, const u8 *lut,
845 unsigned int len, unsigned int base)
846 {
847 unsigned int i;
848 u8 pad;
849
850 /* Tables larger than the hw are clipped */
851 len = min(len, 256u);
852
853 for (i = 0; i < len; i++)
854 fdp1_write(fdp1, lut[i], base + (i*4));
855
856 /* Tables are padded with the last entry */
857 pad = lut[i-1];
858
859 for (; i < 256; i++)
860 fdp1_write(fdp1, pad, base + (i*4));
861 }
862
863 static void fdp1_set_lut(struct fdp1_dev *fdp1)
864 {
865 fdp1_write_lut(fdp1, fdp1_diff_adj, ARRAY_SIZE(fdp1_diff_adj),
866 FD1_LUT_DIF_ADJ);
867 fdp1_write_lut(fdp1, fdp1_sad_adj, ARRAY_SIZE(fdp1_sad_adj),
868 FD1_LUT_SAD_ADJ);
869 fdp1_write_lut(fdp1, fdp1_bld_gain, ARRAY_SIZE(fdp1_bld_gain),
870 FD1_LUT_BLD_GAIN);
871 fdp1_write_lut(fdp1, fdp1_dif_gain, ARRAY_SIZE(fdp1_dif_gain),
872 FD1_LUT_DIF_GAIN);
873 fdp1_write_lut(fdp1, fdp1_mdet, ARRAY_SIZE(fdp1_mdet),
874 FD1_LUT_MDET);
875 }
876
877 static void fdp1_configure_rpf(struct fdp1_ctx *ctx,
878 struct fdp1_job *job)
879 {
880 struct fdp1_dev *fdp1 = ctx->fdp1;
881 u32 picture_size;
882 u32 pstride;
883 u32 format;
884 u32 smsk_addr;
885
886 struct fdp1_q_data *q_data = &ctx->out_q;
887
888 /* Picture size is common to Source and Destination frames */
889 picture_size = (q_data->format.width << FD1_RPF_SIZE_H_SHIFT)
890 | (q_data->vsize << FD1_RPF_SIZE_V_SHIFT);
891
892 /* Strides */
893 pstride = q_data->stride_y << FD1_RPF_PSTRIDE_Y_SHIFT;
894 if (q_data->format.num_planes > 1)
895 pstride |= q_data->stride_c << FD1_RPF_PSTRIDE_C_SHIFT;
896
897 /* Format control */
898 format = q_data->fmt->fmt;
899 if (q_data->fmt->swap_yc)
900 format |= FD1_RPF_FORMAT_RSPYCS;
901
902 if (q_data->fmt->swap_uv)
903 format |= FD1_RPF_FORMAT_RSPUVS;
904
905 if (job->active->field == V4L2_FIELD_BOTTOM) {
906 format |= FD1_RPF_FORMAT_CF; /* Set for Bottom field */
907 smsk_addr = ctx->smsk_addr[0];
908 } else {
909 smsk_addr = ctx->smsk_addr[1];
910 }
911
912 /* Deint mode is non-zero when deinterlacing */
913 if (ctx->deint_mode)
914 format |= FD1_RPF_FORMAT_CIPM;
915
916 fdp1_write(fdp1, format, FD1_RPF_FORMAT);
917 fdp1_write(fdp1, q_data->fmt->swap, FD1_RPF_SWAP);
918 fdp1_write(fdp1, picture_size, FD1_RPF_SIZE);
919 fdp1_write(fdp1, pstride, FD1_RPF_PSTRIDE);
920 fdp1_write(fdp1, smsk_addr, FD1_RPF_SMSK_ADDR);
921
922 /* Previous Field Channel (CH0) */
923 if (job->previous)
924 fdp1_write(fdp1, job->previous->addrs[0], FD1_RPF0_ADDR_Y);
925
926 /* Current Field Channel (CH1) */
927 fdp1_write(fdp1, job->active->addrs[0], FD1_RPF1_ADDR_Y);
928 fdp1_write(fdp1, job->active->addrs[1], FD1_RPF1_ADDR_C0);
929 fdp1_write(fdp1, job->active->addrs[2], FD1_RPF1_ADDR_C1);
930
931 /* Next Field Channel (CH2) */
932 if (job->next)
933 fdp1_write(fdp1, job->next->addrs[0], FD1_RPF2_ADDR_Y);
934 }
935
936 static void fdp1_configure_wpf(struct fdp1_ctx *ctx,
937 struct fdp1_job *job)
938 {
939 struct fdp1_dev *fdp1 = ctx->fdp1;
940 struct fdp1_q_data *src_q_data = &ctx->out_q;
941 struct fdp1_q_data *q_data = &ctx->cap_q;
942 u32 pstride;
943 u32 format;
944 u32 swap;
945 u32 rndctl;
946
947 pstride = q_data->format.plane_fmt[0].bytesperline
948 << FD1_WPF_PSTRIDE_Y_SHIFT;
949
950 if (q_data->format.num_planes > 1)
951 pstride |= q_data->format.plane_fmt[1].bytesperline
952 << FD1_WPF_PSTRIDE_C_SHIFT;
953
954 format = q_data->fmt->fmt; /* Output Format Code */
955
956 if (q_data->fmt->swap_yc)
957 format |= FD1_WPF_FORMAT_WSPYCS;
958
959 if (q_data->fmt->swap_uv)
960 format |= FD1_WPF_FORMAT_WSPUVS;
961
962 if (fdp1_fmt_is_rgb(q_data->fmt)) {
963 /* Enable Colour Space conversion */
964 format |= FD1_WPF_FORMAT_CSC;
965
966 /* Set WRTM */
967 if (src_q_data->format.ycbcr_enc == V4L2_YCBCR_ENC_709)
968 format |= FD1_WPF_FORMAT_WRTM_709_16;
969 else if (src_q_data->format.quantization ==
970 V4L2_QUANTIZATION_FULL_RANGE)
971 format |= FD1_WPF_FORMAT_WRTM_601_0;
972 else
973 format |= FD1_WPF_FORMAT_WRTM_601_16;
974 }
975
976 /* Set an alpha value into the Pad Value */
977 format |= ctx->alpha << FD1_WPF_FORMAT_PDV_SHIFT;
978
979 /* Determine picture rounding and clipping */
980 rndctl = FD1_WPF_RNDCTL_CBRM; /* Rounding Off */
981 rndctl |= FD1_WPF_RNDCTL_CLMD_NOCLIP;
982
983 /* WPF Swap needs both ISWAP and OSWAP setting */
984 swap = q_data->fmt->swap << FD1_WPF_SWAP_OSWAP_SHIFT;
985 swap |= src_q_data->fmt->swap << FD1_WPF_SWAP_SSWAP_SHIFT;
986
987 fdp1_write(fdp1, format, FD1_WPF_FORMAT);
988 fdp1_write(fdp1, rndctl, FD1_WPF_RNDCTL);
989 fdp1_write(fdp1, swap, FD1_WPF_SWAP);
990 fdp1_write(fdp1, pstride, FD1_WPF_PSTRIDE);
991
992 fdp1_write(fdp1, job->dst->addrs[0], FD1_WPF_ADDR_Y);
993 fdp1_write(fdp1, job->dst->addrs[1], FD1_WPF_ADDR_C0);
994 fdp1_write(fdp1, job->dst->addrs[2], FD1_WPF_ADDR_C1);
995 }
996
997 static void fdp1_configure_deint_mode(struct fdp1_ctx *ctx,
998 struct fdp1_job *job)
999 {
1000 struct fdp1_dev *fdp1 = ctx->fdp1;
1001 u32 opmode = FD1_CTL_OPMODE_VIMD_NOINTERRUPT;
1002 u32 ipcmode = FD1_IPC_MODE_DLI; /* Always set */
1003 u32 channels = FD1_CTL_CHACT_WR | FD1_CTL_CHACT_RD1; /* Always on */
1004
1005 /* De-interlacing Mode */
1006 switch (ctx->deint_mode) {
1007 default:
1008 case FDP1_PROGRESSIVE:
1009 dprintk(fdp1, "Progressive Mode\n");
1010 opmode |= FD1_CTL_OPMODE_PRG;
1011 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D;
1012 break;
1013 case FDP1_ADAPT2D3D:
1014 dprintk(fdp1, "Adapt2D3D Mode\n");
1015 if (ctx->sequence == 0 || ctx->aborting)
1016 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D;
1017 else
1018 ipcmode |= FD1_IPC_MODE_DIM_ADAPT2D3D;
1019
1020 if (ctx->sequence > 1) {
1021 channels |= FD1_CTL_CHACT_SMW;
1022 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2;
1023 }
1024
1025 if (ctx->sequence > 2)
1026 channels |= FD1_CTL_CHACT_SMR;
1027
1028 break;
1029 case FDP1_FIXED3D:
1030 dprintk(fdp1, "Fixed 3D Mode\n");
1031 ipcmode |= FD1_IPC_MODE_DIM_FIXED3D;
1032 /* Except for first and last frame, enable all channels */
1033 if (!(ctx->sequence == 0 || ctx->aborting))
1034 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2;
1035 break;
1036 case FDP1_FIXED2D:
1037 dprintk(fdp1, "Fixed 2D Mode\n");
1038 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D;
1039 /* No extra channels enabled */
1040 break;
1041 case FDP1_PREVFIELD:
1042 dprintk(fdp1, "Previous Field Mode\n");
1043 ipcmode |= FD1_IPC_MODE_DIM_PREVFIELD;
1044 channels |= FD1_CTL_CHACT_RD0; /* Previous */
1045 break;
1046 case FDP1_NEXTFIELD:
1047 dprintk(fdp1, "Next Field Mode\n");
1048 ipcmode |= FD1_IPC_MODE_DIM_NEXTFIELD;
1049 channels |= FD1_CTL_CHACT_RD2; /* Next */
1050 break;
1051 }
1052
1053 fdp1_write(fdp1, channels, FD1_CTL_CHACT);
1054 fdp1_write(fdp1, opmode, FD1_CTL_OPMODE);
1055 fdp1_write(fdp1, ipcmode, FD1_IPC_MODE);
1056 }
1057
1058 /*
1059 * fdp1_device_process() - Run the hardware
1060 *
1061 * Configure and start the hardware to generate a single frame
1062 * of output given our input parameters.
1063 */
1064 static int fdp1_device_process(struct fdp1_ctx *ctx)
1065
1066 {
1067 struct fdp1_dev *fdp1 = ctx->fdp1;
1068 struct fdp1_job *job;
1069 unsigned long flags;
1070
1071 spin_lock_irqsave(&fdp1->device_process_lock, flags);
1072
1073 /* Get a job to process */
1074 job = get_queued_job(fdp1);
1075 if (!job) {
1076 /*
1077 * VINT can call us to see if we can queue another job.
1078 * If we have no work to do, we simply return.
1079 */
1080 spin_unlock_irqrestore(&fdp1->device_process_lock, flags);
1081 return 0;
1082 }
1083
1084 /* First Frame only? ... */
1085 fdp1_write(fdp1, FD1_CTL_CLKCTRL_CSTP_N, FD1_CTL_CLKCTRL);
1086
1087 /* Set the mode, and configuration */
1088 fdp1_configure_deint_mode(ctx, job);
1089
1090 /* DLI Static Configuration */
1091 fdp1_set_ipc_dli(ctx);
1092
1093 /* Sensor Configuration */
1094 fdp1_set_ipc_sensor(ctx);
1095
1096 /* Setup the source picture */
1097 fdp1_configure_rpf(ctx, job);
1098
1099 /* Setup the destination picture */
1100 fdp1_configure_wpf(ctx, job);
1101
1102 /* Line Memory Pixel Number Register for linear access */
1103 fdp1_write(fdp1, FD1_IPC_LMEM_LINEAR, FD1_IPC_LMEM);
1104
1105 /* Enable Interrupts */
1106 fdp1_write(fdp1, FD1_CTL_IRQ_MASK, FD1_CTL_IRQENB);
1107
1108 /* Finally, the Immediate Registers */
1109
1110 /* This job is now in the HW queue */
1111 queue_hw_job(fdp1, job);
1112
1113 /* Start the command */
1114 fdp1_write(fdp1, FD1_CTL_CMD_STRCMD, FD1_CTL_CMD);
1115
1116 /* Registers will update to HW at next VINT */
1117 fdp1_write(fdp1, FD1_CTL_REGEND_REGEND, FD1_CTL_REGEND);
1118
1119 /* Enable VINT Generator */
1120 fdp1_write(fdp1, FD1_CTL_SGCMD_SGEN, FD1_CTL_SGCMD);
1121
1122 spin_unlock_irqrestore(&fdp1->device_process_lock, flags);
1123
1124 return 0;
1125 }
1126
1127 /*
1128 * mem2mem callbacks
1129 */
1130
1131 /*
1132 * job_ready() - check whether an instance is ready to be scheduled to run
1133 */
1134 static int fdp1_m2m_job_ready(void *priv)
1135 {
1136 struct fdp1_ctx *ctx = priv;
1137 struct fdp1_q_data *src_q_data = &ctx->out_q;
1138 int srcbufs = 1;
1139 int dstbufs = 1;
1140
1141 dprintk(ctx->fdp1, "+ Src: %d : Dst: %d\n",
1142 v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx),
1143 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx));
1144
1145 /* One output buffer is required for each field */
1146 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field))
1147 dstbufs = 2;
1148
1149 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < srcbufs
1150 || v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < dstbufs) {
1151 dprintk(ctx->fdp1, "Not enough buffers available\n");
1152 return 0;
1153 }
1154
1155 return 1;
1156 }
1157
1158 static void fdp1_m2m_job_abort(void *priv)
1159 {
1160 struct fdp1_ctx *ctx = priv;
1161
1162 dprintk(ctx->fdp1, "+\n");
1163
1164 /* Will cancel the transaction in the next interrupt handler */
1165 ctx->aborting = 1;
1166
1167 /* Immediate abort sequence */
1168 fdp1_write(ctx->fdp1, 0, FD1_CTL_SGCMD);
1169 fdp1_write(ctx->fdp1, FD1_CTL_SRESET_SRST, FD1_CTL_SRESET);
1170 }
1171
1172 /*
1173 * fdp1_prepare_job: Prepare and queue a new job for a single action of work
1174 *
1175 * Prepare the next field, (or frame in progressive) and an output
1176 * buffer for the hardware to perform a single operation.
1177 */
1178 static struct fdp1_job *fdp1_prepare_job(struct fdp1_ctx *ctx)
1179 {
1180 struct vb2_v4l2_buffer *vbuf;
1181 struct fdp1_buffer *fbuf;
1182 struct fdp1_dev *fdp1 = ctx->fdp1;
1183 struct fdp1_job *job;
1184 unsigned int buffers_required = 1;
1185
1186 dprintk(fdp1, "+\n");
1187
1188 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode))
1189 buffers_required = 2;
1190
1191 if (ctx->buffers_queued < buffers_required)
1192 return NULL;
1193
1194 job = fdp1_job_alloc(fdp1);
1195 if (!job) {
1196 dprintk(fdp1, "No free jobs currently available\n");
1197 return NULL;
1198 }
1199
1200 job->active = fdp1_dequeue_field(ctx);
1201 if (!job->active) {
1202 /* Buffer check should prevent this ever happening */
1203 dprintk(fdp1, "No input buffers currently available\n");
1204
1205 fdp1_job_free(fdp1, job);
1206 return NULL;
1207 }
1208
1209 dprintk(fdp1, "+ Buffer en-route...\n");
1210
1211 /* Source buffers have been prepared on our buffer_queue
1212 * Prepare our Output buffer
1213 */
1214 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1215 fbuf = to_fdp1_buffer(vbuf);
1216 job->dst = &fbuf->fields[0];
1217
1218 job->active->vb->sequence = ctx->sequence;
1219 job->dst->vb->sequence = ctx->sequence;
1220 ctx->sequence++;
1221
1222 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) {
1223 job->previous = ctx->previous;
1224
1225 /* Active buffer becomes the next job's previous buffer */
1226 ctx->previous = job->active;
1227 }
1228
1229 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode)) {
1230 /* Must be called after 'active' is dequeued */
1231 job->next = fdp1_peek_queued_field(ctx);
1232 }
1233
1234 /* Transfer timestamps and flags from src->dst */
1235
1236 job->dst->vb->vb2_buf.timestamp = job->active->vb->vb2_buf.timestamp;
1237
1238 job->dst->vb->flags = job->active->vb->flags &
1239 V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
1240
1241 /* Ideally, the frame-end function will just 'check' to see
1242 * if there are more jobs instead
1243 */
1244 ctx->translen++;
1245
1246 /* Finally, Put this job on the processing queue */
1247 queue_job(fdp1, job);
1248
1249 dprintk(fdp1, "Job Queued translen = %d\n", ctx->translen);
1250
1251 return job;
1252 }
1253
1254 /* fdp1_m2m_device_run() - prepares and starts the device for an M2M task
1255 *
1256 * A single input buffer is taken and serialised into our fdp1_buffer
1257 * queue. The queue is then processed to create as many jobs as possible
1258 * from our available input.
1259 */
1260 static void fdp1_m2m_device_run(void *priv)
1261 {
1262 struct fdp1_ctx *ctx = priv;
1263 struct fdp1_dev *fdp1 = ctx->fdp1;
1264 struct vb2_v4l2_buffer *src_vb;
1265 struct fdp1_buffer *buf;
1266 unsigned int i;
1267
1268 dprintk(fdp1, "+\n");
1269
1270 ctx->translen = 0;
1271
1272 /* Get our incoming buffer of either one or two fields, or one frame */
1273 src_vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1274 buf = to_fdp1_buffer(src_vb);
1275
1276 for (i = 0; i < buf->num_fields; i++) {
1277 struct fdp1_field_buffer *fbuf = &buf->fields[i];
1278
1279 fdp1_queue_field(ctx, fbuf);
1280 dprintk(fdp1, "Queued Buffer [%d] last_field:%d\n",
1281 i, fbuf->last_field);
1282 }
1283
1284 /* Queue as many jobs as our data provides for */
1285 while (fdp1_prepare_job(ctx))
1286 ;
1287
1288 if (ctx->translen == 0) {
1289 dprintk(fdp1, "No jobs were processed. M2M action complete\n");
1290 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx);
1291 return;
1292 }
1293
1294 /* Kick the job processing action */
1295 fdp1_device_process(ctx);
1296 }
1297
1298 /*
1299 * device_frame_end:
1300 *
1301 * Handles the M2M level after a buffer completion event.
1302 */
1303 static void device_frame_end(struct fdp1_dev *fdp1,
1304 enum vb2_buffer_state state)
1305 {
1306 struct fdp1_ctx *ctx;
1307 unsigned long flags;
1308 struct fdp1_job *job = get_hw_queued_job(fdp1);
1309
1310 dprintk(fdp1, "+\n");
1311
1312 ctx = v4l2_m2m_get_curr_priv(fdp1->m2m_dev);
1313
1314 if (ctx == NULL) {
1315 v4l2_err(&fdp1->v4l2_dev,
1316 "Instance released before the end of transaction\n");
1317 return;
1318 }
1319
1320 ctx->num_processed++;
1321
1322 /*
1323 * fdp1_field_complete will call buf_done only when the last vb2_buffer
1324 * reference is complete
1325 */
1326 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode))
1327 fdp1_field_complete(ctx, job->previous);
1328 else
1329 fdp1_field_complete(ctx, job->active);
1330
1331 spin_lock_irqsave(&fdp1->irqlock, flags);
1332 v4l2_m2m_buf_done(job->dst->vb, state);
1333 job->dst = NULL;
1334 spin_unlock_irqrestore(&fdp1->irqlock, flags);
1335
1336 /* Move this job back to the free job list */
1337 fdp1_job_free(fdp1, job);
1338
1339 dprintk(fdp1, "curr_ctx->num_processed %d curr_ctx->translen %d\n",
1340 ctx->num_processed, ctx->translen);
1341
1342 if (ctx->num_processed == ctx->translen ||
1343 ctx->aborting) {
1344 dprintk(ctx->fdp1, "Finishing transaction\n");
1345 ctx->num_processed = 0;
1346 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx);
1347 } else {
1348 /*
1349 * For pipelined performance support, this would
1350 * be called from a VINT handler
1351 */
1352 fdp1_device_process(ctx);
1353 }
1354 }
1355
1356 /*
1357 * video ioctls
1358 */
1359 static int fdp1_vidioc_querycap(struct file *file, void *priv,
1360 struct v4l2_capability *cap)
1361 {
1362 strlcpy(cap->driver, DRIVER_NAME, sizeof(cap->driver));
1363 strlcpy(cap->card, DRIVER_NAME, sizeof(cap->card));
1364 snprintf(cap->bus_info, sizeof(cap->bus_info),
1365 "platform:%s", DRIVER_NAME);
1366 return 0;
1367 }
1368
1369 static int fdp1_enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1370 {
1371 unsigned int i, num;
1372
1373 num = 0;
1374
1375 for (i = 0; i < ARRAY_SIZE(fdp1_formats); ++i) {
1376 if (fdp1_formats[i].types & type) {
1377 if (num == f->index)
1378 break;
1379 ++num;
1380 }
1381 }
1382
1383 /* Format not found */
1384 if (i >= ARRAY_SIZE(fdp1_formats))
1385 return -EINVAL;
1386
1387 /* Format found */
1388 f->pixelformat = fdp1_formats[i].fourcc;
1389
1390 return 0;
1391 }
1392
1393 static int fdp1_enum_fmt_vid_cap(struct file *file, void *priv,
1394 struct v4l2_fmtdesc *f)
1395 {
1396 return fdp1_enum_fmt(f, FDP1_CAPTURE);
1397 }
1398
1399 static int fdp1_enum_fmt_vid_out(struct file *file, void *priv,
1400 struct v4l2_fmtdesc *f)
1401 {
1402 return fdp1_enum_fmt(f, FDP1_OUTPUT);
1403 }
1404
1405 static int fdp1_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1406 {
1407 struct fdp1_q_data *q_data;
1408 struct fdp1_ctx *ctx = fh_to_ctx(priv);
1409
1410 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type))
1411 return -EINVAL;
1412
1413 q_data = get_q_data(ctx, f->type);
1414 f->fmt.pix_mp = q_data->format;
1415
1416 return 0;
1417 }
1418
1419 static void fdp1_compute_stride(struct v4l2_pix_format_mplane *pix,
1420 const struct fdp1_fmt *fmt)
1421 {
1422 unsigned int i;
1423
1424 /* Compute and clamp the stride and image size. */
1425 for (i = 0; i < min_t(unsigned int, fmt->num_planes, 2U); ++i) {
1426 unsigned int hsub = i > 0 ? fmt->hsub : 1;
1427 unsigned int vsub = i > 0 ? fmt->vsub : 1;
1428 /* From VSP : TODO: Confirm alignment limits for FDP1 */
1429 unsigned int align = 128;
1430 unsigned int bpl;
1431
1432 bpl = clamp_t(unsigned int, pix->plane_fmt[i].bytesperline,
1433 pix->width / hsub * fmt->bpp[i] / 8,
1434 round_down(FDP1_MAX_STRIDE, align));
1435
1436 pix->plane_fmt[i].bytesperline = round_up(bpl, align);
1437 pix->plane_fmt[i].sizeimage = pix->plane_fmt[i].bytesperline
1438 * pix->height / vsub;
1439
1440 memset(pix->plane_fmt[i].reserved, 0,
1441 sizeof(pix->plane_fmt[i].reserved));
1442 }
1443
1444 if (fmt->num_planes == 3) {
1445 /* The two chroma planes must have the same stride. */
1446 pix->plane_fmt[2].bytesperline = pix->plane_fmt[1].bytesperline;
1447 pix->plane_fmt[2].sizeimage = pix->plane_fmt[1].sizeimage;
1448
1449 memset(pix->plane_fmt[2].reserved, 0,
1450 sizeof(pix->plane_fmt[2].reserved));
1451 }
1452 }
1453
1454 static void fdp1_try_fmt_output(struct fdp1_ctx *ctx,
1455 const struct fdp1_fmt **fmtinfo,
1456 struct v4l2_pix_format_mplane *pix)
1457 {
1458 const struct fdp1_fmt *fmt;
1459 unsigned int width;
1460 unsigned int height;
1461
1462 /* Validate the pixel format to ensure the output queue supports it. */
1463 fmt = fdp1_find_format(pix->pixelformat);
1464 if (!fmt || !(fmt->types & FDP1_OUTPUT))
1465 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV);
1466
1467 if (fmtinfo)
1468 *fmtinfo = fmt;
1469
1470 pix->pixelformat = fmt->fourcc;
1471 pix->num_planes = fmt->num_planes;
1472
1473 /*
1474 * Progressive video and all interlaced field orders are acceptable.
1475 * Default to V4L2_FIELD_INTERLACED.
1476 */
1477 if (pix->field != V4L2_FIELD_NONE &&
1478 pix->field != V4L2_FIELD_ALTERNATE &&
1479 !V4L2_FIELD_HAS_BOTH(pix->field))
1480 pix->field = V4L2_FIELD_INTERLACED;
1481
1482 /*
1483 * The deinterlacer doesn't care about the colorspace, accept all values
1484 * and default to V4L2_COLORSPACE_SMPTE170M. The YUV to RGB conversion
1485 * at the output of the deinterlacer supports a subset of encodings and
1486 * quantization methods and will only be available when the colorspace
1487 * allows it.
1488 */
1489 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT)
1490 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1491
1492 /*
1493 * Align the width and height for YUV 4:2:2 and 4:2:0 formats and clamp
1494 * them to the supported frame size range. The height boundary are
1495 * related to the full frame, divide them by two when the format passes
1496 * fields in separate buffers.
1497 */
1498 width = round_down(pix->width, fmt->hsub);
1499 pix->width = clamp(width, FDP1_MIN_W, FDP1_MAX_W);
1500
1501 height = round_down(pix->height, fmt->vsub);
1502 if (pix->field == V4L2_FIELD_ALTERNATE)
1503 pix->height = clamp(height, FDP1_MIN_H / 2, FDP1_MAX_H / 2);
1504 else
1505 pix->height = clamp(height, FDP1_MIN_H, FDP1_MAX_H);
1506
1507 fdp1_compute_stride(pix, fmt);
1508 }
1509
1510 static void fdp1_try_fmt_capture(struct fdp1_ctx *ctx,
1511 const struct fdp1_fmt **fmtinfo,
1512 struct v4l2_pix_format_mplane *pix)
1513 {
1514 struct fdp1_q_data *src_data = &ctx->out_q;
1515 enum v4l2_colorspace colorspace;
1516 enum v4l2_ycbcr_encoding ycbcr_enc;
1517 enum v4l2_quantization quantization;
1518 const struct fdp1_fmt *fmt;
1519 bool allow_rgb;
1520
1521 /*
1522 * Validate the pixel format. We can only accept RGB output formats if
1523 * the input encoding and quantization are compatible with the format
1524 * conversions supported by the hardware. The supported combinations are
1525 *
1526 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_LIM_RANGE
1527 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_FULL_RANGE
1528 * V4L2_YCBCR_ENC_709 + V4L2_QUANTIZATION_LIM_RANGE
1529 */
1530 colorspace = src_data->format.colorspace;
1531
1532 ycbcr_enc = src_data->format.ycbcr_enc;
1533 if (ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT)
1534 ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(colorspace);
1535
1536 quantization = src_data->format.quantization;
1537 if (quantization == V4L2_QUANTIZATION_DEFAULT)
1538 quantization = V4L2_MAP_QUANTIZATION_DEFAULT(false, colorspace,
1539 ycbcr_enc);
1540
1541 allow_rgb = ycbcr_enc == V4L2_YCBCR_ENC_601 ||
1542 (ycbcr_enc == V4L2_YCBCR_ENC_709 &&
1543 quantization == V4L2_QUANTIZATION_LIM_RANGE);
1544
1545 fmt = fdp1_find_format(pix->pixelformat);
1546 if (!fmt || (!allow_rgb && fdp1_fmt_is_rgb(fmt)))
1547 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV);
1548
1549 if (fmtinfo)
1550 *fmtinfo = fmt;
1551
1552 pix->pixelformat = fmt->fourcc;
1553 pix->num_planes = fmt->num_planes;
1554 pix->field = V4L2_FIELD_NONE;
1555
1556 /*
1557 * The colorspace on the capture queue is copied from the output queue
1558 * as the hardware can't change the colorspace. It can convert YCbCr to
1559 * RGB though, in which case the encoding and quantization are set to
1560 * default values as anything else wouldn't make sense.
1561 */
1562 pix->colorspace = src_data->format.colorspace;
1563 pix->xfer_func = src_data->format.xfer_func;
1564
1565 if (fdp1_fmt_is_rgb(fmt)) {
1566 pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1567 pix->quantization = V4L2_QUANTIZATION_DEFAULT;
1568 } else {
1569 pix->ycbcr_enc = src_data->format.ycbcr_enc;
1570 pix->quantization = src_data->format.quantization;
1571 }
1572
1573 /*
1574 * The frame width is identical to the output queue, and the height is
1575 * either doubled or identical depending on whether the output queue
1576 * field order contains one or two fields per frame.
1577 */
1578 pix->width = src_data->format.width;
1579 if (src_data->format.field == V4L2_FIELD_ALTERNATE)
1580 pix->height = 2 * src_data->format.height;
1581 else
1582 pix->height = src_data->format.height;
1583
1584 fdp1_compute_stride(pix, fmt);
1585 }
1586
1587 static int fdp1_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1588 {
1589 struct fdp1_ctx *ctx = fh_to_ctx(priv);
1590
1591 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1592 fdp1_try_fmt_output(ctx, NULL, &f->fmt.pix_mp);
1593 else
1594 fdp1_try_fmt_capture(ctx, NULL, &f->fmt.pix_mp);
1595
1596 dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n",
1597 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture",
1598 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat,
1599 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field);
1600
1601 return 0;
1602 }
1603
1604 static void fdp1_set_format(struct fdp1_ctx *ctx,
1605 struct v4l2_pix_format_mplane *pix,
1606 enum v4l2_buf_type type)
1607 {
1608 struct fdp1_q_data *q_data = get_q_data(ctx, type);
1609 const struct fdp1_fmt *fmtinfo;
1610
1611 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1612 fdp1_try_fmt_output(ctx, &fmtinfo, pix);
1613 else
1614 fdp1_try_fmt_capture(ctx, &fmtinfo, pix);
1615
1616 q_data->fmt = fmtinfo;
1617 q_data->format = *pix;
1618
1619 q_data->vsize = pix->height;
1620 if (pix->field != V4L2_FIELD_NONE)
1621 q_data->vsize /= 2;
1622
1623 q_data->stride_y = pix->plane_fmt[0].bytesperline;
1624 q_data->stride_c = pix->plane_fmt[1].bytesperline;
1625
1626 /* Adjust strides for interleaved buffers */
1627 if (pix->field == V4L2_FIELD_INTERLACED ||
1628 pix->field == V4L2_FIELD_INTERLACED_TB ||
1629 pix->field == V4L2_FIELD_INTERLACED_BT) {
1630 q_data->stride_y *= 2;
1631 q_data->stride_c *= 2;
1632 }
1633
1634 /* Propagate the format from the output node to the capture node. */
1635 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1636 struct fdp1_q_data *dst_data = &ctx->cap_q;
1637
1638 /*
1639 * Copy the format, clear the per-plane bytes per line and image
1640 * size, override the field and double the height if needed.
1641 */
1642 dst_data->format = q_data->format;
1643 memset(dst_data->format.plane_fmt, 0,
1644 sizeof(dst_data->format.plane_fmt));
1645
1646 dst_data->format.field = V4L2_FIELD_NONE;
1647 if (pix->field == V4L2_FIELD_ALTERNATE)
1648 dst_data->format.height *= 2;
1649
1650 fdp1_try_fmt_capture(ctx, &dst_data->fmt, &dst_data->format);
1651
1652 dst_data->vsize = dst_data->format.height;
1653 dst_data->stride_y = dst_data->format.plane_fmt[0].bytesperline;
1654 dst_data->stride_c = dst_data->format.plane_fmt[1].bytesperline;
1655 }
1656 }
1657
1658 static int fdp1_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1659 {
1660 struct fdp1_ctx *ctx = fh_to_ctx(priv);
1661 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
1662 struct vb2_queue *vq = v4l2_m2m_get_vq(m2m_ctx, f->type);
1663
1664 if (vb2_is_busy(vq)) {
1665 v4l2_err(&ctx->fdp1->v4l2_dev, "%s queue busy\n", __func__);
1666 return -EBUSY;
1667 }
1668
1669 fdp1_set_format(ctx, &f->fmt.pix_mp, f->type);
1670
1671 dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n",
1672 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture",
1673 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat,
1674 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field);
1675
1676 return 0;
1677 }
1678
1679 static int fdp1_g_ctrl(struct v4l2_ctrl *ctrl)
1680 {
1681 struct fdp1_ctx *ctx =
1682 container_of(ctrl->handler, struct fdp1_ctx, hdl);
1683 struct fdp1_q_data *src_q_data = &ctx->out_q;
1684
1685 switch (ctrl->id) {
1686 case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE:
1687 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field))
1688 ctrl->val = 2;
1689 else
1690 ctrl->val = 1;
1691 return 0;
1692 }
1693
1694 return 1;
1695 }
1696
1697 static int fdp1_s_ctrl(struct v4l2_ctrl *ctrl)
1698 {
1699 struct fdp1_ctx *ctx =
1700 container_of(ctrl->handler, struct fdp1_ctx, hdl);
1701
1702 switch (ctrl->id) {
1703 case V4L2_CID_ALPHA_COMPONENT:
1704 ctx->alpha = ctrl->val;
1705 break;
1706
1707 case V4L2_CID_DEINTERLACING_MODE:
1708 ctx->deint_mode = ctrl->val;
1709 break;
1710 }
1711
1712 return 0;
1713 }
1714
1715 static const struct v4l2_ctrl_ops fdp1_ctrl_ops = {
1716 .s_ctrl = fdp1_s_ctrl,
1717 .g_volatile_ctrl = fdp1_g_ctrl,
1718 };
1719
1720 static const char * const fdp1_ctrl_deint_menu[] = {
1721 "Progressive",
1722 "Adaptive 2D/3D",
1723 "Fixed 2D",
1724 "Fixed 3D",
1725 "Previous field",
1726 "Next field",
1727 NULL
1728 };
1729
1730 static const struct v4l2_ioctl_ops fdp1_ioctl_ops = {
1731 .vidioc_querycap = fdp1_vidioc_querycap,
1732
1733 .vidioc_enum_fmt_vid_cap_mplane = fdp1_enum_fmt_vid_cap,
1734 .vidioc_enum_fmt_vid_out_mplane = fdp1_enum_fmt_vid_out,
1735 .vidioc_g_fmt_vid_cap_mplane = fdp1_g_fmt,
1736 .vidioc_g_fmt_vid_out_mplane = fdp1_g_fmt,
1737 .vidioc_try_fmt_vid_cap_mplane = fdp1_try_fmt,
1738 .vidioc_try_fmt_vid_out_mplane = fdp1_try_fmt,
1739 .vidioc_s_fmt_vid_cap_mplane = fdp1_s_fmt,
1740 .vidioc_s_fmt_vid_out_mplane = fdp1_s_fmt,
1741
1742 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1743 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1744 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1745 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1746 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
1747 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
1748 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1749
1750 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1751 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1752
1753 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1754 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1755 };
1756
1757 /*
1758 * Queue operations
1759 */
1760
1761 static int fdp1_queue_setup(struct vb2_queue *vq,
1762 unsigned int *nbuffers, unsigned int *nplanes,
1763 unsigned int sizes[],
1764 struct device *alloc_ctxs[])
1765 {
1766 struct fdp1_ctx *ctx = vb2_get_drv_priv(vq);
1767 struct fdp1_q_data *q_data;
1768 unsigned int i;
1769
1770 q_data = get_q_data(ctx, vq->type);
1771
1772 if (*nplanes) {
1773 if (*nplanes > FDP1_MAX_PLANES)
1774 return -EINVAL;
1775
1776 return 0;
1777 }
1778
1779 *nplanes = q_data->format.num_planes;
1780
1781 for (i = 0; i < *nplanes; i++)
1782 sizes[i] = q_data->format.plane_fmt[i].sizeimage;
1783
1784 return 0;
1785 }
1786
1787 static void fdp1_buf_prepare_field(struct fdp1_q_data *q_data,
1788 struct vb2_v4l2_buffer *vbuf,
1789 unsigned int field_num)
1790 {
1791 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf);
1792 struct fdp1_field_buffer *fbuf = &buf->fields[field_num];
1793 unsigned int num_fields;
1794 unsigned int i;
1795
1796 num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1;
1797
1798 fbuf->vb = vbuf;
1799 fbuf->last_field = (field_num + 1) == num_fields;
1800
1801 for (i = 0; i < vbuf->vb2_buf.num_planes; ++i)
1802 fbuf->addrs[i] = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, i);
1803
1804 switch (vbuf->field) {
1805 case V4L2_FIELD_INTERLACED:
1806 /*
1807 * Interlaced means bottom-top for 60Hz TV standards (NTSC) and
1808 * top-bottom for 50Hz. As TV standards are not applicable to
1809 * the mem-to-mem API, use the height as a heuristic.
1810 */
1811 fbuf->field = (q_data->format.height < 576) == field_num
1812 ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM;
1813 break;
1814 case V4L2_FIELD_INTERLACED_TB:
1815 case V4L2_FIELD_SEQ_TB:
1816 fbuf->field = field_num ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
1817 break;
1818 case V4L2_FIELD_INTERLACED_BT:
1819 case V4L2_FIELD_SEQ_BT:
1820 fbuf->field = field_num ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM;
1821 break;
1822 default:
1823 fbuf->field = vbuf->field;
1824 break;
1825 }
1826
1827 /* Buffer is completed */
1828 if (!field_num)
1829 return;
1830
1831 /* Adjust buffer addresses for second field */
1832 switch (vbuf->field) {
1833 case V4L2_FIELD_INTERLACED:
1834 case V4L2_FIELD_INTERLACED_TB:
1835 case V4L2_FIELD_INTERLACED_BT:
1836 for (i = 0; i < vbuf->vb2_buf.num_planes; i++)
1837 fbuf->addrs[i] +=
1838 (i == 0 ? q_data->stride_y : q_data->stride_c);
1839 break;
1840 case V4L2_FIELD_SEQ_TB:
1841 case V4L2_FIELD_SEQ_BT:
1842 for (i = 0; i < vbuf->vb2_buf.num_planes; i++)
1843 fbuf->addrs[i] += q_data->vsize *
1844 (i == 0 ? q_data->stride_y : q_data->stride_c);
1845 break;
1846 }
1847 }
1848
1849 static int fdp1_buf_prepare(struct vb2_buffer *vb)
1850 {
1851 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1852 struct fdp1_q_data *q_data = get_q_data(ctx, vb->vb2_queue->type);
1853 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1854 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf);
1855 unsigned int i;
1856
1857 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) {
1858 bool field_valid = true;
1859
1860 /* Validate the buffer field. */
1861 switch (q_data->format.field) {
1862 case V4L2_FIELD_NONE:
1863 if (vbuf->field != V4L2_FIELD_NONE)
1864 field_valid = false;
1865 break;
1866
1867 case V4L2_FIELD_ALTERNATE:
1868 if (vbuf->field != V4L2_FIELD_TOP &&
1869 vbuf->field != V4L2_FIELD_BOTTOM)
1870 field_valid = false;
1871 break;
1872
1873 case V4L2_FIELD_INTERLACED:
1874 case V4L2_FIELD_SEQ_TB:
1875 case V4L2_FIELD_SEQ_BT:
1876 case V4L2_FIELD_INTERLACED_TB:
1877 case V4L2_FIELD_INTERLACED_BT:
1878 if (vbuf->field != q_data->format.field)
1879 field_valid = false;
1880 break;
1881 }
1882
1883 if (!field_valid) {
1884 dprintk(ctx->fdp1,
1885 "buffer field %u invalid for format field %u\n",
1886 vbuf->field, q_data->format.field);
1887 return -EINVAL;
1888 }
1889 } else {
1890 vbuf->field = V4L2_FIELD_NONE;
1891 }
1892
1893 /* Validate the planes sizes. */
1894 for (i = 0; i < q_data->format.num_planes; i++) {
1895 unsigned long size = q_data->format.plane_fmt[i].sizeimage;
1896
1897 if (vb2_plane_size(vb, i) < size) {
1898 dprintk(ctx->fdp1,
1899 "data will not fit into plane [%u/%u] (%lu < %lu)\n",
1900 i, q_data->format.num_planes,
1901 vb2_plane_size(vb, i), size);
1902 return -EINVAL;
1903 }
1904
1905 /* We have known size formats all around */
1906 vb2_set_plane_payload(vb, i, size);
1907 }
1908
1909 buf->num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1;
1910 for (i = 0; i < buf->num_fields; ++i)
1911 fdp1_buf_prepare_field(q_data, vbuf, i);
1912
1913 return 0;
1914 }
1915
1916 static void fdp1_buf_queue(struct vb2_buffer *vb)
1917 {
1918 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1919 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
1920
1921 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
1922 }
1923
1924 static int fdp1_start_streaming(struct vb2_queue *q, unsigned int count)
1925 {
1926 struct fdp1_ctx *ctx = vb2_get_drv_priv(q);
1927 struct fdp1_q_data *q_data = get_q_data(ctx, q->type);
1928
1929 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
1930 /*
1931 * Force our deint_mode when we are progressive,
1932 * ignoring any setting on the device from the user,
1933 * Otherwise, lock in the requested de-interlace mode.
1934 */
1935 if (q_data->format.field == V4L2_FIELD_NONE)
1936 ctx->deint_mode = FDP1_PROGRESSIVE;
1937
1938 if (ctx->deint_mode == FDP1_ADAPT2D3D) {
1939 u32 stride;
1940 dma_addr_t smsk_base;
1941 const u32 bpp = 2; /* bytes per pixel */
1942
1943 stride = round_up(q_data->format.width, 8);
1944
1945 ctx->smsk_size = bpp * stride * q_data->vsize;
1946
1947 ctx->smsk_cpu = dma_alloc_coherent(ctx->fdp1->dev,
1948 ctx->smsk_size, &smsk_base, GFP_KERNEL);
1949
1950 if (ctx->smsk_cpu == NULL) {
1951 dprintk(ctx->fdp1, "Failed to alloc smsk\n");
1952 return -ENOMEM;
1953 }
1954
1955 ctx->smsk_addr[0] = smsk_base;
1956 ctx->smsk_addr[1] = smsk_base + (ctx->smsk_size/2);
1957 }
1958 }
1959
1960 return 0;
1961 }
1962
1963 static void fdp1_stop_streaming(struct vb2_queue *q)
1964 {
1965 struct fdp1_ctx *ctx = vb2_get_drv_priv(q);
1966 struct vb2_v4l2_buffer *vbuf;
1967 unsigned long flags;
1968
1969 while (1) {
1970 if (V4L2_TYPE_IS_OUTPUT(q->type))
1971 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1972 else
1973 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1974 if (vbuf == NULL)
1975 break;
1976 spin_lock_irqsave(&ctx->fdp1->irqlock, flags);
1977 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
1978 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags);
1979 }
1980
1981 /* Empty Output queues */
1982 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
1983 /* Empty our internal queues */
1984 struct fdp1_field_buffer *fbuf;
1985
1986 /* Free any queued buffers */
1987 fbuf = fdp1_dequeue_field(ctx);
1988 while (fbuf != NULL) {
1989 fdp1_field_complete(ctx, fbuf);
1990 fbuf = fdp1_dequeue_field(ctx);
1991 }
1992
1993 /* Free smsk_data */
1994 if (ctx->smsk_cpu) {
1995 dma_free_coherent(ctx->fdp1->dev, ctx->smsk_size,
1996 ctx->smsk_cpu, ctx->smsk_addr[0]);
1997 ctx->smsk_addr[0] = ctx->smsk_addr[1] = 0;
1998 ctx->smsk_cpu = NULL;
1999 }
2000
2001 WARN(!list_empty(&ctx->fields_queue),
2002 "Buffer queue not empty");
2003 } else {
2004 /* Empty Capture queues (Jobs) */
2005 struct fdp1_job *job;
2006
2007 job = get_queued_job(ctx->fdp1);
2008 while (job) {
2009 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode))
2010 fdp1_field_complete(ctx, job->previous);
2011 else
2012 fdp1_field_complete(ctx, job->active);
2013
2014 v4l2_m2m_buf_done(job->dst->vb, VB2_BUF_STATE_ERROR);
2015 job->dst = NULL;
2016
2017 job = get_queued_job(ctx->fdp1);
2018 }
2019
2020 /* Free any held buffer in the ctx */
2021 fdp1_field_complete(ctx, ctx->previous);
2022
2023 WARN(!list_empty(&ctx->fdp1->queued_job_list),
2024 "Queued Job List not empty");
2025
2026 WARN(!list_empty(&ctx->fdp1->hw_job_list),
2027 "HW Job list not empty");
2028 }
2029 }
2030
2031 static const struct vb2_ops fdp1_qops = {
2032 .queue_setup = fdp1_queue_setup,
2033 .buf_prepare = fdp1_buf_prepare,
2034 .buf_queue = fdp1_buf_queue,
2035 .start_streaming = fdp1_start_streaming,
2036 .stop_streaming = fdp1_stop_streaming,
2037 .wait_prepare = vb2_ops_wait_prepare,
2038 .wait_finish = vb2_ops_wait_finish,
2039 };
2040
2041 static int queue_init(void *priv, struct vb2_queue *src_vq,
2042 struct vb2_queue *dst_vq)
2043 {
2044 struct fdp1_ctx *ctx = priv;
2045 int ret;
2046
2047 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2048 src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
2049 src_vq->drv_priv = ctx;
2050 src_vq->buf_struct_size = sizeof(struct fdp1_buffer);
2051 src_vq->ops = &fdp1_qops;
2052 src_vq->mem_ops = &vb2_dma_contig_memops;
2053 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2054 src_vq->lock = &ctx->fdp1->dev_mutex;
2055 src_vq->dev = ctx->fdp1->dev;
2056
2057 ret = vb2_queue_init(src_vq);
2058 if (ret)
2059 return ret;
2060
2061 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2062 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
2063 dst_vq->drv_priv = ctx;
2064 dst_vq->buf_struct_size = sizeof(struct fdp1_buffer);
2065 dst_vq->ops = &fdp1_qops;
2066 dst_vq->mem_ops = &vb2_dma_contig_memops;
2067 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2068 dst_vq->lock = &ctx->fdp1->dev_mutex;
2069 dst_vq->dev = ctx->fdp1->dev;
2070
2071 return vb2_queue_init(dst_vq);
2072 }
2073
2074 /*
2075 * File operations
2076 */
2077 static int fdp1_open(struct file *file)
2078 {
2079 struct fdp1_dev *fdp1 = video_drvdata(file);
2080 struct v4l2_pix_format_mplane format;
2081 struct fdp1_ctx *ctx = NULL;
2082 struct v4l2_ctrl *ctrl;
2083 int ret = 0;
2084
2085 if (mutex_lock_interruptible(&fdp1->dev_mutex))
2086 return -ERESTARTSYS;
2087
2088 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2089 if (!ctx) {
2090 ret = -ENOMEM;
2091 goto done;
2092 }
2093
2094 v4l2_fh_init(&ctx->fh, video_devdata(file));
2095 file->private_data = &ctx->fh;
2096 ctx->fdp1 = fdp1;
2097
2098 /* Initialise Queues */
2099 INIT_LIST_HEAD(&ctx->fields_queue);
2100
2101 ctx->translen = 1;
2102 ctx->sequence = 0;
2103
2104 /* Initialise controls */
2105
2106 v4l2_ctrl_handler_init(&ctx->hdl, 3);
2107 v4l2_ctrl_new_std_menu_items(&ctx->hdl, &fdp1_ctrl_ops,
2108 V4L2_CID_DEINTERLACING_MODE,
2109 FDP1_NEXTFIELD, BIT(0), FDP1_FIXED3D,
2110 fdp1_ctrl_deint_menu);
2111
2112 ctrl = v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops,
2113 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 2, 1, 1);
2114 if (ctrl)
2115 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2116
2117 v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops,
2118 V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 255);
2119
2120 if (ctx->hdl.error) {
2121 ret = ctx->hdl.error;
2122 v4l2_ctrl_handler_free(&ctx->hdl);
2123 goto done;
2124 }
2125
2126 ctx->fh.ctrl_handler = &ctx->hdl;
2127 v4l2_ctrl_handler_setup(&ctx->hdl);
2128
2129 /* Configure default parameters. */
2130 memset(&format, 0, sizeof(format));
2131 fdp1_set_format(ctx, &format, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
2132
2133 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(fdp1->m2m_dev, ctx, &queue_init);
2134
2135 if (IS_ERR(ctx->fh.m2m_ctx)) {
2136 ret = PTR_ERR(ctx->fh.m2m_ctx);
2137
2138 v4l2_ctrl_handler_free(&ctx->hdl);
2139 kfree(ctx);
2140 goto done;
2141 }
2142
2143 /* Perform any power management required */
2144 pm_runtime_get_sync(fdp1->dev);
2145
2146 v4l2_fh_add(&ctx->fh);
2147
2148 dprintk(fdp1, "Created instance: %p, m2m_ctx: %p\n",
2149 ctx, ctx->fh.m2m_ctx);
2150
2151 done:
2152 mutex_unlock(&fdp1->dev_mutex);
2153 return ret;
2154 }
2155
2156 static int fdp1_release(struct file *file)
2157 {
2158 struct fdp1_dev *fdp1 = video_drvdata(file);
2159 struct fdp1_ctx *ctx = fh_to_ctx(file->private_data);
2160
2161 dprintk(fdp1, "Releasing instance %p\n", ctx);
2162
2163 v4l2_fh_del(&ctx->fh);
2164 v4l2_fh_exit(&ctx->fh);
2165 v4l2_ctrl_handler_free(&ctx->hdl);
2166 mutex_lock(&fdp1->dev_mutex);
2167 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2168 mutex_unlock(&fdp1->dev_mutex);
2169 kfree(ctx);
2170
2171 pm_runtime_put(fdp1->dev);
2172
2173 return 0;
2174 }
2175
2176 static const struct v4l2_file_operations fdp1_fops = {
2177 .owner = THIS_MODULE,
2178 .open = fdp1_open,
2179 .release = fdp1_release,
2180 .poll = v4l2_m2m_fop_poll,
2181 .unlocked_ioctl = video_ioctl2,
2182 .mmap = v4l2_m2m_fop_mmap,
2183 };
2184
2185 static const struct video_device fdp1_videodev = {
2186 .name = DRIVER_NAME,
2187 .vfl_dir = VFL_DIR_M2M,
2188 .fops = &fdp1_fops,
2189 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING,
2190 .ioctl_ops = &fdp1_ioctl_ops,
2191 .minor = -1,
2192 .release = video_device_release_empty,
2193 };
2194
2195 static const struct v4l2_m2m_ops m2m_ops = {
2196 .device_run = fdp1_m2m_device_run,
2197 .job_ready = fdp1_m2m_job_ready,
2198 .job_abort = fdp1_m2m_job_abort,
2199 };
2200
2201 static irqreturn_t fdp1_irq_handler(int irq, void *dev_id)
2202 {
2203 struct fdp1_dev *fdp1 = dev_id;
2204 u32 int_status;
2205 u32 ctl_status;
2206 u32 vint_cnt;
2207 u32 cycles;
2208
2209 int_status = fdp1_read(fdp1, FD1_CTL_IRQSTA);
2210 cycles = fdp1_read(fdp1, FD1_CTL_VCYCLE_STAT);
2211 ctl_status = fdp1_read(fdp1, FD1_CTL_STATUS);
2212 vint_cnt = (ctl_status & FD1_CTL_STATUS_VINT_CNT_MASK) >>
2213 FD1_CTL_STATUS_VINT_CNT_SHIFT;
2214
2215 /* Clear interrupts */
2216 fdp1_write(fdp1, ~(int_status) & FD1_CTL_IRQ_MASK, FD1_CTL_IRQSTA);
2217
2218 if (debug >= 2) {
2219 dprintk(fdp1, "IRQ: 0x%x %s%s%s\n", int_status,
2220 int_status & FD1_CTL_IRQ_VERE ? "[Error]" : "[!E]",
2221 int_status & FD1_CTL_IRQ_VINTE ? "[VSync]" : "[!V]",
2222 int_status & FD1_CTL_IRQ_FREE ? "[FrameEnd]" : "[!F]");
2223
2224 dprintk(fdp1, "CycleStatus = %d (%dms)\n",
2225 cycles, cycles/(fdp1->clk_rate/1000));
2226
2227 dprintk(fdp1,
2228 "Control Status = 0x%08x : VINT_CNT = %d %s:%s:%s:%s\n",
2229 ctl_status, vint_cnt,
2230 ctl_status & FD1_CTL_STATUS_SGREGSET ? "RegSet" : "",
2231 ctl_status & FD1_CTL_STATUS_SGVERR ? "Vsync Error" : "",
2232 ctl_status & FD1_CTL_STATUS_SGFREND ? "FrameEnd" : "",
2233 ctl_status & FD1_CTL_STATUS_BSY ? "Busy" : "");
2234 dprintk(fdp1, "***********************************\n");
2235 }
2236
2237 /* Spurious interrupt */
2238 if (!(FD1_CTL_IRQ_MASK & int_status))
2239 return IRQ_NONE;
2240
2241 /* Work completed, release the frame */
2242 if (FD1_CTL_IRQ_VERE & int_status)
2243 device_frame_end(fdp1, VB2_BUF_STATE_ERROR);
2244 else if (FD1_CTL_IRQ_FREE & int_status)
2245 device_frame_end(fdp1, VB2_BUF_STATE_DONE);
2246
2247 return IRQ_HANDLED;
2248 }
2249
2250 static int fdp1_probe(struct platform_device *pdev)
2251 {
2252 struct fdp1_dev *fdp1;
2253 struct video_device *vfd;
2254 struct device_node *fcp_node;
2255 struct resource *res;
2256 struct clk *clk;
2257 unsigned int i;
2258
2259 int ret;
2260 int hw_version;
2261
2262 fdp1 = devm_kzalloc(&pdev->dev, sizeof(*fdp1), GFP_KERNEL);
2263 if (!fdp1)
2264 return -ENOMEM;
2265
2266 INIT_LIST_HEAD(&fdp1->free_job_list);
2267 INIT_LIST_HEAD(&fdp1->queued_job_list);
2268 INIT_LIST_HEAD(&fdp1->hw_job_list);
2269
2270 /* Initialise the jobs on the free list */
2271 for (i = 0; i < ARRAY_SIZE(fdp1->jobs); i++)
2272 list_add(&fdp1->jobs[i].list, &fdp1->free_job_list);
2273
2274 mutex_init(&fdp1->dev_mutex);
2275
2276 spin_lock_init(&fdp1->irqlock);
2277 spin_lock_init(&fdp1->device_process_lock);
2278 fdp1->dev = &pdev->dev;
2279 platform_set_drvdata(pdev, fdp1);
2280
2281 /* Memory-mapped registers */
2282 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2283 fdp1->regs = devm_ioremap_resource(&pdev->dev, res);
2284 if (IS_ERR(fdp1->regs))
2285 return PTR_ERR(fdp1->regs);
2286
2287 /* Interrupt service routine registration */
2288 fdp1->irq = ret = platform_get_irq(pdev, 0);
2289 if (ret < 0) {
2290 dev_err(&pdev->dev, "cannot find IRQ\n");
2291 return ret;
2292 }
2293
2294 ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0,
2295 dev_name(&pdev->dev), fdp1);
2296 if (ret) {
2297 dev_err(&pdev->dev, "cannot claim IRQ %d\n", fdp1->irq);
2298 return ret;
2299 }
2300
2301 /* FCP */
2302 fcp_node = of_parse_phandle(pdev->dev.of_node, "renesas,fcp", 0);
2303 if (fcp_node) {
2304 fdp1->fcp = rcar_fcp_get(fcp_node);
2305 of_node_put(fcp_node);
2306 if (IS_ERR(fdp1->fcp)) {
2307 dev_err(&pdev->dev, "FCP not found (%ld)\n",
2308 PTR_ERR(fdp1->fcp));
2309 return PTR_ERR(fdp1->fcp);
2310 }
2311 }
2312
2313 /* Determine our clock rate */
2314 clk = clk_get(&pdev->dev, NULL);
2315 if (IS_ERR(clk))
2316 return PTR_ERR(clk);
2317
2318 fdp1->clk_rate = clk_get_rate(clk);
2319 clk_put(clk);
2320
2321 /* V4L2 device registration */
2322 ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev);
2323 if (ret) {
2324 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n");
2325 return ret;
2326 }
2327
2328 /* M2M registration */
2329 fdp1->m2m_dev = v4l2_m2m_init(&m2m_ops);
2330 if (IS_ERR(fdp1->m2m_dev)) {
2331 v4l2_err(&fdp1->v4l2_dev, "Failed to init mem2mem device\n");
2332 ret = PTR_ERR(fdp1->m2m_dev);
2333 goto unreg_dev;
2334 }
2335
2336 /* Video registration */
2337 fdp1->vfd = fdp1_videodev;
2338 vfd = &fdp1->vfd;
2339 vfd->lock = &fdp1->dev_mutex;
2340 vfd->v4l2_dev = &fdp1->v4l2_dev;
2341 video_set_drvdata(vfd, fdp1);
2342 strlcpy(vfd->name, fdp1_videodev.name, sizeof(vfd->name));
2343
2344 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2345 if (ret) {
2346 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n");
2347 goto release_m2m;
2348 }
2349
2350 v4l2_info(&fdp1->v4l2_dev,
2351 "Device registered as /dev/video%d\n", vfd->num);
2352
2353 /* Power up the cells to read HW */
2354 pm_runtime_enable(&pdev->dev);
2355 pm_runtime_get_sync(fdp1->dev);
2356
2357 hw_version = fdp1_read(fdp1, FD1_IP_INTDATA);
2358 switch (hw_version) {
2359 case FD1_IP_H3_ES1:
2360 dprintk(fdp1, "FDP1 Version R-Car H3 ES1\n");
2361 break;
2362 case FD1_IP_M3W:
2363 dprintk(fdp1, "FDP1 Version R-Car M3-W\n");
2364 break;
2365 case FD1_IP_H3:
2366 dprintk(fdp1, "FDP1 Version R-Car H3\n");
2367 break;
2368 default:
2369 dev_err(fdp1->dev, "FDP1 Unidentifiable (0x%08x)\n",
2370 hw_version);
2371 }
2372
2373 /* Allow the hw to sleep until an open call puts it to use */
2374 pm_runtime_put(fdp1->dev);
2375
2376 return 0;
2377
2378 release_m2m:
2379 v4l2_m2m_release(fdp1->m2m_dev);
2380
2381 unreg_dev:
2382 v4l2_device_unregister(&fdp1->v4l2_dev);
2383
2384 return ret;
2385 }
2386
2387 static int fdp1_remove(struct platform_device *pdev)
2388 {
2389 struct fdp1_dev *fdp1 = platform_get_drvdata(pdev);
2390
2391 v4l2_m2m_release(fdp1->m2m_dev);
2392 video_unregister_device(&fdp1->vfd);
2393 v4l2_device_unregister(&fdp1->v4l2_dev);
2394 pm_runtime_disable(&pdev->dev);
2395
2396 return 0;
2397 }
2398
2399 static int __maybe_unused fdp1_pm_runtime_suspend(struct device *dev)
2400 {
2401 struct fdp1_dev *fdp1 = dev_get_drvdata(dev);
2402
2403 rcar_fcp_disable(fdp1->fcp);
2404
2405 return 0;
2406 }
2407
2408 static int __maybe_unused fdp1_pm_runtime_resume(struct device *dev)
2409 {
2410 struct fdp1_dev *fdp1 = dev_get_drvdata(dev);
2411
2412 /* Program in the static LUTs */
2413 fdp1_set_lut(fdp1);
2414
2415 return rcar_fcp_enable(fdp1->fcp);
2416 }
2417
2418 static const struct dev_pm_ops fdp1_pm_ops = {
2419 SET_RUNTIME_PM_OPS(fdp1_pm_runtime_suspend,
2420 fdp1_pm_runtime_resume,
2421 NULL)
2422 };
2423
2424 static const struct of_device_id fdp1_dt_ids[] = {
2425 { .compatible = "renesas,fdp1" },
2426 { },
2427 };
2428 MODULE_DEVICE_TABLE(of, fdp1_dt_ids);
2429
2430 static struct platform_driver fdp1_pdrv = {
2431 .probe = fdp1_probe,
2432 .remove = fdp1_remove,
2433 .driver = {
2434 .name = DRIVER_NAME,
2435 .of_match_table = fdp1_dt_ids,
2436 .pm = &fdp1_pm_ops,
2437 },
2438 };
2439
2440 module_platform_driver(fdp1_pdrv);
2441
2442 MODULE_DESCRIPTION("Renesas R-Car Fine Display Processor Driver");
2443 MODULE_AUTHOR("Kieran Bingham <kieran@bingham.xyz>");
2444 MODULE_LICENSE("GPL");
2445 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support