arch/arm/mach-imx/mach-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/i2c-gpio.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/can/platform/mcp251x.h>
  28
  29 #include <asm/setup.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/mach/arch.h>
  32 #include <asm/mach/time.h>
  33
  34 #include "common.h"
  35 #include "devices-imx51.h"
  36 #include "eukrea-baseboards.h"
  37 #include "hardware.h"
  38 #include "iomux-mx51.h"
  39
  40 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  41 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  42 #define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
  43 #define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
  44 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  45 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  46 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  47 #define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
  48 #define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
  49 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  50 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  51 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  52 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  53 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  54 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  55
  56 /* USB_CTRL_1 */
  57 #define MX51_USB_CTRL_1_OFFSET          0x10
  58 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  59
  60 #define MX51_USB_PLLDIV_12_MHZ          0x00
  61 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  62 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  63
  64 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  65         /* UART1 */
  66         MX51_PAD_UART1_RXD__UART1_RXD,
  67         MX51_PAD_UART1_TXD__UART1_TXD,
  68         MX51_PAD_UART1_RTS__UART1_RTS,
  69         MX51_PAD_UART1_CTS__UART1_CTS,
  70
  71         /* USB HOST1 */
  72         MX51_PAD_USBH1_CLK__USBH1_CLK,
  73         MX51_PAD_USBH1_DIR__USBH1_DIR,
  74         MX51_PAD_USBH1_NXT__USBH1_NXT,
  75         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  76         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  77         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  78         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  79         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  80         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  81         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  82         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  83         MX51_PAD_USBH1_STP__USBH1_STP,
  84         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  85
  86         /* FEC */
  87         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  88
  89         /* HSI2C */
  90         MX51_PAD_I2C1_CLK__GPIO4_16,
  91         MX51_PAD_I2C1_DAT__GPIO4_17,
  92
  93         /* I2C1 */
  94         MX51_PAD_SD2_CMD__I2C1_SCL,
  95         MX51_PAD_SD2_CLK__I2C1_SDA,
  96
  97         /* CAN */
  98         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
  99         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 100         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 101         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 102         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 103         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 104         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 105         MX51_PAD_GPIO1_6__GPIO1_6,
 106         MX51_PAD_GPIO1_7__GPIO1_7,
 107         MX51_PAD_GPIO1_8__GPIO1_8,
 108         MX51_PAD_GPIO1_9__GPIO1_9,
 109
 110         /* Touchscreen */
 111         /* IRQ */
 112         NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
 113                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 114                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 115         NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
 116                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 117                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 118 };
 119
 120 static const struct imxuart_platform_data uart_pdata __initconst = {
 121         .flags = IMXUART_HAVE_RTSCTS,
 122 };
 123
 124 static int tsc2007_get_pendown_state(void)
 125 {
 126         if (mx51_revision() < IMX_CHIP_REVISION_3_0)
 127                 return !gpio_get_value(TSC2007_IRQGPIO_REV2);
 128         else
 129                 return !gpio_get_value(TSC2007_IRQGPIO_REV3);
 130 }
 131
 132 static struct tsc2007_platform_data tsc2007_info = {
 133         .model                  = 2007,
 134         .x_plate_ohms           = 180,
 135         .get_pendown_state      = tsc2007_get_pendown_state,
 136 };
 137
 138 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 139         {
 140                 I2C_BOARD_INFO("pcf8563", 0x51),
 141         }, {
 142                 I2C_BOARD_INFO("tsc2007", 0x49),
 143                 .platform_data  = &tsc2007_info,
 144         },
 145 };
 146
 147 static const struct mxc_nand_platform_data
 148                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 149         .width          = 1,
 150         .hw_ecc         = 1,
 151         .flash_bbt      = 1,
 152 };
 153
 154 /* This function is board specific as the bit mask for the plldiv will also
 155 be different for other Freescale SoCs, thus a common bitmask is not
 156 possible and cannot get place in /plat-mxc/ehci.c.*/
 157 static int initialize_otg_port(struct platform_device *pdev)
 158 {
 159         u32 v;
 160         void __iomem *usb_base;
 161         void __iomem *usbother_base;
 162
 163         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 164         if (!usb_base)
 165                 return -ENOMEM;
 166         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 167
 168         /* Set the PHY clock to 19.2MHz */
 169         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 170         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 171         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 172         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 173         iounmap(usb_base);
 174
 175         mdelay(10);
 176
 177         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 178 }
 179
 180 static int initialize_usbh1_port(struct platform_device *pdev)
 181 {
 182         u32 v;
 183         void __iomem *usb_base;
 184         void __iomem *usbother_base;
 185
 186         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 187         if (!usb_base)
 188                 return -ENOMEM;
 189         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 190
 191         /* The clock for the USBH1 ULPI port will come from the PHY. */
 192         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 193         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 194                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 195         iounmap(usb_base);
 196
 197         mdelay(10);
 198
 199         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 200                         MXC_EHCI_ITC_NO_THRESHOLD);
 201 }
 202
 203 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
 204         .init           = initialize_otg_port,
 205         .portsc = MXC_EHCI_UTMI_16BIT,
 206 };
 207
 208 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 209         .operating_mode = FSL_USB2_DR_DEVICE,
 210         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 211 };
 212
 213 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
 214         .init           = initialize_usbh1_port,
 215         .portsc = MXC_EHCI_MODE_ULPI,
 216 };
 217
 218 static bool otg_mode_host __initdata;
 219
 220 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 221 {
 222         if (!strcmp(options, "host"))
 223                 otg_mode_host = true;
 224         else if (!strcmp(options, "device"))
 225                 otg_mode_host = false;
 226         else
 227                 pr_info("otg_mode neither \"host\" nor \"device\". "
 228                         "Defaulting to device\n");
 229         return 1;
 230 }
 231 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 232
 233 static struct i2c_gpio_platform_data pdata = {
 234         .sda_pin                = I2C_SDA,
 235         .sda_is_open_drain      = 0,
 236         .scl_pin                = I2C_SCL,
 237         .scl_is_open_drain      = 0,
 238         .udelay                 = 2,
 239 };
 240
 241 static struct platform_device hsi2c_gpio_device = {
 242         .name                   = "i2c-gpio",
 243         .id                     = 0,
 244         .dev.platform_data      = &pdata,
 245 };
 246
 247 static struct mcp251x_platform_data mcp251x_info = {
 248         .oscillator_frequency = 24E6,
 249 };
 250
 251 static struct spi_board_info cpuimx51sd_spi_device[] = {
 252         {
 253                 .modalias        = "mcp2515",
 254                 .max_speed_hz    = 10000000,
 255                 .bus_num         = 0,
 256                 .mode           = SPI_MODE_0,
 257                 .chip_select     = 0,
 258                 .platform_data   = &mcp251x_info,
 259                 /* irq number is run-time assigned */
 260         },
 261 };
 262
 263 static int cpuimx51sd_spi1_cs[] = {
 264         CAN_NCS,
 265 };
 266
 267 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 268         .chipselect     = cpuimx51sd_spi1_cs,
 269         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 270 };
 271
 272 static struct platform_device *rev2_platform_devices[] __initdata = {
 273         &hsi2c_gpio_device,
 274 };
 275
 276 static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
 277         .bitrate = 100000,
 278 };
 279
 280 static void __init eukrea_cpuimx51sd_init(void)
 281 {
 282         imx51_soc_init();
 283
 284         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 285                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 286
 287         imx51_add_imx_uart(0, &uart_pdata);
 288         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 289         imx51_add_imx2_wdt(0);
 290
 291         gpio_request(ETH_RST, "eth_rst");
 292         gpio_set_value(ETH_RST, 1);
 293         imx51_add_fec(NULL);
 294
 295         gpio_request(CAN_IRQGPIO, "can_irq");
 296         gpio_direction_input(CAN_IRQGPIO);
 297         gpio_free(CAN_IRQGPIO);
 298         gpio_request(CAN_NCS, "can_ncs");
 299         gpio_direction_output(CAN_NCS, 1);
 300         gpio_free(CAN_NCS);
 301         gpio_request(CAN_RST, "can_rst");
 302         gpio_direction_output(CAN_RST, 0);
 303         msleep(20);
 304         gpio_set_value(CAN_RST, 1);
 305         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 306         cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
 307         spi_register_board_info(cpuimx51sd_spi_device,
 308                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 309
 310         if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
 311                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 312                         gpio_to_irq(TSC2007_IRQGPIO_REV2),
 313                 platform_add_devices(rev2_platform_devices,
 314                         ARRAY_SIZE(rev2_platform_devices));
 315                 gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
 316                 gpio_direction_input(TSC2007_IRQGPIO_REV2);
 317                 gpio_free(TSC2007_IRQGPIO_REV2);
 318         } else {
 319                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 320                         gpio_to_irq(TSC2007_IRQGPIO_REV3),
 321                 imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
 322                 gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
 323                 gpio_direction_input(TSC2007_IRQGPIO_REV3);
 324                 gpio_free(TSC2007_IRQGPIO_REV3);
 325         }
 326
 327         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 328                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 329
 330         if (otg_mode_host)
 331                 imx51_add_mxc_ehci_otg(&dr_utmi_config);
 332         else {
 333                 initialize_otg_port(NULL);
 334                 imx51_add_fsl_usb2_udc(&usb_pdata);
 335         }
 336
 337         gpio_request(USBH1_RST, "usb_rst");
 338         gpio_direction_output(USBH1_RST, 0);
 339         msleep(20);
 340         gpio_set_value(USBH1_RST, 1);
 341         imx51_add_mxc_ehci_hs(1, &usbh1_config);
 342
 343 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 344         eukrea_mbimxsd51_baseboard_init();
 345 #endif
 346 }
 347
 348 static void __init eukrea_cpuimx51sd_timer_init(void)
 349 {
 350         mx51_clocks_init(32768, 24000000, 22579200, 0);
 351 }
 352
 353 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 354         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 355         .atag_offset = 0x100,
 356         .map_io = mx51_map_io,
 357         .init_early = imx51_init_early,
 358         .init_irq = mx51_init_irq,
 359         .handle_irq = imx51_handle_irq,
 360         .init_time      = eukrea_cpuimx51sd_timer_init,
 361         .init_machine = eukrea_cpuimx51sd_init,
 362         .init_late      = imx51_init_late,
 363         .restart        = mxc_restart,
 364 MACHINE_END